KM736V799H-57_技术文档

KM736V799

128Kx36 Synchronous SRAM

Document Title

128Kx36-Bit Synchronous Pipelined Burst SRAM

Revision History

Remark

Rev. No

History

Draft Date

Preliminary

0.0

0.1

Initial draft

April . 14. 1998

April . 20. 1998

Change Undershoot spec

from -3.0V(pulse width£20ns) to -2.0V(pulse width£tCYC/2)

Add Overshoot spec 4.6V(pulse width£tCYC/2)

Change VIH max from 5.5V to VDD+0.5V

Preliminary

0.2

Change tCD from 3.2ns to 3.1ns at bin -50.

Change tOE from 3.2ns to 3.1ns at bin -50.

Change setup from 1.5ns to 1.4ns at bin -50.

Change tCYC from 5.5ns to 5.4ns at bin -55.

May . 23. 1998

May . 25. 1998

0.3

Change tCD from 3.5ns to 3.1ns at bin -55.

Change tOE from 3.5ns to 3.1ns at bin -55.

Change setup from 1.5ns to 1.4ns at bin -55.

.

Preliminary

0.4

Add tCYC 175Mhz.

Change ISB2 from 20mA to 30mA.

May . 30. 1998

June. 08. 1998

0.5

Modify DC characteristics( Input Leakage Current test Conditions)

form VDD=VSS to VDD to Max.

Final

Fianl

1.0

2.0

3.0

4.0

Final Release.

June. 15 . 1998

July. 10 . 1998

Dec. 02. 1998

Mar. 04. 1999

Add tCYC 225Mhz.

Add VDDQ Supply voltage( 2.5V )

Change tCD , tOE from 3.1ns to 2.8ns at bin -44.

Change tHZC max , tHZOE max from 3.0ns to 2.8ns at bin -44.

Final

5.0

6.0

7.0

Add tCYC 250Mhz.

April. 10. 1999

May. 03. 1999

May. 10. 1999

Change tAH, tSH, tDH, tWH, tADVH, tCSH from 0.5ns to 0.4ns at bin -40.

1. Change tAS, tSS, tDS, tWS, tADVS, tCSS from 1.4ns to 1.2ns at bin -44.

2. Change tAH, tSH, tDH, tWH, tADVH, tCSH from 0.5ns to 0.4ns at bin -44.

3. Change tAS, tSS, tDS, tWS, tADVS, tCSS from 1.2ns to 0.8ns at bin -40.

4. Change tAH, tSH, tDH, tWH, tADVH, tCSH from 0.4ns to 0.3ns at bin -40.

Final

8.0

1. Change ISB value from 120mA to 130mA at -57

June. 24. 1999

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

- 1 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

128Kx36-Bit Synchronous Pipelined Burst SRAM

FEATURES

GENERAL DESCRIPTION

• Synchronous Operation.

• 2 Stage Pipelined operation with 4 Burst.

• On-Chip Address Counter.

The KM736V799 is a 4,718,592-bit Synchronous Static Ran-

dom Access Memory designed for high performance second

level cache of Pentium and Power PC based System.

It is organized as 128K words of 36bits and integrates address

and control registers, a 2-bit burst address counter and added

some new functions for high performance cache RAM applica-

tions; GW, BW, LBO, ZZ. Write cycles are internally self-timed

and synchronous.

• Self-Timed Write Cycle.

• On-Chip Address and Control Registers.

• VDD= 3.3V+0.165V/-0.165V Power Supply.

• VDDQ Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O

or 2.5V+0.4V/-0.125V for 2.5V I/O.

• 5V Tolerant Inputs Except I/O Pins.

• Byte Writable Function.

• Global Write Enable Controls a full bus-width write.

• Power Down State via ZZ Signal.

• LBO Pin allows a choice of either a interleaved burst or a lin-

ear burst.

• Three Chip Enables for simple depth expansion with No Data

Contention ; 2cycle Enable, 1cycle Disable.

• Asynchronous Output Enable Control.

• ADSP, ADSC, ADV Burst Control Pins.

• TTL-Level Three-State Output.

Full bus-width write is done by GW, and each byte write is per-

formed by the combination of WEx and BW when GW is high.

And with CS1 high, ADSP is blocked to control signals.

Burst cycle can be initiated with either the address status pro-

cessor(ADSP) or address status cache controller(ADSC)

inputs. Subsequent burst addresses are generated internally in

the system¢s burst sequence and are controlled by the burst

address advance(ADV) input.

LBO pin is DC operated and determines burst sequence(linear

or interleaved).

• 100-TQFP-1420A / 119BGA(7x17 Ball Grid Array Package)

ZZ pin controls Power Down State and reduces Stand-by cur-

rent regardless of CLK.

The KM736V799 is fabricated using SAMSUNG¢s high perfor-

mance CMOS technology and is available in a 100pin TQFP

and 119BGA package. Multiple power and ground pins are uti-

lized to minimize ground bounce.

FAST ACCESS TIMES

Symbol -40 -44 -50 -55 -57 Unit

PARAMETER

Cycle Time

Clock Access Time

4.0 4.4 5.0 5.4 5.7

2.5 2.8 3.1 3.1 3.3

2.8 2.8 3.1 3.1 3.3

tCYC

tCD

ns

Output Enable Access Time tOE

LOGIC BLOCK DIAGRAM

CLK

LBO

128Kx36

BURST CONTROL

LOGIC

BURST

MEMORY

ADDRESS

COUNTER

ADV

ADSC

A¢0~A¢1

ARRAY

A0~A1

A2~A16

ADDRESS

REGISTER

A0~A16

ADSP

DATA-IN

REGISTER

CS

1

2

GW

BW

WEa

WEb

WEc

WEd

OUTPUT

REGISTER

CONTROL

LOGIC

BUFFER

OE

ZZ

DQa

0 ~ DQd7

DQPa ~ DQPd

- 2 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

PIN CONFIGURATION(TOP VIEW)

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQPb

DQb7

DQb6

VDDQ

VSSQ

DQb5

DQb4

DQb3

DQb2

VSSQ

VDDQ

DQb1

DQb0

VSS

DQPc

DQc0

DQc1

VDDQ

VSSQ

DQc2

DQc3

DQc4

DQc5

VSSQ

VDDQ

DQc6

DQc7

N.C.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100 Pin

TQFP

(20mm x 14mm)

N.C.

VDD

ZZ

VDD

N.C.

VSS

DQd0

DQd1

VDDQ

VSSQ

DQd2

DQd3

DQd4

DQd5

VSSQ

VDDQ

DQd6

DQd7

DQPd

DQa7

DQa6

VDDQ

VSSQ

DQa5

DQa4

DQa3

DQa2

VSSQ

VDDQ

DQa1

DQa0

DQPa

PIN NAME

SYMBOL

PIN NAME

TQFP PIN NO.

SYMBOL

PIN NAME

TQFP PIN NO.

A0 - A16

Address Inputs

32,33,34,35,36,37

44,45,46,47,48,49

50,81,82,99,100

83

VDD

VSS

Power Supply(+3.3V)

Ground

15,41,65,91

17,40,67,90

ADV

ADSP

ADSC

CLK

CS1

Burst Address Advance

Address Status Processor 84

Address Status Controller 85

No Connect

14,16,38,39,42,43,66

N.C.

Data Inputs/Outputs

52,53,56,57,58,59,62,63

68,69,72,73,74,75,78,79

2,3,6,7,8,9,12,13

18,19,22,23,24,25,28,29

51,80,1,30

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

Clock

89

98

97

92

Chip Select

CS2

WEx(x=a,b,c,d) Byte Write Inputs

93,94,95,96

OE

Output Enable

86

88

87

64

31

Output Power Supply

(2.5V or 3.3V)

Output Ground

4,11,20,27,54,61,70,77

5,10,21,26,55,60,71,76

VDDQ

VSSQ

GW

BW

ZZ

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

LBO

- 3 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW)

KM736V799(128Kx36)

1

2

3

4

ADSP

ADSC

VDD

NC

5

6

7

A

B

C

D

E

F

VDDQ

NC

A13

A10

A9

A7

A4

VDDQ

NC

CS2

A8

CS2

NC

A12

A11

VSS

WEc

VSS

NC

A6

A5

NC

DQc7

DQc5

VDDQ

DQc2

DQc0

VDDQ

DQd0

DQd2

VDDQ

DQd5

DQd7

NC

DQPc

DQc6

DQc4

DQc3

DQc1

VDD

VSS

WEb

VSS

NC

VSS

WEa

VSS

NC

A3

DQPb

DQb6

DQb4

DQb3

DQb1

VDD

DQb7

DQb5

VDDQ

DQb2

DQb0

VDDQ

DQa0

DQa2

VDDQ

DQa5

DQa7

NC

CS1

OE

G

H

J

ADV

GW

VDD

CLK

NC

K

L

DQd1

DQd3

DQd4

DQd6

DQPd

A15

VSS

WEd

VSS

LBO

A14

NC

DQa1

DQa3

DQa4

DQa6

DQPa

A2

M

N

P

R

T

BW

A1

A0

VDD

A16

NC

ZZ

U

VDDQ

NC

VDDQ

PIN NAME

SYMBOL

PIN NAME

Address Inputs

BGA PIN NO.

SYMBOL

PIN NAME

BGA PIN NO.

A0 - A16

4P,4N,6R,5T,6A,6C VDD

5C,5A,5B,3B,3A,3C VSS

2C,2A,3T,2R,4T

Power Supply(+3.3V) 4C,2J,4J,6J,4R

Ground

3D,5D,3E,5E,3F,5F,3H,5H

3K,5K,3M,5M,3N,5N,3P,5P

1B,7B,1C,7C,4D,3J,5J,4L

1R,5R,7R,1T,2T,6T,2U,3U

4U,5U,6U

7K,6K,7L,6L,6M,6N,7N,7P

7H,6H,7G,6G,6F,7E,6E,7D

1H,2H,1G,2G,2F,1E,2E,1D

1K,2K,1L,2L,2M,1N,2N,1P

6P,6D,2D,2P

ADV

Burst Address Advance

Address Status Processor 4A

Address Status Controller

Clock

Chip Select

Byte Write Inputs

4G

N.C.

No Connect

ADSP

ADSC

CLK

CS1

CS2

WEx

(x=a,b,c,d)

4B

4K

4E

2B

DQa0~a7

DQb0~b7

DQc0~c7

DQd0~d7

DQPa~Pd

VDDQ

Data Inputs/Outputs

6B

5L,5G,3G,3L

Output Power Supply 1A,7A,1F,7F,1J,7J,1M,7M

(2.5V or 3.3V) 1U,7U

OE

Output Enable

4F

4H

4M

7T

3R

GW

BW

ZZ

Global Write Enable

Byte Write Enable

Power Down Input

Burst Mode Control

LBO

- 4 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

FUNCTION DESCRIPTION

The KM736V799 is a synchronous SRAM designed to support the burst address accessing sequence of the P6 and Power PC based

microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The start and duration of the

burst access is controlled by ADSC, ADSP and ADV and chip select pins.

The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with

ADV.

When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ

returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.

Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address

register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read oper-

ation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are car-

ried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output

pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address

increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to

control signals by disabling CS1.

All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx

when GW is high.

Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that sam-

ples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled

Low(regaedless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the

next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte

write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7

and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initi-

ated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;

ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).

Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external

address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state

of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is

selected.

BURST SEQUENCE TABLE

(Interleaved Burst)

Case 4

Case 1

Case 2

Case 3

LBO PIN

HIGH

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

BQ TABLE

(Linear Burst)

Case 1

Case 2

Case 3

Case 4

LBO PIN

LOW

First Address

A1

A0

A1

A0

A1

A0

A1

A0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Fourth Address

Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.

- 5 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

TRUTH TABLES

SYNCHRONOUS TRUTH TABLE

CS1

H

L

CS2

X

L

CS2 ADSP ADSC ADV WRITE CLK

ADDRESS ACCESSED

OPERATION

Not Selected

X

H

X

H

L

X

L

X

L

X

L

X

L

•

N/A

Not Selected

L

X

L

N/A

Not Selected

L

X

L

N/A

Not Selected

L

X

H

X

L

N/A

Not Selected

L

X

L

External Address

Next Address

Current Address

Begin Burst Read Cycle

Begin Burst Write Cycle

Begin Burst Read Cycle

Continue Burst Read Cycle

Continue Burst Write Cycle

Suspend Burst Read Cycle

Suspend Burst Write Cycle

L

H

X

H

X

H

X

H

X

L

H

L

X

H

X

H

X

H

X

H

X

H

L

H

L

Notes : 1. X means "Don¢t Care".

2. The rising edge of clock is symbolized by • .

3. WRITE = L means Write operation in WRITE TRUTH TABLE.

WRITE = H means Read operation in WRITE TRUTH TABLE.

4. Operation finally depends on status of asynchronous input pins(ZZ and OE).

WRITE TRUTH TABLE

GW

H

BW

H

L

WEa

X

WEb

X

WEc

X

WEd

X

OPERATION

READ

H

READ

H

L

H

WRITE BYTE a

WRITE BYTE b

WRITE BYTE c and d

WRITE ALL BYTEs

H

L

H

L

H

L

H

L

H

L

X

Notes : 1. X means "Don¢t Care".

2. All inputs in this table must meet setup and hold time around the rising edge of CLK(• ).

ASYNCHRONOUS TRUTH TABLE

(See Notes 1 and 2):

OPERATION

ZZ

H

L

OE

X

I/O STATUS

High-Z

Notes

Sleep Mode

1. X means "Don¢t Care".

2. ZZ pin is pulled down internally

L

DQ

3. For write cycles that following read cycles, the output buffers must be

disabled with OE, otherwise data bus contention will occur.

4. Sleep Mode means power down state of which stand-by current does

not depend on cycle time.

5. Deselected means power down state of which stand-by current

depends on cycle time.

Read

L

H

X

High-Z

Write

L

Din, High-Z

High-Z

Deselected

L

X

- 6 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

PASS-THROUGH TRUTH TABLE

PREVIOUS CYCLE

PRESENT CYCLE

NEXT CYCLE

OPERATION

WRITE

OPERATION

Initiate Read Cycle

All L Address=An

CS1

WRITE OE

Write Cycle, All bytes

Read Cycle

Data=Qn

L

H

L

Address=An-1, Data=Dn-1

Data=Qn-1 for all bytes

Write Cycle, All bytes

Address=An-1, Data=Dn-1

No new cycle

Data=Qn-1 for all bytes

No carryover from

previous cycle

All L

H

L

Write Cycle, All bytes

Address=An-1, Data=Dn-1

No new cycle

Data=High-Z

No carryover from

previous cycle

H

Initiate Read Cycle

One L Address=An

Data=Qn-1 for one byte

Write Cycle, One byte

Address=An-1, Data=Dn-1

Read Cycle

Data=Qn

L

H

L

Write Cycle, One byte

Address=An-1, Data=Dn-1

No new cycle

Data=Qn-1 for one byte

No carryover from

previous cycle

One L

H

Notes : 1. This operation makes written data immediately available at output during a read cycle preceded by a write cycle.s

ABSOLUTE MAXIMUM RATINGS*

PARAMETER

Voltage on VDD Supply Relative to VSS

Voltage on VDDQ Supply Relative to VSS

Voltage on Input Pin Relative to VSS

Voltage on I/O Pin Relative to VSS

Power Dissipation

SYMBOL

VDD

RATING

-0.3 to 4.6

VDD

UNIT

V

VDDQ

VIN

V

-0.3 to 6.0

-0.3 to VDDQ+0.5

2.2

V

VIO

V

PD

W

°C

Storage Temperature

TSTG

TOPR

TBIAS

-65 to 150

0 to 70

Operating Temperature

Storage Temperature Range Under Bias

-10 to 85

*Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

OPERATING CONDITIONS at 3.3V I/O (0°C£ TA£70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

0

Typ.

3.3

0

MAX

3.465

0

UNIT

V

VDDQ

VSS

OPERATING CONDITIONS at 2.5V I/O(0°C £ TA £ 70°C)

PARAMETER

Supply Voltage

Ground

SYMBOL

VDD

MIN

3.135

2.375

0

Typ.

3.3

2.5

0

Max

3.465

2.9

Unit

V

VDDQ

VSS

V

0

V

CAPACITANCE*(TA=25°C, f=1MHz)

PARAMETER

Input Capacitance

SYMBOL

TEST CONDITION

VIN=0V

MIN

MAX

UNIT

pF

CIN

-

6

8

Output Capacitance

COUT

VOUT=0V

pF

*Note : Sampled not 100% tested.

- 7 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.165V/-0.165V)

PARAMETER

Input Leakage Current(except ZZ)

Output Leakage Current

SYMBOL

TEST CONDITIONS

VDD = Max ; VIN=VSS to VDD

MIN

MAX

+2

UNIT

mA

IIL

-2

-

mA

IOL

Output Disabled, VOUT=VSS to VDDQ

+2

-40

-44

-50

-55

-57

-40

-44

-50

-55

-57

570

520

480

450

430

160

150

140

130

-

Device Selected, IOUT=0mA, ZZ£VIL,

All Inputs=VIL or VIH , Cycle Time ³ cyc Min

Operating Current

ICC

-

mA

-

Device deselected, IOUT=0mA,ZZ£VIL,

f=Max, All Inputs£0.2V or ³ VDD-0.2V

ISB

-

Standby Current

-

Device deselected, IOUT=0mA, ZZ£0.2V,

f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)

ISB1

ISB2

-

30

mA

Device deselected, IOUT=0mA, ZZ³ VDD-0.2V,

f=Max, All Inputs£VIL or ³ VIH

Output Low Voltage(3.3V I/O)

Output High Voltage(3.3V I/O)

Output Low Voltage(2.5V I/O)

Output High Voltage(2.5V I/O)

Input Low Voltage(3.3V I/O)

Input High Voltage(3.3V I/O)

Input Low Voltage(2.5V I/O)

Input High Voltage(2.5V I/O)

VOL

VOH

VOL

VOH

VIL

IOL = 8.0mA

IOH = -4.0mA

IOL = 1.0mA

IOH = -1.0mA

-

0.4

V

2.4

-

0.4

-

2.0

-0.5*

2.0

-0.3*

1.7

0.8

VIH

VIL

VDD+0.5**

0.7

VIH

VDD+0.5**

*

VIL(Min)=-2.0(Pulse Width £ tCYC/2)

** VIH(Max)=4.6(Pulse Width £ tCYC/2)

** In Case of I/O Pins, the Max. VIH=VDDQ+0.5V

TEST CONDITIONS

(VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)

PARAMETER

VALUE

0 to 3V

0 to 2.5V

1ns

Input Pulse Level(for 3.3V I/O)

Input Pulse Level(for 2.5V I/O)

Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)

Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)

Input and Output Timing Reference Levels for 3.3V I/O

Input and Output Timing Reference Levels for 2.5V I/O

Output Load

1ns

1.5V

VDDQ/2

See Fig. 1

- 8 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

Output Load(A)

Output Load(B)

(for tLZC, tLZOE, tHZOE & tHZC)

+3.3V for 3.3V I/O

/+2.5V for 2.5V I/O

Dout

RL=50W

VL=1.5V for 3.3V I/O

319W / 1667W

VDDQ/2 for 2.5V I/O

30pF*

Dout

Z0=50W

353W / 1538W

5pF*

* Capacitive Load consists of all components of

the test environment.

* Including Scope and Jig Capacitance

Fig. 1

AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.165V/-0.165V)

-40

-44

-50

-55

-57

PARAMETER

SYMBOL

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

Cycle Time

tCYC

tCD

4.0

-

4.4

-

5.0

-

5.4

-

5.7

-

ns

Clock Access Time

2.5

2.8

3.1

3.3

Output Enable to Data Valid

tOE

-

2.8

-

2.8

-

3.1

-

3.1

-

3.3

ns

Clock High to Output Low-Z

tLZC

tOH

0

-

0

-

0

-

0

-

0

-

ns

Output Hold from Clock High

Output Enable Low to Output Low-Z

Output Enable High to Output High-Z

Clock High to Output High-Z

Clock High Pulse Width

1.0

0

-

1.0

0

-

1.0

0

-

1.0

0

-

1.3

0

-

ns

tLZOE

tHZOE

tHZC

tCH

-

ns

-

2.8

-

2.8

-

3.0

-

3.0

-

3.0

ns

1.0

1.7

0.8

0.3

2

2.5

-

1.0

2.0

1.2

0.4

2

2.8

-

1.0

2.0

1.4

0.5

2

3.0

-

1.0

2.0

1.4

0.5

2

3.0

-

1.3

2.0

1.5

0.5

2

3.0

-

ns

Clock Low Pulse Width

tCL

-

ns

Address Setup to Clock High

Address Status Setup to Clock High

Data Setup to Clock High

tAS

-

ns

tSS

-

ns

tDS

-

ns

Write Setup to Clock High (GW, BW, WEX)

Address Advance Setup to Clock High

Chip Select Setup to Clock High

Address Hold from Clock High

Address Status Hold from Clock High

Data Hold from Clock High

tWS

-

ns

tADVS

tCSS

tAH

-

ns

-

ns

-

ns

tSH

-

ns

tDH

-

ns

Write Hold from Clock High (GW, BW, WEX)

Address Advance Hold from Clock High

Chip Select Hold from Clock High

ZZ High to Power Down

tWH

tADVH

tCSH

tPDS

tPUS

-

ns

-

ns

-

ns

-

cycle

ZZ Low to Power Up

2

-

2

-

2

-

2

-

2

-

Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC

and/or ADSP is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and

hold times whenever this device is chip selected.

2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.

3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.

- 9 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

- 10 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

- 11 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

- 12 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

- 13 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

- 14 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

APPLICATION INFORMATION

DEPTH EXPANSION

The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.

This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.

I/O[0:71]

Data

Address

A[0:17]

A[17]

A[0:16]

A[17]

A[0:16]

Address Data

CS

Address Data

CS

CLK

2

CS2

64-Bits

Microprocessor

CLK

ADSC

WEx

OE

128Kx36

SPB

SRAM

CLK

ADSC

WEx

OE

128Kx36

SPB

SRAM

Address

CLK

(Bank 1)

(Bank 0)

Cache

Controller

CS1

ADV ADSP

ADS

INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)

(ADSP CONTROLLED , ADSC=HIGH)

Clock

tSS

tSH

ADSP

tAS

tAH

A2

A1

ADDRESS

[0:n]

tWS

tWH

WRITE

CS1

tCSS

tCSH

Bank 0 is selected by CS2, and Bank 1 deselected by CS2

An+1

ADV

OE

Bank 0 is deselected by CS2, and Bank 1 selected by CS2

tADVS

tADVH

tOE

tHZC

tLZOE

Data Out

(Bank 0)

Q1-1

Q1-2

Q1-3

Q1-4

tCD

tLZC

Data Out

(Bank 1)

Q2-1

Q2-2

Q2-3

Q2-4

*Notes : n = 14 32K depth

15 64K depth

Don¢t Care

Undefined

16 128K depth

17 256K depth

- 15 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

PACKAGE DIMENSIONS

Units ; millimeters/Inches

100-TQFP-1420A

22.00 ±0.30

20.00 ±0.20

0~8°

+ 0.10

- 0.05

0.127

16.00 ±0.30

0.10 MAX

14.00 ±0.20

(0.83)

0.50 ±0.10

#1

0.65

(0.58)

0.30 ±0.10

0.10 MAX

1.40 ±0.10

1.60 MAX

0.05 MIN

0.50 ±0.10

- 16 -

June 1999

Rev 8.0

KM736V799

128Kx36 Synchronous SRAM

119 BGA PACKAGE DIMENSIONS

1.27

14.00±0.10

22.00±0.10

Indicator of

Ball(1A) Location

20.50±0.10

C0.70

C1.00

0.750±0.15

1.50REF

0.60±0.10

NOTE :

1. All Dimensions are in Millimeters.

2. Solder Ball to PCB Offset : 0.10 MAX.

3. PCB to Cavity Offset : 0.10 MAX.

12.50±0.10

- 17 -

June 1999

Rev 8.0


型号：	KM736V799H-57
厂家：	SAMSUNG
描述：	Cache SRAM, 128KX36, 3.3ns, CMOS, PBGA119, BGA-119 静态存储器
文件：	总17页 (文件大小：467K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KM736V799H-57 [SAMSUNG]

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