KMM366S104CT-G80_技术文档

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

Revision History

Revision .2 (Feb. 1998)

- Input leakage Currents (Inputs / DQ) of Component level are changed.

IIL(Inputs) : ± 5uA to ± 1uA, IIL(DQ) : ± 5uA to ± 1.5uA.

- Cin to be measured at V DD = 3.3V, TA = 23°C, f = 1MHz, V REF =1.4V ± 200 mV.

- Refresh cycle is changed 2K/32ms to 4K/64ms.

Revision .3 (Mar. 1998)

• AC Operating Condition is changed as defined :

- VIH(max) = 5.6V AC. The overshoot voltage duration is £ 3ns.

VIL(min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

KMM366S104CT SDRAM DIMM

1Mx64 SDRAM DIMM based on 1Mx16, 4K Refresh, 3.3V Synchronous DRAMs with SPD

GENERAL DESCRIPTION

FEATURE

The Samsung KMM366S104CT is a 1M bit x 64 Synchronous

Dynamic RAM high density memory module. The Samsung

KMM366S104CT consists of four CMOS 1M x 16 bit Synchro-

nous DRAMs in TSOP-II 400mil package and a 1K or 2K

EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy

substrate. Two 0.1uF decoupling capacitors are mounted on the

printed circuit board in parellel for each SDRAM.

•

Performance range

Max Freq. (Speed)

125MHz (8ns)

100MHz (10ns)

KMM366S104CT-G8

KMM366S104CT-GH

KMM366S104CT-GL

•

Burst Mode Operation

Auto & Self Refresh Capability (4096 cycles / 64ms)

LVTTL compatible inputs and outputs

The KMM366S104CT is a Dual In-line Memory Module and is

intended for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use of

system clock. I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable latencies allows

the same device to be useful for a variety of high bandwidth,

high performance memory system applications.

• Single 3.3V ± 0.3V power supply

•

MRS cycle with address key programs

Latency (Access from column address)

Burst Length (1, 2, 4, 8 & Full page)

Data Scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

•

Serial Presence Detect with EEPROM

• PCB : Height(1,375mil), single sided component

PIN CONFIGURATIONS (Front Side / Back Side)

PIN NAMES

Pin Front Pin Front

Front Pin Back Pin Back Pin Back

Pin Name

A0 ~ A10/AP

BA0

Function

Address Input (multiplexed)

Select Bank

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

1

2

3

4

5

6

7

8

9

10

11

12

13

VSS

DQ0

DQ1

DQ2

DQ3

VDD

DQ4

DQ5

DQ6

DQ7

DQ8

VSS

29 DQM1

DQ18 85

DQ19 86 DQ32 114 *CS1 142 DQ51

87 DQ33 115 RAS 143 VDD

VSS

113 DQM5 141 DQ50

30

31

32

33

34

35

36

37

CS0

DU

VSS

A0

A2

A4

DQ0 ~ DQ63

CLK0 , CLK2

CKE0

Data Input / Output

Clock Input

VDD

DQ20 88 DQ34 116

NC 89 DQ35 117

*VREF 90 VDD 118

*CKE1 91 DQ36 119

92 DQ37 120

DQ21 93 DQ38 121

VSS

A1

A3

A5

A7

A9

144 DQ52

145 NC

146 *VREF

147 NC

148 VSS

149 DQ53

Clock Enable Input

Chip Select Input

Row Address Storbe

Column Address Strobe

Write Enable

CS0, CS2

RAS

A6

A8

VSS

CAS

38 A10/AP

DQ22 94 DQ39 122 BA0 150 DQ54

DQ23 95 DQ40 123 *A11 151 DQ55

WE

39

40

41

*BA1

VDD

DQM0 ~ 7

VDD

DQM

VSS

96

VSS

124 VDD 152 VSS

DQ9

DQ24 97 DQ41 125 *CLK1 153 DQ56

DQ25 98 DQ42 126 *A12 154 DQ57

Power Supply (3.3V)

Ground

14 DQ10 42 CLK0

VSS

15 DQ11 43

16 DQ12 44

17 DQ13 45

VSS

NC

CS2

DQ26 99 DQ43 127

VSS

155 DQ58

*VREF

Power Supply for Reference

Serial Data I/O

Serial Clock

DQ27 100 DQ44 128 CKE0 156 DQ59

VDD 101 DQ45 129 *CS3 157 VDD

DQ28 102 VDD 130 DQM6 158 DQ60

DQ29 103 DQ46 131 DQM7 159 DQ61

DQ30 104 DQ47 132 *A13 160 DQ62

DQ31 105 *CB4 133 VDD 161 DQ63

SDA

18

VDD

46 DQM2

SCL

19 DQ14 47 DQM3

SA0 ~ 2

WP

Address in EEPROM

Write Protection

Don¢t use

20 DQ15 48

21 *CB0 49

22 *CB1 50

NC

VDD

NC

VSS

106 *CB5 134

NC

162 VSS

163 *CLK3

DU

23

24

25

26

27

VSS

NC

VDD

WE

51

52

53

54

NC

CLK2 107

NC 108

WP 109

VSS

NC

135

NC

No Connection

*CB2

*CB3

VSS

136 *CB6 164

137 *CB7 165 **SA0

166 **SA1

NC

*

These pins are not used in this module.

** These pins should be NC in the system

**SDA 110 VDD 138

VSS

55 DQ16

**SCL 111 CAS 139 DQ48 167 **SA2

VDD 112 DQM4 140 DQ49 168 VDD

which does not support SPD.

28 DQM0 56 DQ17

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

PIN CONFIGURATION DESCRIPTION

Name

System Clock

Input Function

CLK

CS

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Chip Select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE

Clock Enable

CKE should be enabled 1CLK+t SS prior to valid command.

Row / column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA10, column address : CA0 ~ CA7

A0 ~ A10/AP Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

BA0

RAS

CAS

WE

Bank Select Address

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Row Address Strobe

Column Address Strobe

Write Enable

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

Makes data output Hi-Z, t SHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)l be

DQM0 ~ 7

DQ0 ~ 63

Data Input/Output Mask

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

WP pin is connected to V CC.

WP

Write Protection

When WP is "high", EEPROM Programming will be inhibited and the entire memory will

be write - protected.

VDD/VSS

Power Supply/Ground

Power and ground for the input buffers and the core logic.

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

FUNCTIONAL BLOCK DIAGRAM

·

CS0

DQM0

DQM4

LDQM CS

DQ0

DQ1

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U0

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U2

UDQM

DQM1

UDQM

DQM5

DQ8

DQ9

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

·

CS2

DQM2

DQM6

LDQM CS

DQ16

DQ0

DQ1

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ0

DQ1

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U3

UDQM

DQM3

UDQM

DQM7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ8

DQ9

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

Serial PD

SDRAM U0 ~ U3

A0 ~ An, BA0

RAS

SCL

SDA

WP

A0 A1 A2

47W

CAS

SA0 SA1 SA2

WE

10W

CKE0

U0/U2

U1/U3

·

CLK0/2

15pF

10W

DQn

Every DQpin of SDRAM

10W

CLK1/3

·

VDD

Vss

Two 0.1uF Capacitors

per each SDRAM

10pF

To all SDRAMs

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V DD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0 ~ 4.6

-55 ~ +150

4

Unit

V

°C

W

Power dissipation

PD

Short circuit current

IOS

50

mA

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to V SS = 0V, TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

Min

3.0

2.0

-0.3

2.4

-

Typ

Max

Unit

V

Note

VDD, VDDQ

3.3

3.6

Input logic high votlage

VIH

VIL

VOH

VOL

IIL

3.0

VDDQ+0.3

V

1

Input logic low voltage

0

-

0.8

-

V

2

IOH = -2mA

IOL = 2mA

3

Output logic high voltage

Output logic low voltage

Input leakage current(Inputs)

Input leakage current (I/O pins)

V

-

0.4

4

V

-4

-

uA

IIL

-1.5

-

1.5

3,4

Note :

1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

3. Any input 0V £ VIN £ VDDQ.

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. Dout is disabled, 0V £ VOUT £ VDDQ.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)

Parameter

Symbol

Min

Max

Unit

Input capacitance (A0 ~ A10/AP, BA0)

Input capacitance ( RAS, CAS, WE)

Input capacitance (CKE0)

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

COUT

30

25

15

5

40

35

25

15

pF

Input capacitance (CLK0,CLK2)

Input capacitance ( CS0, CS2)

Input capacitance (DQM0 ~ DQM7)

Data input/output capacitance (DQ0 ~ DQ63)

5

MAXIMUM TRACE LENGTHS

Signal

Max lengths

Unit

Signal

Max lengths

Unit

A0 ~ A10/AP

BA0

8.0

inches

CKE0

5.5

4.0

3.0

2.0

inches

CS0, CS2

RAS

DQM0 ~ DQM7

DQ0 ~ DQ63

CAS

WE

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)

CAS

Latency

Version

Parameter

Symbol

Test Condition

Unit

mA

Note

-8

-H

-L

Burst Length =1

t RC ³ tRC(min)

I OL = 0 mA

Operating Current

(One Bank Active)

ICC1

380

360

1

ICC2P

CKE £ VIL(max), tCC = 15ns

CKE & CLK £ VIL(max), tCC = ¥

4

Precharge Standby Current

in power-down mode

mA

ICC2PS

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

Input signals are changed one time during

ICC2N

60

16

Precharge Standby Current

in non power-down mode

mA

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC2NS

Active Standby Current

in power-down mode

ICC3P

CKE £ VIL(max), tCC = 15ns

8

4

mA

ICC3PS

CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

Input signals are changed one time during

ICC3N

100

60

Active Standby Current

in non power-down mode

(One Bank Active)

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC3NS

IOL = 0 mA

3

520

400

460

400

Operating Current

(Burst Mode)

Page Burst

ICC4

mA

1

2

2Banks Activated

2

TCCD = 2CLKs

Refresh Current

ICC5

ICC6

tRC ³ tRC(min)

CKE £ 0.2V

360

4

mA

Self Refresh Current

Note :

1. Measured with outputs open.

2. Refresh period is 64ms.

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter

Input levels (Vih/Vil)

Value

2.4 / 0.4

1.4

Unit

V

Input timing measurement reference level

Input rise and fall time

V

tr / tf = 1 / 1

1.4

ns

V

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt=1.4V

1200W

50W

VOH (DC) = 2.4V, I OH = -2mA

VOL (DC) = 0.4V, I OL = 2mA

·

Output

Z0=50W

50pF

870W

(Fig. 1) DC Output Load Circuit

(Fig. 2) AC Output Load Circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

-8

Unit

Note

-H

20

50

100

70

1

-L

20

50

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

16

20

48

ns

1

Row precharge time

ns

tRAS(min)

tRAS(max)

tRC(min)

ns

Row active time

us

Row cycle time

68

70

ns

1

2

3

Last data in to new col. address delay

Last data in to row precharge

Last data in to burst stop

tCDL(min)

tRDL(min)

tBDL(min)

tCCD(min)

CLK

1

Col. address to col. address delay

1

CAS latency=3

CAS latency=2

2

Number of valid

output data

ea

4

1

Note :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Refer to the individual componenet, not the whole module.

-8

-H

-L

Parameter

Symbol

Unit

ns

Note

1

Min

8

Max

Min

10

Max

Min

10

Max

CAS Latency=3

CLK cycle time

tCC

1000

CAS Latency=2

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

12

10

12

6

7

CLK to valid

output delay

tSAC

ns

1, 2

2

3

2

1

3

2

1

3

2

1

Output data

hold time

tOH

ns

CLK high pulse width

CLK low pulse width

Input setup time

tCH

tCL

ns

3

2

tSS

Input hold time

tSH

tSLZ

CLK to output in Low-Z

CAS latency=3

CAS latency=2

6

7

CLK to output

in Hi-Z

tSHZ

ns

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE

KMM366S104CT-8

(Unit : number of clock)

tRC

tRAS

tRP

tRRD

tRCD

tCCD

tCDL

8ns

1

tRDL

8ns

1

CAS

Latency

Frequency

68ns

48ns

20ns

16ns

20ns

8ns

1

125MHz (8.0ns)

100MHz (10.0ns)

83MHz (12.0ns)

75MHz (13.0ns)

66MHz (15.0ns)

3

2

9

7

6

5

4

3

2

3

2

1

KMM366S104CT-H

Frequency

(Unit : number of clock)

tRC

tRAS

tRP

tRRD

tRCD

tCCD

tCDL

tRDL

CAS

Latency

70ns

50ns

20ns

10ns

100MHz (10.0ns)

83MHz (12.0ns)

75MHz (13.0ns)

66MHz (15.0ns)

60MHz (16.7ns)

2

7

6

5

4

3

2

1

KMM366S104CT-L

Frequency

(Unit : number of clock)

tRC

tRAS

tRP

tRRD

tRCD

tCCD

tCDL

tRDL

CAS

Latency

70ns

50ns

20ns

10ns

100MHz (10.0ns)

83MHz (12.0ns)

75MHz (13.0ns)

66MHz (15.0ns)

60MHz (16.7ns)

3

2

7

6

5

4

3

2

1

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

SIMPLIFIED TRUTH TABLE

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM BA0

A10/AP

A9 ~ A0

Note

1, 2

3

COMMAND

Register

Refresh

Mode Register Set

Auto Refresh

H

X

H

L

X

OP CODE

H

L

H

X

Entry

3

Self

Refresh

L

H

L

H

X

L

H

X

H

X

H

3

Exit

L

H

X

3

Bank Active & Row Addr.

X

V

Row Address

Column

Address

(A0~A7)

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

L

H

L

4

4, 5

4

Read &

Column Address

L

H

L

H

Column

Address

(A0~A7)

Write &

Column Address

H

X

L

H

L

X

V

H

4, 5

6

Burst Stop

Precharge

H

X

Bank Selection

Both Banks

V

X

L

X

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

Exit

H

L

H

L

X

Clock Suspend or

Active Power Down

X

H

L

Entry

H

Precharge Power Down Mode

H

L

Exit

L

H

X

V

X

DQM

X

7

H

L

X

H

X

H

No Operation Command

(V=Valid, X=Don ¢t Care, H=Logic High, L=Logic Low)

Note :

1. OP Code : Operand Code

A0 ~ A10/AP, BA0 : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at both banks precharge state.

4. BA0 : Bank select address.

If "Low" at read, write, row active and precharge, bank A is selected.

If "High" at read, write, row active and precharge, bank B is selected.

If A10/AP is "High" at row precharge, BA 0 is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the assoiated bank can be issued at t RP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

REV. 3 Mar. '98

Preliminary

KMM366S104CT

PC100 SDRAM MODULE

PACKAGE DIMENSIONS

Units : Inches (millimeters)

5.250

R 0.079

0.089

(133.350)

0.175

(R 2.000)

(2.26)

5.014

(4.45)

0.118

(3.000)

0.387 ± 0.062

(127.350)

0.157 ± 0.004

(9.84 ± 1.59)

(4.000 ± 0.100)

B

C

A

.118DIA ±. 004

(3.000DIA ±. 100)

0.250

(6.350)

0.250

(6.350)

0.350

(8.890)

1.450

(36.830)

2.150

(54.61)

.450

(11.430)

4.550

(115.57)

0.100Max

(2.54Max)

0.050 ± 0.0039

(1.270 ± 0.10)

0.250

(6.350)

0.250

(6.350)

0.039 ±. 002

(1.000 ±. 050)

0.123 ±. 005

(3.125 ±. 125)

0.123 ±. 005

(3.125 ±. 125)

0.010Max

(0.250 Max)

0.050

(1.270)

0.079 ±. 004

(2.000 ±. 100)

0.079 ±. 004

(2.000 ±. 100)

Detail A

Detail B

Detail C

Tolerances : ±.005(.13) unless otherwise specified

The used device is 1Mx16 SDRAM, TSOP

SDRAM Part No. : KM416S1020CT

REV. 3 Mar. '98


型号：	KMM366S104CT-G80
厂家：	SAMSUNG
描述：	Synchronous DRAM Module, 1MX64, 6ns, CMOS, DIMM-168 动态存储器内存集成电路
文件：	总11页 (文件大小：148K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KMM366S104CT-G80 [SAMSUNG]

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KMM366S1623BT-GL

KMM366S1623BTL

KMM366S1623BTL-G0