KMM372C1600BK [SAMSUNG]
16M x 72 DRAM DIMM with ECC Using 16Mx4, 4K 8K Refresh 5V; 16M X 72的DRAM DIMM ECC与使用16Mx4 ， 4K 8K刷新5V
| 型号： | KMM372C1600BK |
| 厂家： | 
SAMSUNG |
| 描述： | 16M x 72 DRAM DIMM with ECC Using 16Mx4, 4K 8K Refresh 5V |
| 文件： | 总19页 (文件大小：430K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRAM MODULE
KMM372C213CK/CS
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC
-1 to +7.0
-1 to +7.0
-55 to +125
9
V
V
°C
W
Tstg
PD
Power Dissipation
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
4.5
0
2.4
5.5
0
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
5.0
0
-
V
V
V
V
*1
VCC+1
0.8
*2
-
-1.0
*1 : VCC+2.0V/20ns, Pulse width is measured at VCC.
*2 : -2.0V/20ns, Pulse width is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
KMM372C213CK/CS
Symbol
Speed
Unit
Min
Max
-5
-6
990
900
mA
mA
-
-
ICC1
ICC2
ICC3
Don¢t care
-
100
mA
-5
-6
-
-
990
900
mA
mA
-5
-6
-
-
810
720
mA
mA
ICC4
ICC5
ICC6
Don¢t care
-
30
mA
-5
-6
-
-
990
900
mA
mA
II(L)
IO(L)
-25
-5
25
5
uA
uA
Don¢t care
Don¢t care
VOH
VOL
2.4
-
-
V
V
0.4
ICC1*
ICC2
ICC3*
ICC4*
ICC5
ICC6*
II(L)
: Operating Current * (RAS, CAS, Address cycling @tRC=min)
: Standby Current (RAS=CAS=W=VIH)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0£VIN£Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V£VOUT£Vcc)
: Output High Voltage Level (IOH = -5mA)
IO(L)
VOH
VOL : Output Low Voltage Level (IOL = 4.2mA)
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one page mode cycle, tPC.
DRAM MODULE
KMM372C213CK/CS
CAPACITANCE (TA = 25°C, Vcc=5V, f = 1MHz)
Item
Symbol
Min
Max
Unit
-
-
-
-
-
Input capacitance[A0-A10, B0]
CIN1
CIN2
CIN3
CIN4
CDQ1
15
17
38
17
17
pF
pF
pF
pF
pF
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0 , RAS2]
Input capacitance[CAS0 , CAS4]
Input/Output capacitance[DQ0 - 71 ]
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, Output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
90
Max
Min
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
110
155
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
tRC
133
tRWC
tRAC
tCAC
tAA
50
18
30
60
20
35
3,4
3,4,5,11
3,10,11
3,11
Access time from CAS
Access time from column address
CAS to output in Low-Z
5
5
5
tCLZ
tOFF
tT
Output buffer turn-off delay
Transition time(rise and fall)
RAS precharge time
5
18
50
20
50
6,11
2
2
2
30
50
18
48
13
18
13
10
5
40
60
20
58
15
18
13
10
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
11
11
CAS hold time
CAS pulse width
10K
32
10K
40
RAS to CAS delay time
4,11
10,11
11
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
20
25
11
8
8
11
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
0
0
10
30
0
10
35
0
11
0
0
8
-2
10
10
18
13
-2
15
-2
10
10
20
15
-2
20
8,11
11
tRWL
tCWL
tDS
9,11
9,11
Data hold time
tDH
Refresh period (2K refresh)
Write command set-up time
CAS to W delay time
32
32
tREF
tWCS
tCWD
tAWD
tCPWD
0
0
7
7
7
7
36
48
53
40
55
60
Column address to W delay time
CAS precharge to W delay time
DRAM MODULE
KMM372C213CK/CS
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V, Output loading CL=100pF
-5
-6
Parameter
RAS to W delay time
Symbol
Unit
Note
Min
71
10
8
Max
Min
83
10
8
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7,11
11
tRWD
tCSR
tCHR
tRPC
tCPA
tPC
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS precharge to CAS hold time
Access time from CAS precharge
Fast page mode cycle time
11
3
3
11
35
40
3,11
35
75
10
50
35
15
8
40
80
10
60
40
15
8
Fast page mode read-modify-write cycle time
CAS precharge time(Fast page cycle)
RAS pulse width (Fast page cycle)
RAS hold time from CAS precharge
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
OE access time
tPRWC
tCP
200K
200K
tRASP
tRHCP
tWRP
tWRH
tOEA
tOED
tOEZ
tOEH
11
11
11
11
11
11
18
18
20
20
OE to data delay
18
5
20
5
Output buffer turn off delay time from OE
OE command hold time
13
15
Present Detect Read Cycle
PDE to Valid PD bit
10
7
10
7
ns
ns
tPD
PDE to PD bit Inactive
2
2
tPDOFF
DRAM MODULE
KMM372C213CK/CS
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
tWCS is not restrictive operating parameter. It included in the
data sheet as electrical characteristic only. If tWCS³ tWCS(min)
the cycle is an early write cycle and the data out pin will
remain high impedance for the duration of the cycle.
7.
2.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are
reference levels for measuring timing of input signals. Transi-
tion times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
8.
9.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
3.
4.
Measured with a load equivalent to 2 TTL loads and 100pF.
10.
11.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
Assumes that tRCD³ tRCD(max).
5.
6.
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
DRAM MODULE
KMM372C213CK/CS
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tASR
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAL
tRAH
tASC
tRCS
tCAH
VIH -
COLUMN
ADDRESS
ROW
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tOFF
tOEZ
tAA
VIH -
tOEA
OE
VIL -
tCAC
tCLZ
tRAC
VOH -
DQ
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCS
tWCH
tWP
VIH -
VIL -
W
VIH -
VIL -
OE
DQ
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRP
tRAS
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tCWL
tRWL
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
DQ
tOED
tOEH
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
READ - MODIFY - WRTIE CYCLE
tRWC
tRP
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tRAH
tASR
tASC
tCAH
tCSH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tRWL
tAWD
tCWD
tCWL
VIH -
VIL -
tWP
W
tRWD
tOEA
VIH -
VIL -
OE
tCLZ
tCAC
tOED
tAA
tDS
tDH
tOEZ
tRAC
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
DQ
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
FAST PAGE READ CYCLE
NOTE : DOUT = OPEN
tRP
tRASP
¡ó
VIH -
RAS
VIL -
tRHCP
tPC
tCRP
tCP
tRCD
tRAD
tCP
tRSH
tCAS
tCAS
¡ó
VIH -
CAS
tCAS
VIL -
tASC
tCSH
tASR
ROW
tASC
tCAH
tASC
tCAH
tRAH
tCAH
tRCH
¡ó
¡ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
A
W
ADDR
ADDRESS
tRCS
tRRH
tRCH
tRCS
tRCS
¡ó
VIH -
VIL -
tCAC
tOEA
tCAC
tOEA
tCAC
tOEA
¡ó
¡ó
VIH -
VIL -
OE
tAA
tOFF
tAA
tOFF
tCLZ
tAA
tOFF
tOEZ
tRAC
tCLZ
tCLZ
tOEZ
VALID
tOEZ
VALID
VOH -
VOL -
VALID
DQ
DATA-OUT
DATA-OUT
DATA-OUT
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
FAST PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
¡ó
VIH -
RAS
VIL -
tRHCP
tPC
tPC
tCRP
tCP
tRCD
tCP
tRSH
tCAS
tCAS
¡ó
VIH -
VIL -
tCAS
CAS
tRAD
tASC
tRAH
ROW
tCStHCAH
tASC
tCAH
tASC
tCAH
tASR
¡ó
¡ó
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDR
tWCS
tWCS
tWCH
tWP
tWCS
tWCH
¡ó
tWCH
VIH -
VIL -
tWP
tWP
W
tCWL
tCWL
tRWL
tCWL
¡ó
VIH -
VIL -
OE
DQ
¡ó
tDS
tDH
tDS
tDH
tDS
tDH
¡ó
¡ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
FAST PAGE READ - MODIFY - WRITE CYCLE
tRP
tRASP
tCP
VIH -
VIL -
tCSH
RAS
CAS
tRSH
tCAS
tPRWC
tRCD
tRAD
tCRP
VIH -
VIL -
tCAS
tRAH
tRAL
tCAH
tASR
ROW
tCAH
tASC
tASC
VIH -
VIL -
COL.
ADDR
COL.
ADDR
A
ADDR
tRWL
tWP
tRCS
tCWL
tCWL
VIH -
VIL -
tWP
W
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
tOEA
VIH -
VIL -
tOEA
OE
tOED
tCAC
tOED
tCAC
tDH
tDH
tAA
tAA
tDS
tOEZ
tDS
tOEZ
tRAC
VI/OH -
VI/OL -
DQ
tCLZ
tCLZ
VALID
VALID
DATA-IN
VALID
VALID
DATA-OUT
DATA-IN
DATA-OUT
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRAS
tRP
VIH -
RAS
tRPC
tCP
VIL -
tRPC
VIH -
VIL -
tCSR
tWRP
CAS
W
tCHR
tWRH
VIH -
VIL -
tOFF
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCAH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tRCS
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWRH
tWRP
tRRH
VIH -
VIL -
W
tAA
VIH -
VIL -
OE
tOEA
tOFF
tCAC
tCLZ
tRAC
tOEZ
DATA-OUT
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
A
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
W
tWP
VIH -
VIL -
OE
tDS
tDH
VIH -
VIL -
DQ
DATA-IN
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCAS
tCSR
VIH -
VIL -
tCHR
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
tRRH
tRCH
tAA
tWRP
tWRH
tRCS
READ CYCLE
tCAC
VIH -
W
VIL -
VIH -
OE
VIL -
tOFF
tOEZ
tOEA
tCLZ
VOH -
DQ
DATA-OUT
VOL -
WRITE CYCLE
tRWL
tWRP
tWRH
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
READ-MODIFY-WRITE
tAWD
tCWL
tRWL
tWRP
tWRH
tRCS
tCWD
VIH -
W
tWP
tCAC
tOEA
VIL -
tAA
VIH -
OE
tOED
tOEZ
VIL -
tDH
tCLZ
tDS
VI/OH -
DQ
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
Undefined
NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM.
DRAM MODULE
KMM372C213CK/CS
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
tRPC
VIH -
RAS
tRPC
tCP
VIL -
tCHS
VIH -
VIL -
tCSR
CAS
DQ
tOFF
VOH -
VOL -
OPEN
tWRP
tWRH
VIH -
VIL -
W
TEST MODE IN CYCLE
NOTE : OE, A = Don¢t care
tRC
tRP
tRAS
tRP
VIH -
RAS
tRPC
tCP
VIL -
tRPC
VIH -
CAS
VIL -
tCSR
tWTS
tCHR
tWTH
VIH -
W
VIL -
tOFF
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
DRAM MODULE
KMM372C213CK/CS
Units : Inches (millimeters)
0.054
PACKAGE DIMENSIONS
5.250
(133.350)
(1.372)
0.118
(3.000)
5.014
(127.350)
R 0.079
(R 2.000)
0.157±0.004
(4.000±0.100)
B
C
A
.118DIA±.004
0.250
0.250
(6.350)
(3.000DIA±.100)
(6.350)
1.450
2.150
0.350
(8.890)
(36.830)
(54.61)
.450
(11.430)
4.550
(115.57)
( Front view )
0.100Max
(2.54Max)
(TSOP)
0.200Max
(5.08Max)
(SOJ)
0.050±0.0039
(1.270±0.10)
( Back view )
0.250
(6.350)
0.250
(6.350)
0.039±.002
(1.000±.050)
0.123±.005
0.123±.005
0.010Max
(3.125±.125)
(3.125±.125)
(0.250 Max)
0.050
(1.270)
0.079±.004
(2.000±.100)
0.079±.004
(2.000±.100)
Detail A
Detail B
Detail C
Tolerances : ±.005(.13) unless otherwise specified
The used device is 2Mx8 DRAM with Fast Page mode, SOJ or TSOP II (Forward).
DRAM Part No. : KMM372C213CK - KM48C2100CK
KMM372C213CS - KM48C2100CS
相关型号：
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