KMM372F400CS-5 [SAMSUNG]
EDO DRAM Module, 4MX72, 50ns, CMOS, DIMM-168;
| 型号： | KMM372F400CS-5 |
| 厂家： | 
SAMSUNG |
| 描述： | EDO DRAM Module, 4MX72, 50ns, CMOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
KMM372F400CK/CS / KMM372F410CK/CS Fast Page with EDO Mode
4M x 72 DRAM DIMM with ECC using 4Mx4, 4K/2K Refresh, 3.3V
GENERAL DESCRIPTION
FEATURES
The Samsung KMM372F40(1)0C is a 4Mx72bits Dynamic
RAM high density memory module. The Samsung
KMM372F40(1)0C consists of eighteen CMOS 4Mx4bits
DRAMs in SOJ/TSOP-II 300mil package, and two 16bits driver
IC in 48pin TSSOP package mounted on a 168-pin glass-
epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is
mounted on the printed circuit board for each DRAM. The
KMM372F40(1)0C is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
• Part Identification
- KMM372F400CK (4096 cycles/64ms Ref., SOJ)
- KMM372F400CS (4096 cycles/64ms Ref., TSOP)
- KMM372F410CK (4096 cycles/32ms Ref., SOJ)
- KMM372F410CS (4096 cycles/32ms Ref., TSOP)
• Fast Page Mode with Extended Data Out Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
PERFORMANCE RANGE
• Single 3.3V±0.3V power supply
Speed
-5
tRAC
50ns
60ns
tCAC
18ns
20ns
tRC
tHPC
25ns
30ns
• JEDEC standard pinout & Buffered PDpin
• Buffered input except RAS and DQ
90ns
110ns
• PCB : Height(1000mil), double sided component
-6
PIN CONFIGURATIONS
PIN NAMES
Pin
Pin Front Pin Front
Front Pin Back Pin Back Pin Back
Pin Names
Function
A0, B0, A1 - A11 Address Input (4K Ref.)
A0, B0, A1 - A10 Address Input (2K Ref.)
57
58
59
60
1
2
3
4
5
6
7
8
9
VSS
29 RSVD
DQ22 85
DQ23 86 DQ36 114 *RAS1 142 DQ59
87 DQ37 115 RFU 143 VCC
DQ24 88 DQ38 116 VSS 144 DQ60
VSS 113 RSVD 141 DQ58
DQ0 30 RAS0
DQ1 31 OE0
DQ2 32
DQ3 33
DQ0 - DQ71
W0, W2
OE, OE2
RAS0, RAS2
CAS0, CAS4
VCC
Data In/Out
VCC
VSS
A0
Read/Write Enable
Output Enable
61 RFU 89 DQ39 117
A1
A3
A5
A7
A9
145 RFU
146 RFU
147 RFU
148 RFU
149 DQ61
62
63
64
65
66
67
68
69
70
71
VCC
34
A2
RFU 90
VCC 118
Row Address Strobe
Colume Address Strobe
Power(+3.3V)
DQ4 35
DQ5 36
DQ6 37
A4
A6
A8
A10
RFU 91 DQ40 119
RFU 92 DQ41 120
DQ25 93 DQ42 121
10 DQ7 38
11 DQ8 39 *A12
12 40
13 DQ9 41 RFU
14 DQ10 42 RFU
15 DQ11 43
DQ26 94 DQ43 122 A11 150 DQ62
DQ27 95 DQ44 123 *A13 151 DQ63
VSS
Ground
NC
No Connection
Presence Detect Enable
Presence Detect
ID bit
VSS
VCC
VSS
96
DQ28 97 DQ45 125 RFU 153 DQ64
DQ29 98 DQ46 126 B0 154 DQ65
DQ30 99 DQ47 127 VSS 155 DQ66
VSS 124 VCC 152 VSS
PDE
PD1 - 8
ID0 - 1
VSS
16 DQ12 44 OE2 72 DQ31 100 DQ48 128 RFU 156 DQ67
73
74
75
76
77
78
79
80
81
82
83
84
17 DQ13 45 RAS2
18 46 CAS4
19 DQ14 47 RSVD
VCC 101 DQ49 129 *RAS3 157 VCC
DQ32 102 VCC 130 *CAS5 158 DQ68
DQ33 103 DQ50 131 RSVD 159 DQ69
DQ34 104 DQ51 132 PDE 160 DQ70
DQ35 105 DQ52 133 VCC 161 DQ71
RSVD
Reserved Use
VCC
RFU
Reserved for Future Use
Pins marked ¢*¢ are not used in this module.
20 DQ15 48
21 DQ16 49
W2
VCC
PD & ID Table
22 DQ17 50 RSVD
23 51 RSVD
VSS
106 DQ53 134 RSVD 162 VSS
Pin
50NS
60NS
VSS
PD1 107 VSS 135 RSVD 163 PD2
PD3 108 RSVD 136 DQ54 164 PD4
PD5 109 RSVD 137 DQ55 165 PD6
PD7 110 VCC 138 VSS 166 PD8
ID0 111 RFU 139 DQ56 167 ID1
VCC 112 *CAS1 140 DQ57 168 VCC
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
1
1
0
1
1
0
0
0
1
1
0
1
1
1
1
0
24 RSVD 52 DQ18
25 RSVD 53 DQ19
26
27
VCC
W0
54
VSS
55 DQ20
28 CAS0 56 DQ21
NOTE : A11 is used for only KMM372F400CK/CS (4K ref.)
ID0
ID1
0
0
0
0
PD Note : PD & ID Terminals must each be pulled up through a resister to VCC at the next higher
level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits.
ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer.
PD : 0 for Vol of Drive IC & 1 for N.C
ID : 0 for Vss & 1 for N.C
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
RAS0
CAS0
W0
RAS2
CAS4
W2
OE0
A0
OE2
B0
A1-A11(A10)
A1-A11(A10)
DQ0
DQ1
DQ2
DQ3
DQ0
DQ36
DQ0
DQ1
DQ2
DQ3
DQ1
DQ2
DQ3
DQ37
DQ38
DQ39
U0
U1
U2
U3
U4
U5
U6
U7
U8
U9
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ40
DQ41
DQ42
DQ43
DQ0
DQ1
DQ2
DQ3
U10
U11
U12
U13
U14
U15
U16
U17
DQ8
DQ9
DQ10
DQ11
DQ0
DQ1
DQ2
DQ3
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ48
DQ49
DQ50
DQ51
DQ0
DQ1
DQ2
DQ3
DQ16
DQ17
DQ18
DQ19
DQ0
DQ1
DQ2
DQ3
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ56
DQ57
DQ58
DQ59
DQ0
DQ1
DQ2
DQ3
DQ24
DQ25
DQ26
DQ27
DQ0
DQ1
DQ2
DQ3
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ64
DQ65
DQ66
DQ67
DQ0
DQ1
DQ2
DQ3
DQ32
DQ33
DQ34
DQ35
DQ0
DQ1
DQ2
DQ3
DQ68
DQ69
DQ70
DQ71
DQ0
DQ1
DQ2
DQ3
A0
U0-U8
U9-U17
A1-An : U0-U17
Vcc
Vss
B0
A1-An
W0, 2
.1 or .22uF Capacitor
under each DRAM
To all DRAMs
OE0, 2
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC
-0.5 to +4.6
-0.5 to +4.6
-55 to +125
18
V
V
°C
W
Tstg
PD
Power Dissipation
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
3.0
0
2.0
3.6
0
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
3.3
0
-
V
V
V
V
*1
VCC+0.3
0.8
*2
-
-0.3
*1 : VCC+1.3V/15ns, Pulse width is measured at VCC.
*2 : -1.3V/15ns, Pulse width is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
KMM372F400CK/CS
KMM372F410CK/CS
Symbol
Speed
Unit
Min
Max
Min
Max
ICC1
-5
-6
1620
1440
1980
1800
mA
mA
-
-
-
-
ICC2
ICC3
Don¢t care
-
100
-
100
mA
-5
-6
-
-
1620
1440
-
-
1980
1800
mA
mA
ICC4
-5
-6
-
-
1440
1260
-
-
1620
1440
mA
mA
ICC5
ICC6
Don¢t care
-
30
-
30
mA
-5
-6
-
-
1620
1440
-
-
1980
1800
mA
mA
II(L)
IO(L)
-45
-5
45
5
-45
-5
45
5
uA
uA
Don¢t care
Don¢t care
VOH
VOL
2.4
-
-
2.4
-
-
V
V
0.4
0.4
ICC1*
ICC2
ICC3*
ICC4*
ICC5
ICC6*
II(L)
: Operating Current * (RAS, CAS, Address cycling @tRC=min)
: Standby Current (RAS=CAS=W=VIH)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: EDO Mode Current * (RAS=VIL, CAS cycling : tHPC=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0£VIN£Vcc+0.3V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V£VOUT£Vcc)
: Output High Voltage Level (IOH = -2mA)
IO(L)
VOH
VOL
: Output Low Voltage Level (IOL = 2mA)
* NOTE :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one hyper page mode cycle,tHPC.
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
CAPACITANCE (TA = 25°C, Vcc=3.3V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A11(A10), B0]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0, CAS4]
Input/Output capacitance[DQ0 - 71]
CIN1
CIN2
CIN3
CIN4
CDQ1
20
20
80
20
20
pF
pF
pF
pF
pF
-
-
-
-
-
AC CHARACTERISTICS (0°C£TA£70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
90
Max
Min
110
155
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
tRC
131
tRWC
tRAC
tCAC
tAA
50
18
30
60
20
35
3,4,10
3,4,5,14
3,10,14
3,14
Access time from CAS
Access time from column address
CAS to output in Low-Z
8
8
8
8
tCLZ
tOLZ
tCEZ
tT
OE to output in Low-Z
3,14
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
8
18
50
8
20
50
6,11,12,14
2
2
2
30
50
18
36
8
40
60
20
43
10
18
13
10
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
14
14
CAS hold time
CAS pulse width
10K
32
10K
40
13
RAS to CAS delay time
18
13
10
5
4,14
10,14
14
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
20
25
14
8
8
14
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
0
0
8
10
35
0
30
0
14
0
0
8
-2
10
10
18
8
-2
10
10
20
10
-2
15
8,14
14
tRWL
tCWL
tDS
-2
13
9,14
9,14
Data hold time
tDH
Refresh period(4K Ref.)
64
32
64
32
tREF
tREF
tWCS
tCWD
Refresh period(2K Ref.)
Write command set-up time
CAS to W dealy time
0
0
7
7
36
40
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
AC CHARACTERISTICS (0°C£TA£70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V, Output loading CL=100pF
-5
-6
Parameter
RAS to W dealy time
Symbol
Unit
Note
Min
71
48
53
5
Max
Min
83
55
60
5
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7,14
7
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPT
Column address to W delay time
CAS precharge time to W delay time
CAS set-up time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
14
14
14
8
8
3
3
CAS precharge time (C-B-R counter test cycle)
Access time from CAS precharge
Hyper page cycle time
20
20
33
40
3,14
12
tCPA
tHPC
tHPRWC
tCP
25
68
8
30
77
10
60
40
Hyper page read-modify-write cycle time
CAS precharge time(Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
12
50
35
200K
18
200K
20
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tWRP
tWRH
tDOH
tREZ
14
14
OE to data delay
18
5
20
5
14
Output buffer turn off delay time from OE
OE command hold time
18
20
6,11,14
13
15
8
15
15
8
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
14
14
10
3
10
3
14
Output buffer turn off delay time from RAS
Output buffer turn off delay time from W
W to data delay
13
18
15
20
6.11.12
6.11.14
14
3
3
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
20
5
20
5
OE to CAS hold time
CAS hold time to OE
5
5
OE precharge time
5
5
W pulse width(Hyper page cycle)
5
5
Present Detect Read Cycle
PDE to Valid PD bit
10
7
10
7
ns
ns
tPD
PDE to PD bit Inactive
2
2
tPDOFF
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
If tCWD³ tCWD(min), tRWD³ tRWD(min) and tAWD³ tAWD (min),
then the cycle is a read-write cycle and the data output will
contain data read from the selected address. If neither of the
above conditions are satisfied, the condition of the data out
is indeterminated.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are
reference levels for measuring timing of input signals. Transi-
tion times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
2.
Either tRCH or tRRH must be satisfied for a read cycle.
8.
9.
These parameters are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
Measured with a load equivalent to 1TTL loads and 100pF.
Voh=2.0V and Vol=0.8V.
3.
4.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
10.
5.
6.
Assumes that tRCD³ tRCD(max).
11. tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
12.
If RAS goes to high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes to high before RAS high going , the open circuit condi-
tion of the output is achieved by RAS high going.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating
parameter. They are included in the data sheet as electrical
characteristics only. If tWCS³ tWCS(min) the cycle is an early
write cycle and the data out pin will remain high impedance
for the duration of the cycle.
13.
tASC³ tCP min
14. The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tWEZ
tCEZ
tAA
tOEZ
VIH -
tOEA
tOLZ
OE
VIL -
tCAC
tCLZ
tREZ
tRAC
VOH -
DQ
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tASR
tCRP
tRCD
tRSH
VIH -
CAS
VIL -
tCAS
tRAD
tRAL
tRAH
tASC
tCAH
VIH -
COLUMN
ADDRESS
ROW
ADDRESS
A
VIL -
tCWL
tRWL
tWCH
tWCS
VIH -
tWP
W
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tASC
tRAL
tASR
tRAH
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tCWL
tRWL
VIH -
tWP
W
VIL -
VIH -
OE
tOEH
VIL -
tOED
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
VIL -
RAS
CAS
tCRP
tASR
tRCD
tRSH
VIH -
VIL -
tCAS
tCSH
tRAD
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tCWD
tRWL
tCWL
VIH -
VIL -
W
tWP
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
tDS
tDH
tRAC
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
DQ
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
HYPER PAGE READ CYCLE
tRP
tRASP
VIH -
VIL -
RAS
¡ ó
tCSH
tRCD
tRHCP
tHPC
tHPC
tCAS
tHPC
tCAS
tCRP
tASR
tCP
tCP
tCP
tCAS
tCAS
VIH -
VIL -
CAS
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
A
ADDRESS
tRRH
tRCS
tRCH
VIH -
VIL -
W
tCPA
tCAC
tCAC
tAA
tCAC
tAA
tCPA
tOCH
tOEA
tAA
tCPA
tCHO
tOEP
tAA
tCAC
VIH -
VIL -
tOEA
OE
DQ
tOEP
tOEZ
tOEA
tCAC
tDOH
tOEZ
tOEZ
tRAC
VOH -
VOL -
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
tOLZ
tCLZ
VALID
DATA-OUT
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tHPC
tHPC
tRSH
tCAS
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
¡ ó
CAS
tRAD
tRAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
COLUMN
tASC
tCAH
¡ ó
¡ ó
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDR.
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWCH
tWCS
tWP
tWCH
tWCS
tWCH
tWP
¡ ó
VIH -
VIL -
tWP
W
tCWL
tCWL
tCWL
tRWL
¡ ó
¡ ó
VIH -
VIL -
OE
tDS
tDH
tDS
tDH
tDS
tDH
¡ ó
¡ ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
tCP
VIH -
VIL -
tCSH
tRSH
RAS
CAS
tHPRWC
tCRP
tASR
tCRP
tRCD
VIH -
VIL -
tCAS
tCAS
tRAL
tRAD
tRAH
tCAH
tCAH
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
COL.
A
W
ADDR
ADDR
tRWL
tCWL
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tDH
tAA
tAA
tOEZ
tOEZ
tDS
tDS
tRAC
VI/OH -
VI/OL -
DQ
tCLZ
tCLZ
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
READ(tCPA)
VIH -
VIL -
READ(tCAC)
WRITE
READ(tAA)
RAS
tHPC
tHPC
tHPC
tCP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
tCAS
tCAH
CAS
A
tRAD
tRAH
tASR
tASC tCAH
tCAH
tASC
tASC
tCAH
tASC
VIH -
VIL -
COLUMN
COL.
ADDR
COL.
ADDR
ROW
ADDR
COLUMN
ADDRESS
ADDRESS
tRCS
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tDH
tDS
tOEA
tCAC
tAA
tRAC
tWEZ
tREZ
tAA
tWEZ
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
VALID
VALID
DATA-OUT
DQ
DATA-IN
DATA-OUT
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
tRAS
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
VIH -
tCHR
CAS
VIL -
tWRP
tWRH
VIH -
W
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRAS
tRP
tRP
tRAS
VIH -
VIL -
RAS
CAS
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
tRAD
tASR
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tWRH
tWRP
tRRH
VIH -
VIL -
tAA
VIH -
VIL -
tOEA
OE
tCEZ
tOLZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
tOEZ
VOH -
VOL -
DATA-OUT
DQ
OPEN
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRC
tRP
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tASC
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tWRH
tWRP
tWCS
tWCH
VIH -
tWP
W
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCAS
tCSR
VIH -
VIL -
tCHR
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
tRRH
tRCH
tAA
tWRP
tWRH
tRCS
READ CYCLE
tCAC
VIH -
W
VIL -
VIH -
OE
VIL -
tWEZ
tCEZ
tREZ
tOEA
tOEZ
tCLZ
VOH -
DQ
DATA-OUT
VOL -
WRITE CYCLE
tRWL
tWRP
tWRH
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
READ-MODIFY-WRITE
tAWD
tCWL
tRWL
tWRP
tWRH
tRCS
tCWD
VIH -
tWP
W
tCAC
tOEA
VIL -
tAA
VIH -
OE
tOED
tOEZ
VIL -
tDH
tCLZ
tDS
VI/OH -
DQ
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCHS
tCSR
VIH -
CAS
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
VIH -
W
VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tWTS
VIH -
VIL -
tCHR
CAS
W
tWTH
VIH -
VIL -
tCEZ
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
KMM372F400CK/CS
KMM372F410CK/CS
DRAM MODULE
PACKAGE DIMENSIONS
Units : Inches (millimeters)
5.250
(133.350)
0.054
(1.372)
0.118
(3.000)
5.014
(127.350)
R 0.079
(R 2.000)
0.157±0.004
(4.000±0.100)
B
C
A
.118DIA±.004
(3.000DIA±.100)
0.250
(6.350)
0.250
(6.350)
0.350
1.450
2.150
(8.890)
(36.830)
(54.61)
.450
(11.430)
4.550
(115.57)
.150Max
(3.81Max)
TSOP
( Front view )
.350Max
(8.89Max)
SOJ
0.050±0.0039
(1.270±0.10)
( Back view )
0.250
0.250
0.039±.002
(1.000±.050)
(6.350)
(6.350)
0.123±.005
0.123±.005
0.010Max
(3.125±.125)
(3.125±.125)
(0.250 Max)
0.050
(1.270)
0.079±.004
(2.000±.100)
0.079±.004
(2.000±.100)
Detail A
Detail B
Detail C
Tolerances : ±.005(.13) unless otherwise specified
The used device is 4Mx4 DRAM with Fast Page mode, SOJ or TSOP II. (Forward)
DRAM Part No. : KMM372F400CK/CS - KM44V4004CK and KM44V4004CS.
: KMM372F410CK/CS - KM44V4104CK and KM44V4104CS.
Revision History
Rev 0.0 : Aug. 1997
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