KMM374F804BS-6 [SAMSUNG]
EDO DRAM Module, 8MX72, 60ns, CMOS, DIMM-168;
| 型号： | KMM374F804BS-6 |
| 厂家： | 
SAMSUNG |
| 描述： | EDO DRAM Module, 8MX72, 60ns, CMOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：468K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRAM MODULE
KMM374F804BS
KMM374F804BS Fast EDO Mode without buffer
8M x 72 DRAM DIMM with ECC Using 4Mx16 & 4Mx4, 4K Refresh, 3.3V
GENERAL DESCRIPTION
FEATURES
The Samsung KMM374F804BS is a 8Mx72bits Dynamic RAM
high density memory module. The Samsung KMM374F804BS
consists of eight CMOS 4Mx16bits DRAMs in TSOP 400mil
packages and four CMOS 4Mx4bits DRAMs in TSOP 300mil
package and one 2K EEPROM for SPD in 8-pin TSSOP pack-
age mounted on a 168-pin glass-epoxy substrate. A 0.1 or
0.22uF decoupling capacitor is mounted on the printed circuit
board for each DRAM. The KMM374F804BS is a Dual In-line
Memory Module and is intended for mounting into 168 pin
edge connector sockets.
• Part Identification
- KMM374F804BS(4096 cycles/64ms, TSOP II)
• New JEDEC standard proposal without buffer
• Serial Presence Detect with EEPROM
• Extended Data Out Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• LVTTL compatible inputs and outputs
• Single +3.3V±0.3V power supply
• PCB : Height(1000mil), double sided component
PERFORMANCE RANGE
Speed
-5
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
tHPC
20ns
25ns
84ns
104ns
-6
PIN CONFIGURATIONS
PIN NAMES
Pin
Pin Front Pin Front
Front Pin Back Pin Back Pin Back
Pin Name
A0 - A11
DQ0 - DQ63
W0, W2
OE0, OE2
RAS0 - RAS3
CAS0 - CAS7
VCC
Function
Address Input
Data In/Out
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
2
3
4
5
6
7
8
9
VSS
29 CAS1
DQ18 85
DQ19 86 DQ32 114 RAS1 142 DQ51
87 DQ33 115 DU 143 VCC
DQ20 88 DQ34 116 VSS 144 DQ52
VSS 113 CAS5 141 DQ50
DQ0 30 RAS0
DQ1 31 OE0
DQ2 32
DQ3 33
Read/Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power(+3.3V)
Ground
VCC
VSS
A0
NC
DU
NC
VSS
89 DQ35 117
90 VCC 118
91 DQ36 119
92 DQ37 120
A1
A3
A5
A7
A9
145 NC
146 DU
147 NC
148 VSS
149 DQ53
VCC
34
A2
DQ4 35
DQ5 36
DQ6 37
A4
A6
A8
DQ21 93 DQ38 121
VSS
10 DQ7 38
A10
DQ22 94 DQ39 122 A11 150 DQ54
DQ23 95 DQ40 123 *A13 151 DQ55
NC
No Connection
Don't use
11 DQ8 39 *A12
DU
12
VSS
40
VCC
VCC
DU
VSS
96
VSS 124 VCC 152 VSS
13 DQ9 41
14 DQ10 42
15 DQ11 43
DQ24 97 DQ41 125 DU 153 DQ56
DQ25 98 DQ42 126 DU 154 DQ57
DQ26 99 DQ43 127 VSS 155 DQ58
DQ27 100 DQ44 128 DU 156 DQ59
VCC 101 DQ45 129 RAS3 157 VCC
DQ28 102 VCC 130 CAS6 158 DQ60
DQ29 103 DQ46 131 CAS7 159 DQ61
DQ30 104 DQ47 132 DU 160 DQ62
DQ31 105 CB4 133 VCC 161 DQ63
VSS 106 CB5 134 NC 162 VSS
NC 107 VSS 135 NC 163 NC
NC 108 NC 136 CB6 164 NC
NC 109 NC 137 CB7 165 SA0
SDA 110 VCC 138 VSS 166 SA1
SCL 111 DU 139 DQ48 167 SA2
VCC 112 CAS4 140 DQ49 168 VCC
SDA
Serial Address /Data I/O
Serial Clock
SCL
VSS
SA0 -SA2
CB0 - CB7
Address in EEPROM
Check Bit
16 DQ12 44 OE2
17 DQ13 45 RAS2
18
VCC
46 CAS2
* These pins are not used in this module.
19 DQ14 47 CAS3
20 DQ15 48
W2
VCC
NC
NC
21
22
23
24
25
26
27
CB0 49
CB1 50
VSS
NC
NC
VCC
W0
51
52 CB2
53 CB3
54
VSS
55 DQ16
28 CAS0 56 DQ17
DRAM MODULE
KMM374F804BS
FUNCTIONAL BLOCK DIAGRAM
RAS0
RAS1
W0
RAS2
RAS3
W2
OE0
OE2
A0-A11
DQ32~39
LCAS
DQ0~7
LCAS
LCAS
LCAS
CAS0
CAS4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
U2
U4
U6
DQ40~47
DQ8~15
UCAS
DQ8
UCAS
DQ8
UCAS
DQ8
UCAS
DQ8
CAS1
CAS5
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CB0~3
CB4~7
CAS
CAS
CAS
CAS
DQ0
DQ1
DQ2
DQ3
DQ0
U11
DQ0
DQ1
DQ2
DQ3
DQ0
DQ1
DQ2
DQ3
U10
U9
U8
DQ1
DQ2
DQ3
DQ16~23
DQ48~55
LCAS
LCAS
LCAS
LCAS
CAS2
CAS6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
U3
U5
U7
DQ24~31
DQ56~63
UCAS
DQ8
UCAS
DQ8
UCAS
DQ8
UCAS
DQ8
CAS3
CAS7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Serial PD
VCC
Vss
SCL
SDA
0.1 or 0.22uF Capacitor
under each DRAM
To all DRAMs
A0 A1 A2
SA0 SA1 SA2
DRAM MODULE
KMM374F804BS
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC
-0.5 to +4.6
-0.5 to +4.6
-55 to +150
12
V
V
°C
W
Tstg
Power Dissipation
Pd
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
3.0
0
2.0
3.6
0
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
3.3
0
-
V
V
V
V
*1
VCC+0.3
0.8
*2
-
-0.3
*1 : VCC+1.3V at pulse width£15ns which is measured at VCC.
*2 : -1.3V at pulse width£15ns which is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
KMM374F804BS
Symbol
Speed
Unit
Min
Max
-5
-6
-
-
680
620
mA
mA
ICC1
ICC2
ICC3
Don¢t care
-
20
mA
-5
-6
-
-
680
620
mA
mA
-5
-6
-
-
620
560
mA
mA
ICC4
ICC5
ICC6
Don¢t care
-
6
mA
-5
-6
-
-
680
620
mA
mA
II(L)
IO(L)
-10
-10
10
10
uA
uA
Don¢t care
Don¢t care
VOH
VOL
2.4
-
-
V
V
0.4
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
I(IL)
: Operating Current * (RAS, CAS, Address cycling @tRC=min)
: Standby Current (RAS=CAS=W=VIH)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min)
: Standby Current (RAS=CAS=W=VCC-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0£VIN£VCC+0.3V, all other pins not under test=0 V)
I(OL) : Output Leakage Current(Data Out is disabled, 0V£VOUT£VCC)
VOH
VOL
: Output High Voltage Level (IOH = -2mA)
: Output Low Voltage Level (IOL = 2mA)
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.
DRAM MODULE
KMM374F804BS
CAPACITANCE (TA = 25°C, VCC=3.3V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A11]
CIN1
CIN2
CIN3
CIN4
CDQ
70
52
31
38
24
pF
pF
pF
pF
pF
-
-
-
-
-
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0 - RAS3]
Input capacitance[CAS0 - CAS7]
Input/Output capacitance[DQ0-DQ63, CB0-CB7]
AC CHARACTERISTICS (0°C£TA£70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
84
Max
Min
104
153
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
tRC
128
tRWC
tRAC
tCAC
tAA
50
13
25
60
15
30
3,4,9
3,4,5
3,9
3
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
tCLZ
tOLZ
tCEZ
tT
OE to output in Low-Z
3
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
3
13
50
3
13
50
6,12
2
1
1
30
50
8
40
60
10
40
10
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
38
8
CAS pulse width
10K
37
10K
45
RAS to CAS delay time
17
12
5
4
9
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
0
0
7
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
0
13
13
7
10
30
0
25
0
0
0
8
8
0
0
7
10
10
10
10
0
7
8
tRWL
tCWL
tDS
7
16
0
Data hold time
7
10
tDH
Refresh period (4K Ref.)
Write command set-up time
CAS to W dealy time
64
64
tREF
tWCS
tCWD
tRWD
0
0
7
7, 15
7
33
70
38
84
RAS to W dealy time
DRAM MODULE
KMM374F804BS
AC CHARACTERISTICS (0°C£TA£70°C, VCC=3.3V±0.3V. See notes 1,2.)
Test condition : Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
45
47
5
Max
Min
53
58
5
Max
Column address to W delay time
CAS precharge to W delay time
CAS setup time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper page mode cycle time
Hyper page mode read-modify write cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tHPC
tHPRWC
tCP
17
10
5
10
5
28
35
3
20
67
7
25
73
10
60
35
10
10
14
50
30
200K
13
200K
15
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tDOH
tREZ
OE to data delay
10
3
13
3
Output buffer turn off delay time from OE
OE command hold time
13
13
6
5
5
Output data hold time
5
5
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
3
13
13
3
13
13
6,12
6
3
3
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
15
5
15
5
OE to CAS hold time
CAS hold time to OE
5
5
OE precharge time
5
5
W pulse width (Hyper page cycle)
5
5
DRAM MODULE
KMM374F804BS
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
2.
9. Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as a reference point only.
If tRAD is greater than the specified tRAD(max) limit, then
access time is controlled exclusively by tAA.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
10.
tASC³ 6ns, Assume tT = 2.0ns
11. For all of the refresh mode except distributed CAS-before
RAS refresh, 4096 cycle of burst refresh must be executed
within 16ms before and after self-refresh in order to meet
refresh specification.
3.
4.
Measured with a load equivalent to 1 TTL loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit cond-
tion of the output is achieved by RAS high going.
12.
5.
6.
Assumes that tRCD³ tRCD(max).
tASC, tCAH are referenced to the earlier CAS falling edge.
13.
14.
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
tCP is specified from the last CAS rising edge in the previous
cycle to the first CAS falling edge in the next cycle.
7.
tWCS, tRWD, tCWD and tAWD are non-restrictive operating
parameter. They are inclueded in the data sheet as electrical
characteristics only. If tWCS³ tWCS(min), the cycle is an early
write cycle and the data out pin will remain high impedance
for the duration of the cycle. If tCWD³ tCWD(min),
tRWD³ tRWD(min) and tAWD³ tAWD(min), then the cycle is a
read-write cycle and the data output will contain the data
read from the selected address. If neither of the above conti-
tions are satisfied, The condition of the data out is indeterni-
mated.
tCWD is referenced to the later CAS falling edge at word read-
modify-write cycle.
15.
16.
17.
tCWL is specified from W falling edge to the earlier CAS rising
edge.
tCSR is referenced to earlier CAS falling low before RAS tran-
sition low.
8.
Either tRCH or tRRH must be satisfied for a read cycle.
DRAM MODULE
KMM374F804BS
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
CAS
VIL -
tCAS
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tWEZ
tCEZ
tAA
tOEZ
VIH -
tOEA
tOLZ
OE
VIL -
tCAC
tCLZ
tREZ
DATA-OUT
tRAC
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
CAS
VIL -
tCAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCH
tWCS
VIH -
VIL -
tWP
W
OE
DQ
VIH -
VIL -
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tASC
tRAL
tASR
tRAH
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tCWL
tRWL
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
DQ
tOEH
tOED
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
VIL -
RAS
CAS
tCRP
tASR
tRCD
tRSH
VIH -
VIL -
tCAS
tCSH
tRAD
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tCWD
tRWL
tCWL
VIH -
VIL -
W
tWP
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tDS
tDH
tOEZ
tRAC
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
DQ
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
HYPER PAGE READ CYCLE
tRP
tRASP
VIH -
RAS
VIL -
¡ó
tCSH
tRCD
tRHCP
tHPC
tHPC
tCAS
tHPC
tCAS
tCRP
tASR
tCP
tCP
tCP
tCAS
tCAS
VIH -
VIL -
CAS
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
A
tRRH
tRCS
tRCH
VIH -
VIL -
tCPA
W
tCAC
tCAC
tAA
tCHO
tCAC
tAA
tCPA
tOCH
tOEA
tAA
tCPA
tAA
tCAC
tOEP
VIH -
VIL -
tOEA
OE
DQ
tOEP
tOEZ
tOEA
tCAC
tDOH
tOEZ
tOEZ
tRAC
VOH -
VOL -
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
tOLZ
tCLZ
VALID
DATA-OUT
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
VIL -
tRHCP
RAS
¡ó
tHPC
tHPC
tRSH
tCRP
tASR
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
CAS
tRAD
tRAH
¡ó
tCSH
tASC
tCAH
tASC
tCAH
tASC
tCAH
¡ó
¡ó
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDRESS
A
tWCS
tWCH
tWCS
tWP
tWCH
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
tWP
W
tCWL
tCWL
tCWL
tRWL
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDH
tDS
tDH
tDS
tDH
¡ó
¡ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
tCP
VIH -
VIL -
tCSH
tRSH
RAS
CAS
tHPRWC
tCAS
tCRP
tCRP
tRCD
VIH -
VIL -
tCAS
tRAD
tRAH
tRAL
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
ADDR
COL.
ADDR
A
W
tRWL
tCWL
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tDH
tAA
tAA
tOEZ
tOEZ
tDS
tDS
tRAC
VI/OH -
VI/OL -
DQ
tCLZ
tCLZ
VALID
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
VIH -
VIL -
READ(tCAC)
READ(tCPA)
READ(tAA)
WRITE
RAS
tHPC
tHPC
tHPC
tCAS
tCP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAH
tCAS
tCAH
CAS
A
tRAD
tRAH
tASR
tASC tCAH
tASC
tASC
tCAH
tASC
VIH -
VIL -
COLUMN
ADDRESS
COL.
ADDR
COL.
ADDR
ROW
ADDR
COLUMN
ADDRESS
tRCS
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tDH
tDS
tOEA
tCAC
tAA
tRAC
tWEZ
tREZ
tAA
tWEZ
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-OUT
DQ
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
RAS
tRAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tRPC
tCP
tCSR
VIH -
tCHR
CAS
VIL -
tWRP
tWRH
VIH -
W
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
DRAM MODULE
KMM374F804BS
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH -
VIL -
RAS
CAS
tCRP
tASR
tRCD
tRSH
tCHR
VIH -
VIL -
tRAD
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tWRH
tWRP
tRRH
VIH -
VIL -
tAA
VIH -
VIL -
tOEA
OE
tCEZ
tOLZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
tOEZ
DATA-OUT
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRC
tRAS
tRP
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
A
ROW
ADDRESS
COLUMN
ADDRESS
VIL -
tWRH
tWRP
tWCS
tWCH
VIH -
tWP
W
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCAS
tCSR
VIH -
VIL -
tCHR
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
tRRH
tRCH
tAA
tWRP
tWRH
tRCS
READ CYCLE
tCAC
VIH -
W
VIL -
VIH -
OE
VIL -
tWEZ
tCEZ
tREZ
tOEA
tOEZ
tCLZ
VOH -
DQ
DATA-OUT
VOL -
WRITE CYCLE
tRWL
tWRP
tWRH
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
READ-MODIFY-WRITE
tAWD
tCWL
tRWL
tWP
tWRP
tWRH
tRCS
tCWD
VIH -
W
tCAC
tOEA
VIL -
tAA
VIH -
OE
tOED
tOEZ
VIL -
tDH
tCLZ
tDS
VI/OH -
DQ
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
Undefined
DRAM MODULE
KMM374F804BS
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
tRPC
VIH -
RAS
VIL -
tRPC
tCP
tCHS
tCSR
VIH -
CAS
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
VIH -
W
VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tWTS
VIH -
VIL -
tCHR
CAS
W
tWTH
VIH -
VIL -
tCEZ
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
KMM374F804BS
PACKAGE DIMENSIONS
Units : Inches (millimeters)
5.250
(133.350)
0.054
(1.372)
0.118
(3.000)
5.014
(127.350)
R 0.079
(R 2.000)
0.157±0.004
(4.000±0.100)
B
C
A
.118DIA±.004
(3.000DIA±.100)
0.250
(6.350)
0.250
(6.350)
0.350
1.450
2.150
(8.890)
(36.830)
(54.61)
.450
(11.430)
4.550
(115.57)
( Front view )
0.150Max
(3.81Max)
0.050±0.0039
(1.270±0.10)
( Back view )
0.250
(6.350)
0.250
(6.350)
0.039±.002
(1.000±.050)
0.1230±.0050
(3.125±.125)
0.1230±.0050
(3.125±.125)
0.010Max
(0.250 Max)
0.050
(1.270)
0.079±.0040
(2.000±.100)
0.079±.0040
(2.000±.100)
Detail A
Detail B
Detail C
Tolerances : ±.005(.13) unless otherwise specified
The used device is 4Mx16 and 4Mx4 DRAM with EDO mode, TSOP II
DRAM Part No. : KMM374F804BS - KM416V4104BS
- KM44V4004CS
相关型号：
©2020 ICPDF网 联系我们和版权申明