KMM374S6453AT-GL [SAMSUNG]
Synchronous DRAM Module, 64MX72, 6ns, CMOS;
| 型号： | KMM374S6453AT-GL |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM Module, 64MX72, 6ns, CMOS 时钟 动态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KMM374S6453AT
PC100 Unbuffered DIMM
Revision History
Revision 0.1 (March 23, 1999)
• Package dimension and Capacitance changed.
Revision 0.2 (June 11, 1999)
• Skip ICC4 value of CL=2 in DC characteristics in datasheet.
• Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.
• Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.
• Changed Capacitance and DC Characteristics.
• Changed Package Dimension.
•
• Symbol Change Notice
Before
After
I
I
I
Input leakage current (inputs)
IL
I
Input leakage current
LI
Input leakage current (I/O pins)
Output open @ DC characteristic table
IL
Io
Output open @ DC characteristic table
OL
• Test Condition in DC CHARACTERISTIC Change Notice
Symbol
Before
CKE £ VIL(max), tCC = 15ns
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
After
I
I
I
CKE £ VIL(max), tCC = 10ns
CC2P , CC3P
I
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
CC2N , CC3N
Input signals are changed one time during 30ns
Input signals are changed one time during 20ns
I
2 Banks activated
4 Banks activated
CC4
Revision 0.3 (July 5, 1999)
• Added Notes @OPERATING AC PARAMETER
Notes : 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
Rev. 0.3 July 1999
KMM374S6453AT
PC100 Unbuffered DIMM
KMM374S6453AT SDRAM DIMM
64Mx72 SDRAM DIMM with ECC based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
FEATURE
The Samsung KMM374S6453AT is a 64M bit x 72 Synchronous
Dynamic RAM high density memory module. The Samsung
KMM374S6453AT consists of eighteen CMOS 32M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM.
• Performance range
Part No.
Max Freq. (Speed)
125MHz (8ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
KMM374S6453AT-G8
KMM374S6453AT-GH
KMM374S6453AT-GL
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
The KMM374S6453AT is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
Pin Name
A0 ~ A12
Function
Address input (Multiplexed)
Select bank
57
58
59
60
61
62
1
2
3
4
5
6
7
8
9
VSS
29 DQM1
DQ18 85
DQ19 86 DQ32 114 CS1 142 DQ51
87 DQ33 115 RAS 143 VDD
DQ20 88 DQ34 116 VSS 144 DQ52
VSS 113 DQM5 141 DQ50
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ 7
DQ0 30
DQ1 31
DQ2 32
DQ3 33
CS0
DU
VSS
A0
Data input/output
VDD
Check bit (Data-in/data-out)
NC
*VREF 90
89 DQ35 117
VDD 118
A1
A3
A5
A7
A9
145 NC
146 *VREF
147 NC
148 VSS
149 DQ53
CLK0 ~ CLK3 Clock input
VDD
34
A2
CKE0 ~ CKE1 Clock enable input
DQ4 35
DQ5 36
DQ6 37
A4
A6
A8
63 CKE1 91 DQ36 119
64
65
66
VSS
92 DQ37 120
CS0 ~ CS3
RAS
Chip select input
Row address strobe
Column address strobe
Write enable
DQ21 93 DQ38 121
10 DQ7 38 A10/AP
DQ22 94 DQ39 122 BA0 150 DQ54
CAS
11 DQ8 39
12 40
13 DQ9 41
BA1
VDD
VDD
67 DQ23 95 DQ40 123 A11 151 DQ55
WE
68
69
70
VSS
VSS
96
VSS 124 VDD 152 VSS
DQ24 97 DQ41 125 CLK1 153 DQ56
DQ25 98 DQ42 126 A12 154 DQ57
DQM0 ~ 7
VDD
DQM
14 DQ10 42 CLK0
Power supply (3.3V)
Ground
15 DQ11 43
16 DQ12 44
17 DQ13 45
VSS
DU
CS2
71 DQ26 99 DQ43 127 VSS 155 DQ58
VSS
72
73
74
DQ27 100 DQ44 128 CKE0 156 DQ59
VDD 101 DQ45 129 CS3 157 VDD
DQ28 102 VDD 130 DQM6 158 DQ60
*VREF
SDA
Power supply for reference
Serial data I/O
Serial clock
18
VDD
46 DQM2
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61
SCL
76
77
78
20 DQ15 48
DU
VDD
NC
DQ30 104 DQ47 132 *A13 160 DQ62
DQ31 105 CB4 133 VDD 161 DQ63
SA0 ~ 2
WP
Address in EEPROM
Write protection
Don¢t use
21
22
23
24
25
26
27
CB0
CB1
VSS
NC
NC
VDD
WE
49
50
51
52
53
54
VSS 106 CB5 134 NC
162 VSS
163 CLK3
NC
79 CLK2 107 VSS 135 NC
DU
80
81
82
CB2
CB3
VSS
NC
108 NC
136 CB6 164 NC
137 CB7 165 **SA0
NC
No connection
WP 109 NC
**SDA 110 VDD 138 VSS 166 **SA1
*
These pins are not used in this module.
** These pins should be NC in the system
55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2
84
28 DQM0 56 DQ17
VDD 112 DQM4 140 DQ49 168 VDD
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.3 July 1999
KMM374S6453AT
PC100 Unbuffered DIMM
PIN CONFIGURATION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9
A0 ~ A12
BA0 ~ BA1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data input/output mask
DQ0 ~ 63
CB0 ~ 7
Data input/output
Check bit
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
WP pin is connected to VSS through 47KW Resistor.
When WP is "high", EEPROM Programming will be inhibited and the entire memory will
be wirte-protected.
WP
Write protection
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
Rev. 0.3 July 1999
KMM374S6453AT
PC100 Unbuffered DIMM
FUNCTIONAL BLOCK DIAGRAM
CS1
·
·
CS0
DQM0
·
DQM4
·
DQM
DQM
DQM
DQM
CS
U5
CS
CS
U0
CS
U9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U14
·
·
DQM1
DQM5
DQM
DQM
DQM
DQM
CS
U6
CS
CS
U1
CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U15
U10
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
·
DQM6
DQM
DQM
CS
U2
CS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
DQM
CS
U7
CS
U11
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U16
CS3
CS2
DQM2
·
·
·
·
DQM7
DQM
DQM
CS
CS
DQM
DQM
CS
U8
CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
·
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
U12
U17
DQM
DQM
CS
U4
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U13
Serial PD
SDA
VDD
SCL
A0 ~ An, BA0 & 1
SDRAM U0 ~ U17
SDRAM U0 ~ U17
SDRAM U0 ~ U17
SDRAM U0 ~ U17
SDRAM U0 ~ U8
·
A0 A1 A2
WP
RAS
CAS
47KW
SA0 SA1 SA2
10KW
WE
·
CKE1
SDRAM U9 ~ U17
CLK0/1/2/3
U1/U3/U0/U4
U6/U7/U5/U8
U10/U12/U9/U13
U15/U16/U14/U17
U2/U11
·
CKE0
10W
·
10W
DQn
Every DQpin of SDRAM
·
·
VDD
Vss
·
·
·
·
*1
3.3pF
Two 0.1uF Capacitors
per each SDRAM
To all SDRAMs
*1 : For 4 loads, CLK2 & CLK3 only.
Rev. 0.3 July 1999
KMM374S6453AT
PC100 Unbuffered DIMM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
18
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD, VDDQ
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
3.0
VDDQ+0.3
V
1
VIL
0
-
0.8
-
V
2
VOH
V
IOH = -2mA
IOL = 2mA
3
VOL
-
0.4
10
V
ILI
-10
-
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Pin
Symbol
Min
Max
Unit
Address (A0 ~ A12, BA0 ~ BA1)
RAS, CAS, WE
CADD
CIN
50
50
28
18
18
13
13
13
95
95
50
25
30
20
18
18
pF
pF
pF
pF
pF
pF
pF
pF
CKE (CKE0 ~ CKE1)
Clock (CLK0 ~ CLK3)
CS (CS0 ~ CS3)
CCKE
CCLK
CCS
DQM (DQM0 ~ DQM7)
DQ (DQ0 ~ DQ63)
CDQM
COUT1
COUT2
CB (CB0 ~ CB7)
Rev. 0.3 July 1999
KMM374S6453AT
PC100 Unbuffered DIMM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit Note
-8
-H
-L
Burst length = 1
tRC ³ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
1,350
1,260
1,260
mA
mA
1
ICC2P
CKE £ VIL(max), tCC = 10ns
36
36
Precharge standby current in
power-down mode
ICC2PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC2N
288
252
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
mA
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC2NS
Input signals are stable
ICC3P
CKE £ VIL(max), tCC = 10ns
108
108
Active standby current in
power-down mode
ICC3PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
ICC3N
540
450
mA
mA
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 20ns
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC3NS
Input signals are stable
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
tCCD = 2CLKs
ICC4
1,530
2,160
1,305
1,305
2,070
mA
1
2
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
CKE £ 0.2V
2,070
90
mA
mA
Self refresh current
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 0.3 July 1999
KMM374S6453AT
PC100 Unbuffered DIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
·
·
·
·
Output
Output
Z0 = 50W
50pF
50pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-8
-H
-L
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
16
20
20
48
20
20
20
20
50
ns
ns
1
1
1
1
20
Row precharge time
20
ns
tRAS(min)
tRAS(max)
tRC(min)
50
ns
Row active time
100
us
Row cycle time
68
70
70
ns
1
2.5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + 20 ns
1
1
1
2
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
-
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
Rev. 0.3 July 1999
KMM374S6453AT
PC100 Unbuffered DIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
-8
-H
-L
Parameter
Symbol
Unit
ns
Note
1
Min
Max
Min
10
Max
Min
10
Max
CAS latency=3
8
-
CLK cycle time
tCC
1000
1000
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
10
12
6
-
6
6
6
7
CLK to valid
output delay
tSAC
ns
1,2
2
3
-
3
3
3
3
2
1
1
3
3
3
3
2
1
1
Output data
hold time
tOH
ns
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
3
3
2
1
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
6
-
6
6
6
7
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.3 July 1999
KMM374S6453AT
PC100 Unbuffered DIMM
SIMPLIFIED TRUTH TABLE
A12,A11
A9 ~ A0
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
X
OP code
1,2
3
L
L
L
H
X
X
X
X
Entry
3
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
refresh
Exit
L
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Column
address
(A0 ~ A9)
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
L
L
H
H
L
L
H
L
Column
address
(A0 ~ A9)
Write &
column address
H
X
X
V
H
X
L
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
Bank selection
All banks
V
X
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.3 July 1999
KMM374S6453AT
PC100 Unbuffered DIMM
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.250
(133.350)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
B
C
A
.118DIA ± 0.004
(3.000DIA ± 0.100)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
0.250
0.039 ± 0.002
(6.350)
(6.350)
(1.000 ± 0.050)
0.123 ± 0.005
0.008 ±0.006
0.123 ± 0.005
(0.200 ±0.150)
(3.125 ± 0.125)
(3.125 ± 0.125)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail C
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 32Mx8 SDRAM, TSOP
SDRAM Part No. : KM48S32230AT
Rev. 0.3 July 1999
相关型号：
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