KMM375S203CT-GH [SAMSUNG]
Synchronous DRAM Module, 2MX72, 6ns, CMOS, DIMM-168;
| 型号： | KMM375S203CT-GH |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM Module, 2MX72, 6ns, CMOS, DIMM-168 时钟 动态存储器 内存集成电路 |
| 文件： | 总12页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
KMM375S203CT
SDRAM MODULE
Revision History
Revision 4 (May 1998)
-. Input leakage current (Inputs) I IL is updated.
-. Input Capacitances are updated.
Revision 5 (June 1998)
-. "REGE" description is changed.
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
KMM375S203CT SDRAM DIMM
2Mx72 SDRAM DIMM with PLL & Register based on 2Mx8, 4K Ref., 3.3V Synchronous DRAMs with SPD
FEATURE
GENERAL DESCRIPTION
• Performance Range
The Samsung KMM375S203CT is a 2M bit x 72 Synchronous
Dynamic RAM high density memory module. The Samsung
KMM375S203CT consists of nine CMOS 2Mx8 bit Synchro-
nous DRAMs in TSOP-II 400mil packages, two 20-bits Drive
ICs for input control signal, one PLL in 24-pin TSSOP package
for clock and one 2K EEPROM in 8-pin TSSOP package for
Serial Presence Detect on a 168-pin glass-epoxy substrate.
Two 0.1uF decoupling capacitors are mounted on the printed
circuit board in parellel for each SDRAM. The
KMM375S203CT is a Dual In-line Memory Module and is
intented for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable laten-
cies allows the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
Part No.
Max Freq. (Speed)
125MHz (8ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
100MHz (10ns @ CL=3)
KMM375S203CT-G8
KMM375S203CT-GH
KMM375S203CT-GL
KMM375S203CT-G0
• Burst Mode Operation
• Auto & Self Refresh Capability (4096 Cycles/64ms)
• LVTTL Compatible Inputs and Outputs
• Single 3.3V ± 0.3V Power Supply
• MRS Cycle with Address Key Programs
Latency (Access from Column Address)
Burst Length (1, 2, 4, 8 & Full page)
Data Scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial Presence Detect with EEPROM
• PCB : Height(1,300mil), Double Sided Component
PIN CONFIGURATIONS (Front Side/Back Side)
PIN NAMES
Pin
Pin Front Pin Front
Front Pin Back Pin Back Pin Back
Pin Name
A0 ~ A10/AP
BA0
Function
Address Input (Multiplexed)
Select Bank
57
58
59
1
2
3
4
5
6
7
8
9
10
11
12
13
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
29 DQM1
DQ18 85
VSS
113 DQM5 141 DQ50
30
31
32
33
34
35
36
37
CS0
DU
VSS
A0
A2
A4
DQ19 86 DQ32 114 *CS1 142 DQ51
DQ0 ~ DQ63
CB0 ~ CB7
CLK0
Data Input/Output
Check Bit (Data-in/Data-out)
Clock Input
VDD
87 DQ33 115 RAS 143
VDD
60 DQ20 88 DQ34 116
VSS
A1
A3
A5
A7
144 DQ52
61
62
63
64
65
66
67
68
69
70
71
NC
*VREF 90
*CKE1 91 DQ36 119
92 DQ37 120
89 DQ35 117
145
NC
VDD
118
146 *VREF
147 REGE
CKE0
Clock Enable Input
Chip Select Input
Row Address Storbe
Colume Address Strobe
Write Enable
A6
A8
VSS
148
VSS
CS0, CS2
RAS
DQ21 93 DQ38 121
DQ22 94 DQ39 122
A9
BA0
149 DQ53
150 DQ54
38 A10/AP
39 *BA1
CAS
DQ23 95 DQ40 123 *A11 151 DQ55
96 124 152
WE
40
41
VDD
VDD
VSS
VSS
VDD
VSS
DQ9
DQ24 97 DQ41 125 *CLK1 153 DQ56
DQ25 98 DQ42 126 *A12 154 DQ57
DQM0 ~ 7
VDD
DQM
14 DQ10 42 CLK0
Power Supply (3.3V)
Ground
15 DQ11 43
16 DQ12 44
17 DQ13 45
VSS
DU
CS2
DQ26 99 DQ43 127
VSS
155 DQ58
VSS
72 DQ27 100 DQ44 128 CKE0 156 DQ59
73
74
75
VDD
101 DQ45 129 *CS3 157
VDD
*VREF
Power Supply for Reference
Register Enable
Serial Data I/O
18
VDD
46 DQM2
DQ28 102
VDD
130 DQM6 158 DQ60
REGE
SDA
19 DQ14 47 DQM3
DQ29 103 DQ46 131 DQM7 159 DQ61
20 DQ15 48
DU
VDD
NC
76 DQ30 104 DQ47 132 *A13 160 DQ62
77
78
79
80
81
82
83
84
SCL
Serial Clock
21
22
23
24
25
26
27
CB0
CB1
VSS
NC
NC
VDD
WE
49
50
51
52
53
54
DQ31 105 CB4 133
VDD
NC
NC
161 DQ63
162
163 *CLK3
NC
137 CB7 165 **SA0
138 166 **SA1
VSS
106 CB5 134
VSS
SA0 ~ 2
DU
Address in EEPROM
Don¢t use
NC
*CLK2 107
NC 108
VSS
NC
135
CB2
CB3
VSS
136 CB6 164
NC
No Connection
NC/WP 109
**SDA 110
NC
VDD
VSS
WP
Write Protection
55 DQ16
**SCL 111 CAS 139 DQ48 167 **SA2
112 DQM4 140 DQ49 168
*
These pins are not used in this module.
28 DQM0 56 DQ17
VDD
VDD
** These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
PIN CONFIGURATION DESCRIPTION
Pin
Name
System Clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
CKE should be enabled 1CLK+tss prior to valid command.
Row/Column addresses are multiplexed on the same pins.
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA8
A0 ~ A10/AP Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
BA0
Bank Select Address
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
RAS
Row Address Strobe
Column Address Strobe
Write Enable
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data Input/Output Mask
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched. If CLK is held at a high or low logic level ; the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to V CC through 10K ohm Reg-
ister on PCB. So if REGE of module is floating, this module will be operated as regis-
tered mode.
REGE
Register Enable
DQ0 ~ 63
CB0 ~ 7
VDD/VSS
Data Input/Output
Check bit
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
Power Supply/Ground
Power and ground for the input buffers and the core logic.
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
BCKE0
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D0
D1
D2
D3
B0A0~B0A10,BBA0,BRAS0,BCAS0,BWE0
BDQM0
DQ0~7
10W
PCLK1
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
DQ8~15
CB0~7
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM1
10W
CLK
CS
PCLK2
BCS2
CKE
Add,CTL
DQM
DQ0~7
BDQM2
DQ16~23
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
PCLK3
D4
D5
BDQM3
DQ24~31
DQ32~39
10W
PCLK0
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM4
10W
PCLK1
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D6
D7
D8
BDQM5
DQ40~47
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
PCLK2
BDQM6
DQ48~55
DQ56~63
10W
PCLK3
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM7
10W
VSS
Vcc
IY0
3.3pF
PCLK0
A0~A10,CS0
RAS,CAS,WE
B0A0~B0A10,BCS0
SN74ALVCH162836
IY1
IY2
IY3
PCLK1
PCLK2
PCLK3
PCLK4
BRAS0,BCAS0,BWE
CDC2509
CLK
FIBIN
10W
BDQM0,BDQM1,BDQM4,BDQM5
DQM0,1,4,5
REGE
IY4
CLK0
LE
FBOUT
OE
PCLK4
3.3pF
10pF
10kW
Vcc
Serial PD
SN74ALVCH162836
BA0
CS2
CKE0
BBA0
BCS2
BCKE0
SCL
SDA
A0 A1 A2
DQM2,DQM3,DQM6,DQM7
BDQM2,BDQM3,BDQM6,BDQM7
SA0 SA1 SA2
LE
OE
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2
REG
*1
DOUT
Control Signal(RAS,CAS,WE)
*3
*1. Register Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
RAS
CAS
WE
*2. Register Output
RAS
td
tr
td
tr
CAS
WE
*3. SDRAM
CAS latency(refer to *1)
=2CLK+1CLK
1CLK
tSAC
tRAC(refer to *1)
tRAC(refer to *2)
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
DQ
CAS latency(refer to *2)
=2CLK
tRDL
Row Active
Precharge
Command
Row Active
Read
Command
Precharge
Command
Write
Command
td, tr = Delay of Register (SN74ALVCH162836 of TI)
Note : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (SN74ALVCH162836). Therefore, Input/Output signals of read/write function
issued 1CLK earlier as compared to Unbuffered DIMMs.
should be
2. D IN is to be issued 1clock after write command in external timing because D IN is issued directly to module.
: Don¢t Care
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to Vss
Voltage on V DD Supply Relative to Vss
Storage Temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
9
Unit
V
V
°C
W
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended Operating Conditions (Voltage Referenced to V SS = 0V, TA = 0 to 70°C)
Parameter
Supply Voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input High Voltage
3.0
VDDQ+0.3
V
1
Input Low Voltage
VIL
0
-
0.8
-
V
2
IOH = -2mA
IOL = 2mA
3
Output High Voltage
VOH
VOL
IIL
V
Output Low Voltage
-
0.4
2
V
Input Leakage Current (Inputs)
Input Leakage Current (I/O Pins)
-2
-
uA
uA
IIL
-1.5
-
1.5
3,4
Note :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V £ VOUT £ VDDQ.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)
Parameter
Symbol
Min
Max
Unit
Input Capacitance (A 0 ~ A10/AP)
Input Capacitance ( RAS, CAS, WE)
Input Capacitance (CKE0 ~ CKE1)
Input Capacitance (CLK0)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT1
-
-
-
-
-
-
-
-
15
15
15
14
15
15
15
17
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance ( CS0, CS2)
Input Capacitance (DQM0 ~ DQM7)
Input Capacitance (BA0)
Data Input/Output Capacitance (DQ0 ~ DQ63)
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
DC CHARACTERISTICS
(Recommended Operating Condition Unless Otherwise Noted, T A = 0 to 70°C)
Version
CAS
Latency
Parameter
Symbol
Test Condition
Burst Length = 1
tRC ³ tRC(min)
IOL = 0 mA
Unit
mA
Note
-8
-H
-L
-0
Operating Current
(One Bank Active)
ICC1
960
910
910
820
1
ICC2P
CKE £ VIL(max), tCC = 15ns
11
11
Precharge Standby Current
in Power-down Mode
mA
ICC2PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
Input signals are changed one time during
30ns
ICC2N
137
38
Precharge Standby Current
in Non Power-down Mode
mA
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC2NS
ICC3P
CKE £ VIL(max), tCC = 15ns
20
11
Active Standby Current
in Power-down Mode
ICC3PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
Input signals are changed one time during
30ns
ICC3N
227
137
mA
mA
Active Standby Current
in Non Power-down Mode
(One Bank Active)
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC3NS
IOL = 0 mA
Page Burst
tCCD = 2CLKs
3
2
1,140 1,000 1,000 1,000
Operating Current
(Burst Mode)
ICC4
mA
1
910 1,000
497
910
910
450
Refresh Current
ICC5
ICC6
tRC ³ tRC(min)
CKE £ 0.2V
mA
mA
2
3
Self Refresh Current
11
Note :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1 PLL & 2 Drive ICs.
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC Input Levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input Timing Measurement Reference Level
Input Rise and Fall Time
V
tr/tf = 1/1
1.4
ns
V
Output Timing Measurement Reference Level
Output Load Condition
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, I OH = -2mA
VOL (DC) = 0.4V, I OL = 2mA
Output
Output
Z0 = 50W
50pF
50pF
870W
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC Operating Conditions Unless Otherwise Noted)
Version
Parameter
Symbol
Unit
Note
-8
16
20
20
48
-H
20
20
20
50
-L
20
20
20
50
-0
20
26
26
50
Row Active to Row Active Delay
RAS to CAS Delay
tRRD(min)
tRCD(min)
tRP(min)
ns
ns
1
1
1
1
Row Precharge Time
ns
tRAS(min)
tRAS(max)
tRC(min)
ns
Row Active Time
100
us
Row Cycle Time
68
8
70
10
70
10
80
12
ns
1
2
2
2
3
Last Data in to Row Precharge
Last Data in to New Col. Address Delay
Last Data in to Burst Stop
tRDL(min)
tCDL(min)
tBDL(min)
tCCD(min)
ns
1
1
1
2
1
CLK
CLK
CLK
Col. Address to Col. Address Delay
CAS Latency=3
CAS Latency=2
Number of Valid Output Data
ea
4
Note :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
AC CHARACTERISTICS (AC Operating Conditions Unless Otherwise Noted)
-8
-H
-L
-0
Parameter
Symbol
tCC
Unit
ns
Note
1
Min
8
Max
Min
10
Max
Min
10
Max
Min
10
Max
CAS Latency=3
CLK Cycle Time
1000
1000
1000
1000
CAS Latency=2
CAS Latency=3
CAS Latency=2
CAS Latency=3
CAS Latency=2
12
10
12
13
6
6
6
6
6
7
7
8
CLK to Valid
Output Delay
tSAC
ns
1,2
1,2
3
3
3
3
2
1
1
3
3
3
3
2
1
1
3
3
3
3
2
1
1
3
3
Output Data
Hold Time
tOH
ns
CLK High Pulse Width
CLK Low Pulse Width
Input Setup Time
tCH
tCL
3.5
3.5
2.5
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input Hold Time
tSH
tSLZ
CLK to Output in Low-Z
1
CAS Latency=3
CAS Latency=2
6
6
6
6
6
7
7
8
CLK to Output
in Hi-Z
tSHZ
ns
1
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
KMM375S203CT-8
(Unit : Number of Clock)
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
8ns
1
tRDL
8ns
1
CAS
Latency
Frequency
68ns
48ns
20ns
16ns
20ns
8ns
1
125MHz (8.0ns)
100MHz (10.0ns)
83MHz (12.0ns)
75MHz (13.0ns)
66MHz (15.0ns)
3
3
2
2
2
9
7
6
6
6
6
5
4
4
4
3
2
2
2
2
2
2
2
2
2
3
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
KMM375S203CT-H
Frequency
(Unit : Number of Clock)
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
CAS
Latency
70ns
50ns
20ns
20ns
20ns
10ns
10ns
10ns
100MHz (10.0ns)
83MHz (12.0ns)
75MHz (13.0ns)
66MHz (15.0ns)
60MHz (16.7ns)
2
2
2
2
2
7
6
6
5
5
5
5
4
4
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
KMM375S203CT-L
Frequency
(Unit : Number of Clock)
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
CAS
Latency
70ns
50ns
20ns
20ns
20ns
10ns
10ns
10ns
100MHz (10.0ns)
83MHz (12.0ns)
75MHz (13.0ns)
66MHz (15.0ns)
60MHz (16.7ns)
3
2
2
2
2
7
6
6
5
5
5
5
4
4
3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
KMM375S203CT-0
Frequency
(Unit : Number of Clock)
tRC
tRAS
tRP
tRRD
tRCD
tCCD
tCDL
tRDL
CAS
Latency
80ns
50ns
26ns
20ns
26ns
10ns
10ns
12ns
100MHz (10.0ns)
83MHz (12.0ns)
75MHz (13.0ns)
66MHz (15.0ns)
60MHz (16.7ns)
3
3
2
2
2
8
7
7
6
5
5
5
4
4
3
3
3
2
2
2
2
2
2
2
2
3
3
2
2
2
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
SIMPLIFIED TRUTH TABLE
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0
A10/AP
A9 ~ A0
Note
1,2
3
Command
Register
Refresh
Mode Register Set
Auto Refresh
H
X
H
L
L
L
L
L
X
OP Code
H
L
L
L
L
H
X
X
X
X
Entry
3
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
H
3
Bank Active & Row Addr.
H
H
X
X
X
X
V
V
Row Address
Column
Address
(A0 ~ A9)
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4,5
4
Read &
Column Address
L
H
L
H
Column
Address
(A0 ~ A9)
Write &
Column Address
H
H
H
X
X
X
L
L
L
H
H
L
L
L
L
L
X
X
X
V
H
4,5
6
Burst Stop
Precharge
H
H
X
Bank Selection
Both Banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Clock Suspend or
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
X
V
X
DQM
X
X
7
X
X
H
L
X
H
X
H
No Operation Command
H
(V=Valid, X=Don ¢t Care, H=Logic High, L=Logic Low)
Note :
1. OP Code : Operand Code
A0 ~ A10/AP, BA0 : Program Keys. (@ MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/Self refresh can be issued only at both banks precharge state.
4. BA0 : Bank Select Address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A10/AP is "High" at row precharge, BA 0 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t RP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Wirte DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
REV. 5 June 1998
Preliminary
KMM375S203CT
SDRAM MODULE
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157±0.004
(4.000±0.100)
CDC2516
SN74ALVCH162836
B
C
A
.118DIA ±.004
(3.000DIA ±.100)
0.250
(6.350)
1.450
(36.830)
0.250
(6.350)
0.350
(8.890)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150Max
(3.81Max)
SN74ALVCH162836
0.050±0.0039
(1.270±0.10)
0.250
(6.350)
0.250
(6.350)
0.039±.002
(1.000±.050)
0.123±.005
(3.125±.125)
0.123±.005
(3.125±.125)
0.010Max
(0.250 Max)
0.050
(1.270)
0.079±.004
(2.000±.100)
0.079±.004
(2.000±.100)
Detail A
Detail B
Detail C
Tolerances : ±.005(.13) unless otherwise specified
The used device is 2Mx8 SDRAM, TSOP
SDRAM Part No. : KM48S2020CT
REV. 5 June 1998
相关型号：
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