KMM383L3313BT-GZ [SAMSUNG]
DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184;型号: | KMM383L3313BT-GZ |
厂家: | SAMSUNG |
描述: | DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184 动态存储器 双倍数据速率 |
文件: | 总12页 (文件大小:169K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
256MB DDR SDRAM MODULE
(32Mx72(16Mx72*2 bank) based on 16Mx8 DDR SDRAM)
Registered 184pin DIMM
72-bit ECC/Parity
Revision 0.1
Aug. 1999
Rev. 0.1 Aug. 1999
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
Revision History
Revision 0.0 (Mar. 1999)
1.First release for internal usage
Revision 0.1 (Aug. 1999)
1.Modified binning policy
From
To
-Z (133Mhz)
-8 (125Mhz)
-0 (100Mhz)
-Z (133Mhz/266Mbps@CL=2)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz/200Mbps@CL=2)
2.Modified the following AC spec values
From.
-Z
To.
-0
-Z
-Y
-0
tAC
+/- 0.75ns
+/- 0.75ns
+/- 1ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
+/- 0.8ns
+/- 0.8ns
+/- 0.6ns
0.6 ns
tDQSCK
tDQSQ
tDS/tDH
+/- 1ns
+/- 0.5ns
+/- 0.75ns
0.75 ns
0.5 ns
*1
2.5tCK-tDQSS
1tCK +/- 0.75ns
tCK/2 +/- 0.75ns
tCK/2 +/- 0.75ns
2.5tCK-tDQSS
1tCK +/- 1ns
tCK/2 +/- 1ns
tCK/2 +/- 1ns
1tCK
1tCK
1tCK
tCDLR
*1
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
0.9/1.1 tCK
0.4/0.6 tCK
+/-0.8ns
tPRE
*1
tRPST
*1
tHZQ
*1
: Changed description method for the same functionality. This means no difference from the previous version.
3.Changed the following AC parameter symbol From tDQCK To tAC
Output data access time from CK/CK
•
Rev. 0.1 Aug. 1999
- 0 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
KMM383L3313BT DDR SDRAM 184pin DIMM
32Mx72 DDR SDRAM 184pin DIMM based on 16Mx8
2. FEATURE
1. GENERAL DESCRIPTION
• Performance range
The Samsung KMM383L3313BT is 32M bit x 72 Double Data
Rate SDRAM high density memory modules based on first
generation of 128Mb DDR SDRAM respectively. The Samsung
KMM383L3313BT consists of eighteen CMOS 16M x 8 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages, mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The KMM383L3313B-
T is Dual In-line Memory Modules and intended for mounting
into 184pin edge connector sockets.
Part No..
Max Freq. (Speed)
Interface
KMM383L3313BT-G(F)Z
133MHz(7.5ns@CL=2)
SSTL_2
• KMM383L3313BT-G(F)Y 133MHz(7.5ns@CL=2.5)
•
•
•
•
•
•
•
KMM383L3313BT-G(F)0
100MHz(10ns@CL=2)
• Power supply
Vdd: 2.5V ± 0.2V
Power: G - normal, F - Low power
• MRS cycle with address key programs
CAS Latency (Access from column address):2,2.5
Burst length ;2, 4, 8
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
Data scramble ;Sequential & Interleave
• Serial presence detect with EEPROM
• PCB : Height 1700 (mil), double sided component
3. PIN CONFIGURATIONS (Front side/back side)
4. PIN DESCRIPTION
Pin Front
Pin
Front Pin
Front
Pin
Back
Pin
Back
Pin
Back
Pin Name
Function
A0 ~ A11
Address input (Multiplexed)
Bank Select Address
Data input/output
Check bit(Data-in/data-out)
Data Strobe input/output
Clock input
1
2
3
4
5
6
7
8
9
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
32
33
34
35
36
37
38
39
40
A5
DQ24
VSS
DQ25
DQS3 66
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8 77
A0
CB2
VSS
CB3
BA1
KEY
DQ32
VDDQ 85
DQ33 86
DQS4 87
DQ34
VSS
BA0
62
63
64
65
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
93
94
95
96
97
98
99
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
A6
154
155
156
157
158
159
160
161
162
163
164
165
166
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
DQS0 ~ DQS8
CK0,CK0
CKE0,CKE1
CS0, CS1
RAS
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
67
68
69
70
71
72
73
74
75
76
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
DQ46
DQ47
NU
VDDQ
DQ52
DQ53
Clock enable input
Chip select input
Row address strobe
Column address strobe
Write enable
NC
NC
10 /RESET 41
NU
11
12
13
VSS
DQ8
DQ9
42
43
44
45
46
47
48
49
50
51
52
DQ48
DQ49
VSS
NU
NU
*A13
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
*A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
CAS
WE
14 DQS1
15 VDDQ
167 NC,FETEN
DM0 ~ DM8
VDD
Data - in mask
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VDD
DM6
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
Power supply (2.5V)
Power Supply for DQs(2.5V)
Ground
16
17
18
19
20
21
NU
NU
VSS
DQ10
DQ11
CKE0
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
VDDQ
78
79
80
81
82
83
84
VSS
CB6
VDDQ
CB7
VREF
Power supply for reference
Serial EEPROM Power
Serial data I/O
VDDSPD
SDA
22 VDDQ
23
24
KEY
DQ16
DQ17
53
54
55
56
57
58
59
60
61
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
SCL
Serial clock
DM7
SA0 ~ 2
WP
Address in EEPROM
Write protection
25 DQS2
DQ62
DQ63
VDDQ
SA0
SA1
SA2
26
27
28
29
VSS
A9
DQ18
A7
VDDID
RESET
FETEN
NC
VDD identification flag
Reset enable
88
89
90
91
92
DM4
DQ38
DQ39
VSS
WP
SDA
SCL
FET Enable
30 VDDQ
31 DQ19
DQ35
DQ40
No connection
DQ23
DQ44
VDDSPD
NU
No use
* These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 Aug. 1999
- 1 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
5. Functional Block Diagram
RS1
RS0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 7
DQS
CS
D4
CS
DM
I/O 7
DQS
DM
CS
D0
CS DQS
D9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D13
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
CS
D5
CS DQS
D14
DM
DQS
DQS
CS
CS
D1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D10
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
CS DQS
D15
DM
DQS
CS
DM
CS DQS
D2
DQ48
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ16
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D11
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
CS DQS
D16
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
CS DQS
D3
CS DQS
D12
DQ56
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ24
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8
DM
CS DQS
D8
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
Serial PD
V
D0 - D17
DDQ
PLL
CK0,CK0
WP
SDA
V
DD
D0 - D17
A0
A1
A2
SA2
SCL
VREF
D0 - D17
D0 - D17
47KW
SA0 SA1
V
SS
V
DDID
Strap: see Note 4
RCS0
CS0
CS1
BA0-BAN
A0-A11
Notes:
R
E
G
I
S
T
E
R
BA0 -BAn : SDRAMs DQ0 - D17
A0 -An : SDRAMs D0 - D17
RAS : SDRAMs D0 - D17
CAS : SDRAMs DQ0 - D17
CKE : SDRAMs D0 - D8
RCS1
RBA0 - RBAn
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ¹ VDDQ.
RA0 - RA11
RRAS
RAS
CAS
CKE0
CKE1
WE
RCAS
RCKE0
RCKE1
RWE
CKE : SDRAMs D9 - D17
WE: SDRAMs D0 - D17
PCK
PCK
RESET
Rev. 0.1 Aug. 1999
- 2 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
6. ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 3.6
-1.0 ~ 4.6
-0.5 ~ 3.6
-55 ~ +150
18
Unit
V
V
V
VDDQ
TSTG
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
7. POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V)
I/O Supply voltage
Symbol
VDD
Min
2.3
Max
2.7
Unit
V
Note
VDDQ
VREF
2.3
2.7
V
I/O Reference voltage
1.15
1.35
V
1
2
I/O Termination voltage(system)
Input logic high voltage
V
VREF-0.04
VREF+0.18
-0.3
VREF+0.04
VDDQ+0.3
VREF-0.18
VDDQ+0.3
VDDQ+0.6
5
V
TT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
II
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input leakage current
-0.3
V
0.36
V
-5
uA
uA
mA
mA
3
Output leakage current
IOZ
-5
5
Output High Current (V
= 1.95V)
= 0.35V)
IOH
-15.2
15.2
OUT
OUT
Output Low Current (V
IOL
Note :1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-
peak noise on VREF may not exceed 2% of the DC value
2.V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to
TT
TT
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
Rev. 0.1 Aug. 1999
- 3 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
8. DC CHARACTERISTICS
Recommended operating conditions Unless Otherwise Noted,TA=0to70°C)
Version
-Y
CAS
Latency
Parameter
Operating Current
Symbol
Test Condition
Unit Note
-Z
-0
Burst=2 tRC=tRC(min), CL=2.5
IDD1
T.B.D T.B.D T.B.D mA 1
I
=0mA, Active-Read-Precharge
(One Bank Active)
OUT
Precharge Power-down Standby
Current
IDD2P
IDD2N
IDD3P
IDD3N
CKE£VIL(max), tCK=tCK(min), All banks idle
CKE³ VIH(min), CS³ VIH(min), tCK=tCK(min)
All banks idle,CKE£VIL(max),tCK=tCK(min)
T.B.D
T.B.D
T.B.D
mA
mA
mA
mA
Precharge Standby Current
in Non Power-down mode
Active Standby Current
in Power-down mode
One bank; Active-Precharge, tRC=tRAS(max),
tCK=tCK(min)
Active Standby Current
in Non Power-down mode
T.B.D
2.5
2
T.B.D T.B.D T.B.D
Burst=2, tCK=tCK(min),
=0mA
Operating Current(Read)
Operating Current(Write)
I
IDD4R
IDD4W
T.B.D T.B.D T.B.D mA
1
OUT
Burst=2, tCK=tCK(min)
2.5
2
T.B.D T.B.D T.B.D
T.B.D T.B.D T.B.D mA
1
2
Auto Refresh Current
Self Refresh Current
IDD5
IDD6
mA
mA
T.B.D
T.B.D
tRC³ tRFC(min)
CKE£0.2V
Note : 1. Measured with outputs open.
2. Refresh period is 64ms
9. AC Operating Conditions
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC) VREF + 0.35
VIL(AC)
V
V
V
V
VREF - 0.35
VDDQ+0.6
VID(AC) 0.7
1
2
Input Crossing Point Voltage, CK and CK inputs
VIX(AC) 0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
Rev. 0.1 Aug. 1999
- 4 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
10. AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Input reference voltage for Clock
Input signal maximum peak swing
Input signal minimum slew rate
Input Levels(VIH/VIL)
Value
Unit
V
Note
0.5 * VDDQ
1.5
V
1.0
VREF+0.35/VREF-0.35
VREF
V/ns
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
Vtt
V
See Load Circuit
Vtt=0.5*VDDQ
RT=50W
Output
Z0=50W
VREF
=0.5*VDDQ
CLOAD=30pF
(Fig. 1) Output Load Circuit (SSTL_2)
11. Input/Output CAPACITANCE (VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS,
WE )
CIN1
-
12
pF
Input capacitance(CKE0,CKE1)
CIN2
CIN3
-
-
-
-
-
-
12
11
12
16
16
16
pF
pF
pF
pF
pF
pF
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK0)
CIN4
Input capacitance(DM0~DM8)
CIN5
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance(CB0~CB7)
COUT1
COUT2
Rev. 0.1 Aug. 1999
- 5 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
12. AC CHARACTERISTICS. (These AC charicteristics were tested on the Component)
- Z(PC266@CL=2)
- Y(PC266@CL=2.5) - 0(PC200@CL=2)
Parameter
Symbol
Unit Note
Min
65
75
45
20
20
15
2
Max
Min
65
75
48
20
20
15
2
Max
Min
70
80
48
20
20
15
2
Max
Row cycle time
tRC
ns
ns
Refresh row cycle time
Row active time
tRFC
tRAS
tRCD
tRP
12K
12K
12K
ns
RAS to CAS delay
ns
Row precharge time
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
ns
tCK
tCK
tCK
tCK
ns
Last data in to Read command
Last data in to Write command
Col. address to Col. address delay
tCDLR
tCDLW
tCCD
tCK
1
1
1
0
0
0
1
1
1
Clock cycle time
CL=2.0
CL=2.5
7.5
7
15
15
10
7.5
15
15
10
8
15
15
ns
Clock high level width
Clock low level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCL
0.45
-0.75
-0.75
-0.5
0.9
0.55
+0.75
+0.75
+0.5
1.1
0.45
-0.75
-0.75
-0.5
0.9
0.55
+0.75
+0.75
+0.5
1.1
0.45
-0.8
-0.8
-0.6
0.9
0.55
+0.8
+0.8
+0.6
1.1
tCK
ns
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
ns
tCK
tCK
Read Postamble
0.4
0.6
0.4
0.6
0.4
0.6
Data out high impedence time from CK/CK tHZQ
-0.75
0.75
0
+0.75
1.25
-0.75
0.75
0
+0.75
1.25
-0.8
0.75
0
+0.8
1.25
ns
tCK
ns
2
3
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
tDQSS
tWPRES
tWPREH
tDQSH
0.25
0.4
0.25
0.4
0.25
0.4
tCK
DQS-in high level width
0.6
0.6
0.6
0.6
1.1
tCK
DQS-in low level width
tDQSL
tDSC
tIS
0.4
0.9
1.1
1.1
15
0.6
1.1
0.4
0.9
1.1
1.1
15
0.6
1.1
0.4
0.9
1.2
1.2
16
tCK
tCK
ns
DQS-in cycle time
Address and Control Input setup time
Address and Control Input hold time
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tIH
ns
tMRD
tDS
ns
0.5
0.5
0.6
ns
tDH
ns
0.5
0.5
1.75
10
0.6
DQ & DM input pulse width
Power down exit time
tDIPW
tPDEX
tXSW
1.75
10
2
ns
ns
ns
10
Exit self refresh to write command
95
116
Rev. 0.1 Aug. 1999
- 6 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
PC266A
Min Max
PC266B
Min Max
PC200
Min Max
Parameter
Symbol
tXSA
Unit
Note
Exit self refresh to bank active command
Exit self refresh to read command
75
75
80
ns
Cycle
us
tXSR
tREF
tDV
200
15.6
0.35
0.25
35
200
15.6
0.35
0.25
35
200
15.6
0.35
0.25
35
Refresh interval time
128Mb
1
4
Output DQS valid window
DQS write postamble time
tCK
tCK
ns
tWPST
Auto precharge write recovery + Precharge time tDAL
.
1. Maximum burst refresh of 8
2. tHZQ transitions occurs in the same access time windows as valid data transitions. These parameters are not referenced
to a specific voltage level, but specify when the device output is no longer driving.
3. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
4. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
Rev. 0.1 Aug. 1999
- 7 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
13. SIMPLIFIED TRUTH TABLE
A11
A9 ~ A0
CKEn-1
CKEn
CS
RAS
CAS
WE
DM BA0,1
A10/AP
Note
COMMAND
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
H
H
X
X
H
L
L
L
L
L
L
L
L
L
X
X
OP CODE
OP CODE
1, 2
1, 2
3
H
L
L
L
H
X
X
X
X
Entry
3
Refresh
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
X
X
V
V
Row Address
Column
Address
(A0~A7)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
4
4
L
H
L
H
H
Column
Address
(A0~A7)
Write &
Column Address
L
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
X
X
X
Active Power Down
X
X
H
L
Entry
H
Precharge Power Down Mode
X
H
L
Exit
L
H
H
H
X
X
V
X
DM
X
X
8
H
L
X
H
X
H
No Operation Command
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2.EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
Rev. 0.1 Aug. 1999
- 8 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
14. PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.006
(133.350 ± 0.15)
0.089
(2.26)
5.171
(131.350)
5.077
(128.950)
0.78
(19.80)
REG
PLL
REG
A
B
B
2.500
0.10 M
C
B A
A
0.098 Max
(2.47 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.118
(3.00)
0.250
(6.350)
0.157
(4.00)
0.039 ± 0.002
(1.000 ± 0.050)
0.26
(6.62)
0.0787
(2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575
(4.00)
0.10
Detail A
M
C
A
B
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 16Mx8 SDRAM, TSOP
SDRAM Part NO : KM48L16031BT
Rev. 0.1 Aug. 1999
- 9 -
Preliminary
184pin Registered DDR SDRAM MODULE
KMM383L3313BT
184 Pin DDR Registered DIMM Clock Topolgy
0ns
SDRAM
L4
PLL
L5
L3
R=120W
OUT1
L0
L1
L2
CK0
CK0
6pf
120
W
SDRAM
Probe point(reference delay)
Reg1
L7
Reg2
R=240
R=240
W
Clock Reference Net
L6
6pf 120
W
OUT N‘ ’
10W
2.65”
.125”
feedback
W
Z0=60W
tD=2.2ns/ft
LVTTL
16pf
(12pf+4pf)
Note 1
Note 2
Recommended Wire Lengths
L0 = Select Length to Match r‘efence delay.
L1 = .07”(This length should be as short as possible)
L2 = .15” (This length should be as short as possible)
L3 = 2.6”
L4 = .3”
L5 = .6”
L6 = .5” ( This length should be selected to ensure identical clock delay to the SDRAM clock)
L7 = 1.5”
Notes1 :
1. Missing DRAM clock input capacitance “C”: Cap.=1/2 of SDRAM clock capacitance and is connected across CK and CK
2. Characteristic impedance: Z0 = 60 (approx) line to common and 60 (approx) line to line.
3. CK0/CK0 will be the only clock input pari used on Registered DIMMs.
W
W
4. The clock delay from tabs CK0/CK0 will be identical to the delay on the 168pin PC100 and PC133 registered DIMMs,
thereby permitting system designs that support multiple module families.
5. The Clock delay from the input of the PLL clock to the input of any SDRAM or register will be set to 0ns(nominal). This can
be accomplished by setting the PLL feedback wire length and padding capacitance equal to that of the SDRAM clock net.
This delay value is identical to the 168Pin PC100 and PC133 Registered DIMMs.
6. Input,output, and feedback clock lines are terminated from line as shown, and not from line to ground.
Note2: Simulation and hardware analysis will compare the LVTTL 1.5V crosspoint in the rising edge of the clock reference
net to the differential crosspoint on the rising edge of the DDR clock net (at the load).
Rev. 0.1 Aug. 1999
- 10
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