KMM5322104CKU-60 [SAMSUNG]
DRAM Module, 2MX32, 60ns, CMOS, SIMM-72;
| 型号： | KMM5322104CKU-60 |
| 厂家： | 
SAMSUNG |
| 描述： | DRAM Module, 2MX32, 60ns, CMOS, SIMM-72 动态存储器 |
| 文件： | 总15页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRAM MODULE
KMM5322104CKU/CKUG
KMM5322104CKU/CKUG Fast Page Mode with Extended Data Out
2M x 32 DRAM SIMM using 2Mx8 , 2K Refresh, 5V
GENERAL DESCRIPTION
FEATURES
The Samsung KMM5322104CKU is a 2Mx32bits Dynamic
RAM high density memory module. The Samsung
KMM5322104CKU consists of four CMOS 2Mx8bits DRAMs in
28-pin SOJ package mounted on a 72-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on the
printed circuit board for each DRAM. The KMM5322104CKU is
a Single In-line Memory Module with edge connections and is
intended for mounting into 72 pin edge connector sockets.
• Part Identification
- KMM5322104CKU(2048 cycles/32ms Ref, SOJ, Solder)
- KMM5322104CKUG(2048 cycles/32ms Ref, SOJ, Gold)
• Fast Page Mode with Extended Data Out
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDPin & pinout
PERFORMANCE RANGE
• PCB : Height(1000mil), single sided component
Speed
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
tHPC
25ns
30ns
-5
90ns
110ns
-6
PIN CONFIGURATIONS
PIN NAMES
Pin
Symbol
Pin
Symbol
Pin Name
A0 - A10
Function
Address Inputs
Data In/Out
1
2
3
4
5
6
7
8
VSS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
NC
NC
Vss
DQ0 - DQ31
CAS0
CAS2
CAS3
CAS1
RAS0
Res(RAS1)
NC
W
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
RAS0
CAS0 - CAS3
PD1 -PD4
Vcc
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
W
NC
DQ9
Vss
Ground
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
NC
No Connection
Reserved Pin
Res
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1
PD2
PD3
PD4
NC
NC
Vss
Vss
NC
NC
NC
NC
Res(A11)
Vcc
* Pin connection changing available
A8
A9
PD1
PD2
PD3
PD4
NC
Vss
Res(RAS1)
RAS0
NC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
NC
DRAM MODULE
KMM5322104CKU/CKUG
FUNCTIONAL BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RAS
CAS
RAS0
CAS0
U0
DQ0-DQ7
OE
W
A0-A10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RAS
CAS
CAS1
U1
DQ8-DQ15
OE
W
A0-A10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RAS
CAS
CAS2
U2
DQ16-DQ23
OE
W
A0-A10
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RAS
CAS
CAS3
DQ24-DQ31
U3
OE
W
A0-A10
W
A0-A10
Vcc
.1 or .22uF Capacitor
for each DRAM
To all DRAMs
Vss
DRAM MODULE
KMM5322104CKU/CKUG
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC
-1 to +7.0
-1 to +7.0
-55 to +150
4
V
V
°C
W
Tstg
Pd
Power Dissipation
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
4.5
0
2.4
5.5
0
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
5.0
0
-
V
V
V
V
*1
VCC+1
0.8
*2
-
-1.0
*1 : VCC+2.0V/20ns, Pulse width is measured at VCC.
*2 : -2.0V/20ns, Pulse width is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
KMM5322104CKU/CKUG
Symbol
Speed
Unit
Min
Max
ICC1
-5
-6
440
400
mA
mA
-
-
ICC2
ICC3
Don¢t care
-
8
mA
-5
-6
-
-
440
400
mA
mA
ICC4
-5
-6
-
-
360
320
mA
mA
ICC5
ICC6
Don¢t care
-
4
mA
-5
-6
-
-
440
400
mA
mA
II(L)
IO(L)
-20
-5
20
5
uA
uA
Don¢t care
Don¢t care
VOH
VOL
2.4
-
-
V
V
0.4
ICC1
ICC2
ICC3
ICC4
ICC5
ICC6
II(L)
: Operating Current * (RAS, CAS, Address cycling @tRC=min)
: Standby Current (RAS=CAS=W=VIH)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: EDO Mode Current * (RAS=VIL, CAS cycling : tHPC=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0£VIN£Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V£VOUT£Vcc)
: Output High Voltage Level (IOH = -5mA)
IO(L)
VOH
VOL : Output Low Voltage Level (IOL = 4.2mA)
* NOTE :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle, tHPC.
DRAM MODULE
KMM5322104CKU/CKUG
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A10]
Input capacitance[W]
Input capacitance[RAS0]
CIN1
CIN2
CIN3
CIN4
CDQ
35
40
40
20
20
pF
pF
pF
pF
pF
-
-
-
-
-
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0-31]
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
Access time from RAS
90
110
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
tRC
50
13
25
60
15
30
3,4,10
3,4,5
3,10
3
tRAC
tCAC
tAA
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
tCLZ
tCEZ
tT
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
13
50
3
15
50
6,11,12
2
2
2
30
50
13
40
8
40
60
15
50
10
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS hold time
CAS hold time
CAS pulse width
10K
37
10K
45
13
4
RAS to CAS delay time
20
15
5
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
25
30
10
0
0
Row address hold time
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data-in set-up time
8
10
30
0
25
0
0
0
8
8
0
0
10
10
13
8
10
10
15
10
0
tRWL
tCWL
tDS
0
9
9
Data-in hold time
8
10
tDH
Refresh period
32
32
tREF
tWCS
tCSR
tCHR
tRPC
tCPT
Write command set-up time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS precharge to CAS hold time
CAS precharge time (C-B-R counter test)
0
5
0
5
7
10
5
10
5
20
20
DRAM MODULE
KMM5322104CKU/CKUG
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Access time from CAS precharge
Hyper page mode cycle time
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
tCPA
tHPC
tCP
25
8
30
10
60
35
10
10
5
13
CAS precharge time from (Hyper Page Cycle)
RAS pulse width (Hyper Page Cycle)
RAS hold time from CAS precharge
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
Output data hold time
50
30
10
10
5
200K
200K
tRASP
tRHCP
tWRP
tWRH
tDOH
tREZ
tWEZ
tWED
tWPE
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
3
13
13
3
15
15
6,11,12
6,11
3
3
15
5
15
5
W pulse width (Hyper Page Cycle)
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
Either tRCH or tRRH must be satisfied for a read cycle.
8.
9.
These parameters are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
2. VIH(min) and VIL(max) are reference levels for measuring
timing of input signals. Transition times are measured
between VIH(min) and VIL(max) and are assumed to be 5ns
for all inputs.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
10.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
4.
tCEZ(max), tREZ(max), tWEZ(max) and tOEZ(max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
11.
12.
If RAS goes to high before CAS high going, the open circuit
condtion of the output is achieved by CAS high going. If CAS
goes to high before RAS high going, the open circuit condtion
of the output is achieved by RAS high going.
5.
6.
Assumes that tRCD³ tRCD(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
tASC³ tCP min
13.
tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
tWCS³ tWCS(min), the cycle is an early write cycle and the data
out pin will remain high impedance for the duration of the
cycle.
7.
DRAM MODULE
KMM5322104CKU/CKUG
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tWEZ
tCEZ
tAA
tCAC
tCLZ
tREZ
tRAC
VOH -
DQ
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
DRAM MODULE
KMM5322104CKU/CKUG
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tCWL
tRWL
tWCH
tWCS
VIH -
VIL -
tWP
W
tDS
tDH
DATA-IN
VIH -
VIL -
DQ
Don¢t care
Undefined
DRAM MODULE
KMM5322104CKU/CKUG
HYPER PAGE READ CYCLE
tRP
tRASP
VIH -
RAS
VIL -
¡ ó
tCSH
tRCD
tRHCP
tHPC
tHPC
tCAS
tHPC
tCRP
tASR
tCP
tCP
tCP
tCAS
tCAS
tCAS
VIH -
VIL -
CAS
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ROW
A
ADDRESS
ADDR
tRRH
tRCS
tRCH
VIH -
VIL -
W
tCPA
tCAC
tAA
tCAC
tCAC
tAA
tCPA
tAA
tCPA
tAA
tCAC
tDOH
tDOH
tDOH
tRAC
VOH -
VOL -
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
DQ
tCLZ
Don¢t care
Undefined
DRAM MODULE
KMM5322104CKU/CKUG
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
VIH -
tRHCP
RAS
VIL -
¡ ó
tHPC
tHPC
tRSH
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
¡ ó
CAS
tRAD
tRAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
COLUMN
tASC
tCAH
¡ ó
¡ ó
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWCH
tWP
tWCS
tWP
tWCH
tWCS
tWCH
tWP
¡ ó
VIH -
VIL -
W
tCWL
tCWL
tCWL
tRWL
tDS
tDH
tDS
tDH
tDS
tDH
¡ ó
¡ ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ
Don¢t care
Undefined
DRAM MODULE
KMM5322104CKU/CKUG
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
tRAS
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tRPC
tCP
tCSR
VIH -
tCHR
CAS
VIL -
tWRP
tWRH
VIH -
W
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
DRAM MODULE
KMM5322104CKU/CKUG
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRAS
tRP
tRP
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tWRH
tWRP
tRRH
VIH -
VIL -
W
tAA
tCEZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
VOH -
VOL -
DATA-OUT
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
KMM5322104CKU/CKUG
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRC
tRP
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDRESS
COLUMN
ADDRESS
A
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
tWP
W
tDS
tDH
DATA-IN
VIH -
VIL -
DQ
Don¢t care
Undefined
DRAM MODULE
KMM5322104CKU/CKUG
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCAS
tCSR
VIH -
VIL -
tCHR
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
tRRH
tRCH
tAA
tWRP
tWRH
tRCS
READ CYCLE
tCAC
VIH -
W
VIL -
tWEZ
tCEZ
tREZ
tCLZ
VOH -
DQ
DATA-OUT
VOL -
tRWL
WRITE CYCLE
tWRP
tWRH
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
Don¢t care
Undefined
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
DRAM MODULE
KMM5322104CKU/CKUG
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCHS
tCSR
VIH -
CAS
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
VIH -
W
VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tWTS
VIH -
VIL -
tCHR
CAS
W
tWTH
VIH -
VIL -
tCEZ
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
KMM5322104CKU/CKUG
PACKAGE DIMENSIONS
Units : Inches (millimeters)
4.250(107.95)
3.984(101.19)
.133(3.38)
R.062(1.57)
.125 DIA±.002(3.18±.051)
.400(10.16)
1.00(24.50)
.250(6.35)
.080(2.03)
.250(6.35)
R.062±.004(R1.57±.10)
.250(6.35)
3.750(95.25)
( Front view )
.125(3.17)
MIN
( Back view )
.200(5.08)
MAX
Gold & Solder Plating Lead
.100(2.54)
.010(.25)MAX
MIN
.050(1.27)
.041±.004(1.04±.10)
.054(1.37)
.047(1.19)
Tolerances : ±.005(.13) unless otherwise specified
NOTE : The used device is 2Mx8 DRAM
DRAM Part No. : KMM5322104CKU/CKUG -- KM48C2104CK (300mil)
Revision History
Rev 0.0 : Aug. 1997.
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