KMM5364005CSW-6 [SAMSUNG]
EDO DRAM Module, 4MX36, 60ns, CMOS, DIMM-72;
| 型号： | KMM5364005CSW-6 |
| 厂家： | 
SAMSUNG |
| 描述： | EDO DRAM Module, 4MX36, 60ns, CMOS, DIMM-72 动态存储器 |
| 文件： | 总21页 (文件大小：415K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DRAM MODULE
KMM5364005CSW/CSWG
4Byte 4Mx36 SIMM
(4Mx16 & Quad CAS 4Mx4 base)
Revision 0.0
June 1999
DRAM MODULE
KMM5364005CSW/CSWG
Revision History
Version 0.0 (June 1999)
• The 4th. generation of 64Mb DRAM components are applied for this module.
DRAM MODULE
KMM5364005CSW/CSWG
KMM5364005CSW/CSWG EDO Mode
4M x 36 DRAM SIMM Using 4Mx16 & Quad CAS 4Mx4, 4K Refresh, 5V
GENERAL DESCRIPTION
FEATURES
The Samsung KMM5364005C is a 4Mx36bits Dynamic RAM
high density memory module. The Samsung KMM5364005C
consists of two CMOS 4Mx16bits and one CMOS Quad CAS
4Mx4bits DRAMs in TSOP packages mounted on a 72-pin
glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor
is mounted on the printed circuit board for each DRAM. The
KMM5364005C is a Single In-line Memory Module with edge
connections and is intended for mounting into 72 pin edge
connector sockets.
• Part Identification
- KMM5364005CSW(4K cycles/64ms Ref, TSOP, Solder)
- KMM5364005CSWG(4K cycles/64ms Ref, TSOP, Gold)
• Extended Data Out Mode Operation
• CAS-before-RAS & Hidden Refresh capability
• RAS-only refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDpin & pinout
PERFORMANCE RANGE
• PCB : Height(1000mil), single sided component
Speed
-5
tRAC
50ns
60ns
tCAC
13ns
15ns
tRC
tHPC
20ns
25ns
84ns
104ns
-6
PIN CONFIGURATIONS
PIN NAMES
Pin
Symbol
Pin
Symbol
Pin Name
A0 - A11
DQ0 - 35
Function
Address Inputs
Data In/Out
1
2
3
4
5
6
7
8
VSS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
NC
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ17
DQ35
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
NC
W
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
RAS0, RAS2
CAS0 - CAS3
PD1 -PD4
Vcc
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
Vss
Ground
NC
No Connection
PRESENCE DETECT PINS (Optional)
Pin
50NS
60NS
PD1
PD2
PD3
PD4
Vss
NC
Vss
NC
NC
NC
Vss
Vss
PD1
PD2
PD3
PD4
NC
Vss
RAS2
DQ26
DQ8
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
DRAM MODULE
KMM5364005CSW/CSWG
FUNCTIONAL BLOCK DIAGRAM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RAS
RAS0/RAS2
47W
LCAS
CAS0
47W
U0
CAS1
UCAS
OE
DQ8
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
W
A0-A11
RAS
CAS0
CAS1
CAS2
CAS3
W
DQ0
DQ1
DQ2
DQ3
DQ8
DQ17
DQ26
DQ35
U1
A0-A11
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
RAS
LCAS
UCAS
OE
47W
CAS2
47W
U2
CAS3
DQ8
DQ9
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
W
A0-A11
W
A0-A11
Vcc
Vss
0.1 or 0.22uF Capacitor
for each DRAM
To all DRAMs
DRAM MODULE
KMM5364005CSW/CSWG
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC
-1 to +7.0
-1 to +7.0
-55 to +125
3
V
V
°C
W
Tstg
Pd
Power Dissipation
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
4.5
0
2.4
5.5
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
5.0
0
-
V
V
V
V
0
*1
VCC
*2
-
-1.0
0.8
*1 : VCC+2.0V at pulse width£20ns, which is measured at VCC.
*2 : -2.0V at pulse width£ 20ns, which is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
KMM5364005CSW/CSWG
Symbol
Speed
Unit
Min
Max
-5
-6
330
300
mA
mA
-
-
ICC1
ICC2
ICC3
Don¢t care
-
6
mA
-5
-6
-
-
330
300
mA
mA
-5
-6
-
-
260
230
mA
mA
ICC4
ICC5
ICC6
Don¢t care
-
3
mA
-5
-6
-
-
330
300
mA
mA
II(L)
IO(L)
-10
-5
10
5
uA
uA
Don¢t care
Don¢t care
VOH
VOL
2.4
-
-
V
V
0.4
ICC1
: Operating Current * (RAS, CAS, Address cycling @tRC=min)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3
ICC4
ICC5
ICC6
I(IL)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: Hyper Page Mode Current * (RAS=VIL, CAS cycling : tHPC=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0£VIN£Vcc+0.5V, all other pins not under test=0 V)
I(OL) : Output Leakage Current(Data Out is disabled, 0V£VOUT£Vcc)
: Output High Voltage Level (IOH = -5mA)
: Output Low Voltage Level (IOL = 4.2mA)
VOH
VOL
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.
DRAM MODULE
KMM5364005CSW/CSWG
CAPACITANCE (TA = 25°C, VCC=5V, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0-A11]
Input capacitance[W]
CIN1
CIN2
CIN3
CIN4
CDQ
25
31
31
24
17
pF
pF
pF
pF
pF
-
-
-
-
-
Input capacitance[RAS0/RAS2]
Input capacitance[CAS0 - CAS3]
Input/Output capacitance[DQ0 - 35]
AC CHARACTERISTICS (0°C£TA£70°C, Vcc=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Random read or write cycle time
Access time from RAS
84
104
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
tRC
50
13
25
60
15
30
3,4,10
3,4,5
3,10
3
tRAC
tCAC
tAA
Access time from CAS
Access time from column address
CAS to output in Low-Z
3
3
3
3
tCLZ
tCEZ
tT
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
13
50
13
50
6,12
2
1
1
30
50
13
38
8
40
60
15
45
10
20
15
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCS
tWCH
tWP
RAS hold time
CAS hold time
CAS pulse width
10K
37
10K
45
4
9
RAS to CAS delay time
20
15
5
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
25
30
0
0
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command set-up time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
8
10
30
0
25
0
0
0
8
8
7
0
0
0
0
10
10
13
8
10
10
15
10
0
tRWL
tCWL
tDS
0
9
9
Data hold time
8
10
tDH
Refresh period
64
28
64
35
tREF
tCSR
tCHR
tRPC
tCPA
CAS setup time (CAS-before-RAS refresh)
CAS hold time (CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
5
10
5
5
10
5
3
DRAM MODULE
KMM5364005CSW/CSWG
AC CHARACTERISTICS (0°C£TA£70°C, Vcc = 5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-5
-6
Parameter
Symbol
Unit
Note
Min
20
8
Max
Min
25
10
60
35
10
10
5
Max
Hyper page mode cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
tHPC
tCP
50
30
10
10
5
200K
200K
tRASP
tRHCP
tWRP
tWRH
tDOH
tREZ
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
3
13
13
3
15
15
6,12
6
3
3
tWEZ
tWED
tWPE
15
5
15
5
W pulse width
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
8.
9.
Either tRCH or tRRH must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
2.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-
erence levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL(max) and are
assumed to be 5ns for all inputs.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit access time
is controlled by tAA.
10.
3.
4.
Measured with a load equivalent to 2 TTL loads and 100pF.
tASC³ 6ns, Assume tT=2.0ns.
11.
12.
Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
If RAS goes high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes high before RAS high going , the open circuit condition
of the output is achieved by RAS going.
5.
6.
Assumes that tRCD³ tRCD(max).
This parameter defines the time at which the output achieves
the open circuit and is not referenced for VOH or VOL
tWCS is non-restrictive operating parameter. It is included in
the data sheet as electrical characteristics only. If
tWCS³ tWCS(min), the cycle is an early write cycle and the
data out pin will remain high impedance for the duration of
the cycle.
7.
DRAM MODULE
KMM5364005CSW/CSWG
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
COLUMN
ADDRESS
ROW
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tWEZ
tCEZ
tAA
tOEZ
VIH -
tOEA
tOLZ
OE
VIL -
tCAC
tCLZ
tREZ
tRAC
VOH -
DQ
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
CAS
VIL -
tCAS
tRAD
tRAL
tASR
tRAH
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
A
tCWL
tRWL
tWCH
tWCS
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
DQ
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
VIL -
CAS
tRAD
tASC
tRAL
tASR
tRAH
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
tCWL
tRWL
VIH -
VIL -
tWP
W
VIH -
VIL -
OE
DQ
tOEH
tOED
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
VIH -
CAS
tCAS
tCSH
VIL -
tRAD
tRAH
tASR
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tCWD
tRWL
tCWL
VIH -
VIL -
W
tWP
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
tDS
tDH
tRAC
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
DQ
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
HYPER PAGE READ CYCLE
tRP
tRASP
VIH -
RAS
VIL -
¡ó
tCSH
tRCD
tRHCP
tHPC
tHPC
tCAS
tHPC
tCAS
tCRP
tASR
tCP
tCP
tCP
tCAS
tCAS
VIH -
VIL -
CAS
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
ROW
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
A
ADDRESS
ADDR
tRRH
tRCS
tRCH
VIH -
VIL -
tCPA
W
tCAC
tCAC
tAA
tCAC
tAA
tCPA
tOCH
tOEA
tAA
tCPA
tCHO
tOEP
tAA
tCAC
VIH -
VIL -
tOEA
OE
DQ
tOEP
tOEZ
tOEA
tCAC
tDOH
tOEZ
tOEZ
tRAC
VOH -
VOL -
VALID
DATA-OUT
VALID
VALID
DATA-OUT
DATA-OUT
tOLZ
tCLZ
VALID
DATA-OUT
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
tCAS
CAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tRCH
tRRH
VIH -
W
VIL -
tWEZ
tCEZ
tAA
tOEZ
VIH -
tOEA
tOLZ
OE
VIL -
tCAC
tCLZ
tREZ
tRAC
VOH -
DQ
DATA-OUT
OPEN
VOL -
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
tCP
VIH -
VIL -
tCSH
tRSH
RAS
CAS
tHPRWC
tCRP
tCRP
tRCD
VIH -
VIL -
tCAS
tCAS
tRAL
tRAD
tRAH
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
COL.
ADDR
A
W
ADDR
tRWL
tCWL
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tDH
tAA
tAA
tOEZ
tOEZ
tDS
tDS
tRAC
VI/OH -
VI/OL -
DQ
tCLZ
tCLZ
VALID
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
VIH -
VIL -
READ(tCAC)
READ(tCPA)
READ(tAA)
WRITE
RAS
tHPC
tHPC
tHPC
tCAS
tCP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAH
tCAS
tCAH
CAS
A
tRAD
tRAH
tASR
tASC tCAH
tASC
tASC
tCAH
tASC
VIH -
VIL -
COLUMN
COL.
ADDR
COL.
COLUMN
ROW
ADDR
ADDRESS
ADDR
ADDRESS
tRCS
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tDH
tDS
tOEA
tCAC
tAA
tRAC
tWEZ
tREZ
tAA
tWEZ
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
DQ
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
tRAS
RAS
VIL -
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tRPC
tCP
tCSR
VIH -
tCHR
CAS
VIL -
tWRP
tWRH
VIH -
W
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
DRAM MODULE
KMM5364005CSW/CSWG
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRAS
tRP
tRP
tRAS
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
VIL -
CAS
tRAD
tASR
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tWRH
tWRP
tRRH
VIH -
VIL -
tAA
VIH -
VIL -
tOEA
OE
tCEZ
tOLZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
tOEZ
VOH -
VOL -
DATA-OUT
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRC
tRP
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
ROW
ADDRESS
A
W
tWRH
tWRP
tWCS
tWCH
VIH -
VIL -
tWP
VIH -
VIL -
OE
DQ
tDS
tDH
DATA-IN
VIH -
VIL -
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
VIL -
tRAS
RAS
CAS
tCPT
tRSH
tCSR
VIH -
VIL -
tCHR
tCAS
tRAL
tASC
tCAH
VIH -
VIL -
COLUMN
ADDRESS
A
tRRH
tRCH
tAA
tWRP
tWRH
READ CYCLE
tRCS
tCAC
VIH -
W
VIL -
VIH -
OE
VIL -
tWEZ
tCEZ
tREZ
tOEA
tOEZ
DATA-OUT
tCLZ
VOH -
DQ
VOL -
WRITE CYCLE
tRWL
tWRP
tWRH
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
READ-MODIFY-WRITE
tAWD
tCWL
tRWL
tWP
tWRP
tWRH
tRCS
tCWD
VIH -
W
tCAC
tOEA
VIL -
tAA
VIH -
OE
tOED
tOEZ
VIL -
tDH
tCLZ
tDS
VI/OH -
DQ
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
Undefined
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
DRAM MODULE
KMM5364005CSW/CSWG
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCHS
tCSR
VIH -
CAS
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
VIH -
W
VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tWTS
VIH -
VIL -
tCHR
CAS
W
tWTH
VIH -
VIL -
tCEZ
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
KMM5364005CSW/CSWG
PACKAGE DIMENSIONS
Units : Inches (millimeters)
4.250(107.95)
3.984(101.19)
.133(3.38)
R.062(1.57)
.125 DIA±.002(3.18±.051)
.400(10.16)
1.000(25.40)
.250(6.35)
R.062±.004(R1.57±.10)
.080(2.03)
.250(6.35)
.250(6.35)
3.750(95.25)
( Front view )
( Back view )
Gold/Solder Plating Lead
.100(2.54)
MAX
.010(.25)MAX
0.125
MIN
(3.20MIN)
.050(1.27)
.041±.004(1.04±.10)
.054(1.37)
.047(1.19)
Tolerances : ±.005(.13) unless otherwise specified
NOTE : The used device is 4Mx16 & Quad CAS 4Mx4 DRAM, TSOPII
DRAM Part No. : KMM5364005CSW/CSWG -- KM416C4104CS & KM44C4005CS(300 mil)
相关型号：
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