KMM965G511APN-G7_技术文档

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

4MB SGRAM MODULE

(512Kx64 SODIMM based on 512Kx32 SGRAM)

Unbuffered SGRAM

Graphics

64-bit Non-ECC/Parity

144-pin SODIMM

Revision 0.0

July 1999

Rev. 0.0 (Jul. 1999)

- 1 -

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

Revision History

Revision 0.0 (July 1999)

• First edition

Rev. 0.0 (Jul. 1999)

- 2 -

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

KMM965G511AQ(P)N / KMM966G511AQ(P)N SGRAM SODIMM

512Kx64 SGRAM SODIMM based on 512Kx32, 2K Refresh, 3.3V Synchronous Graphic RAMs

FEATURE

GENERAL DESCRIPTION

• Performance range

Part NO.

The Samsung KMM965(6)G511AQ(P)N is a 512K bit x 64

Synchronous Graphic RAM high density memory module. The

Samsung KMM965(6)G511AQ(P)N consists of two CMOS

512K x 32 bit Synchronous Graphic RAMs in 100pin QFP

packages mounted on a 144pin glass-epoxy substrate. Five

0.1uF decoupling capacitors are mounted on the printed

circuit board for each Synchronous GRAM. The

KMM965(6)G511AQ(P)N is a Small Outline Dual In-line Mem-

ory Module and is intended for mounting into 144-pin edge

connector sockets.

Max. Freq. (tCC)

KMM965G511AQ(P)N-G5

KMM965G511AQ(P)N-G6

KMM965G511AQ(P)N-G7

KMM965G511AQ(P)N-G8

* KM965G511AQN : based on PQFP Component

KM965G511APN : based on TQFP Component

• Burst Mode Operation

• BLOCK-WRITE and Write-per-bit capability

• Independent byte operation via DQM0 ~ 7

• Auto & Self Refresh Capability (2048 cycles / 32ms)

• LVTTL compatible inputs and outputs

• Single 3.3V±0.3V power supply

• MRS cycle with address key programs.

CAS Latency (2, 3)

Burst Length (1, 2, 4, 8 & Full page)

Data Scramble (Sequential & Interleave)

• Optional Serial PD with EEPROM (KMM966G511A)

• Resistor Strapping Options for speed and CAS Latency

• PCB : Height(1000mil), single sided components

200MHz (5ns) @CL=3

166MHz (6ns) @CL=3

143MHz (7ns) @CL=3

125MHz (8ns) @CL=3

Synchronous design allows precise cycle control with the use

of system clock. I/O transactions are possible on every clock

cycle. Range of operating frequencies, programmable laten-

cies and burst lengths allows the same device to be useful for a

variety of high bandwidth, high performance memory system

PIN CONFIGURATIONS (Front Side / Back Side)

PIN NAMES

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

Pin Name

A0 ~ A9

Function

1

3

5

7

9

VSS

2

4

6

8

VSS

95 DQ31 96 DQ30

97 DQ29 98 DQ28

99 DQ27 100 DQ26

101 DQ25 102 DQ24

Address Input(multiplexed)

Bank Select Address

Data Input / Output

Voltage Key

DQ63

DQ61

DQ59

DQ62

DQ60

DQ58

BA(A10)

DQ0 ~ 63

51

53

55

57

59

61

63

65

67

69

71

73

75

77

79

RSVD

VSS

52 RSVD

54 RSVD

CLK0, *CLK1 Clock Input

DQ57 10 DQ56

12

103

VSS

104

VSS

56

VSS

CKE

Clock Enable Input

11

VDD

105 DQ23 106 DQ22

107 DQ21 108 DQ20

109 DQ19 110 DQ18

111 DQ17 112 DQ16

DSF

RFU

VDD

58 RFU

60 RFU

62 **SBA

13 DQ55 14 DQ54

15 DQ53 16 DQ52

17 DQ51 18 DQ50

19 DQ49 20 DQ48

CS0, *CS1

RAS

Chip Select Input

Row Address Strobe

Column Address Strobe

Write Enable

64

VDD

CAS

113

VDD

114

VDD

CS1

RAS

WE

66 CS0

68 CAS

70 CKE

WE

21

VSS

22

VSS

115 DQM3 116 DQM2

117 DQM1 118 DQM0

23 DQM7 24 DQM6

25 DQM5 26 DQM4

27

29 DQ47 30 DQ46

31 DQ45 32 DQ44

33 DQ43 34 DQ42

35 DQ41 36 DQ40

DSF

Define Special Function

DQM

119

VSS

120

VSS

CLK1

VDD

RSVD

(A11)

72

74 CLK0

76

78 RSVD

80 A8

VSS

DQM0 ~ 7

VDD

28

VDD

121 DQ15 122 DQ14

123 DQ13 124 DQ12

125 DQ11 126 DQ10

127 DQ9 128 DQ8

Power Supply (3.3V)

Ground

VDD

VSS

**SDA

**SBA

**SCL

RSVD

RFU

Serial Address Data I/O

EEPROM Device Address

Serial Clock

129

VDD

130

VDD

37

VSS

38

VSS

131 DQ7 132 DQ6

133 DQ5 134 DQ4

135 DQ3 136 DQ2

137 DQ1 138 DQ0

81 BA(A10) 82 A9/AP

39 DQ39 40 DQ38

41 DQ37 42 DQ36

43 DQ35 44 DQ34

45 DQ33 46 DQ32

83

85

87

89

91

93

A7

VSS

A5

84

86

88

90

92

94

A6

VSS

A4

Reserved

Reserved for future use

No Connection

139

141 **SDA 142 **SCL

143 144

VSS

140

VSS

NC

A3

A1

VDD

A2

A0

VDD

47

VDD

48

VDD

* These pins are not used in this module.

** These pins should be NC in the system

which does not support SPD.

49 RSVD 50 RSVD

VDD

SAMSUNG ELECTRONICS CO. Ltd. reserves the right to change products and specifications without notice.

Rev. 0.0 (Jul. 1999)

- 3 -

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

PIN CONFIGURATION DESCRIPTION

Name

System Clock

Input Function

CLK

CS

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Chip Select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one clock + tSS prior to new command.

Disable input buffers for power down in standby.

CKE

Clock Enable

Row / column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA9, column address : CA0 ~ CA7

A0 ~ A9

BA(A10)

RAS

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Bank Select Address

Row Address Strobe

Column Address Strobe

Write Enable

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

WE

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

DQM0 ~ 7

Data Input/Output Mask

DQ0 ~ 63

DSF

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

Enables write per bit, block write and special mode register set.

Power and ground for the input buffers and the core logic.

Define Special Function

Power Supply/Ground

VDD/VSS

RESISTOR STRAPPING OPTIONS

Three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing.Timing information

for each clock frequency is indicated in the section titled AC CHARATERISTICS.

Clock Frequency and Memory Timing

Cycle Time

8ns

DQ30

DQ29

1

0

1

0

1

7ns

6ns

5ns

CAS Latency

DQ31

3

0

1

2 and 3

Rev. 0.0 (Jul. 1999)

- 4 -

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

FUNCTIONAL BLOCK DIAGRAM

·

CS0

DQM0

DQ0

DQM4

DQ32

DQM0

DQ0

DQM0

DQ0

·

U0

U1

DQ7

DQ39

DQM5

DQM1

DQ8

DQ40

·

DQ15

DQ47

DQM2

DQM6

DQM2

DQ16

DQ48

·

DQ23

DQ55

DQM3

DQM7

DQM3

DQ24

DQ56

·

DQ31

DQ63

0W

U0 to U1

CKE

CLK0

U0, U1

RAS

CAS

WE

DSF

A(9:0)

BA(A10)

Serial PD

SCL

SDA

A0 A1 A2

VDD

Vss

·

Five 0.1uF Capacitors

per SGRAM device

To all SGRAMs

SBA

VSS

* Serial PD is optional

Rev. 0.0 (Jul. 1999)

- 5 -

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to VSS)

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD

Value

-1.0 ~ 4.6

-55 ~ +150

2

Unit

V

TSTG

°C

W

Power dissipation

PD

Short circuit current

IOS

50

mA

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V)

Parameter

Supply voltage

Symbol

VDD

VIH

Min

3.0

2.0

-0.3

2.4

-

Typ

Max

3.6

Unit

V

Note

3.3

Input high voltage

3.0

VDD+0.3

0.8

V

Input low voltage

VIL

0

-

V

Note 1

IOH = -2mA

IOL = 2mA

Note 2

Output high voltage

Output low voltage

Input leakage current

Output leakage current

Output loading conditon

VOH

VOL

ILI

-

V

-

0.4

V

-20

-10

-

20

uA

ILO

-

10

Note 3

See Figure 1

Note :

1. VIL(min.) = -1.5V AC (pulse width £ 5ns)

2. Any input 0V £ VIN £ VDD + 0.3V, all other pins are not under test = 0V.

3. Dout is disabled, 0V £ VOUT £ VDD

CAPACITANCE (VCC = 3.3V, TA = 25°C, f = 1MHz)

Parameter

Symbol

Min

Max

Unit

Input capacitance (A0 ~ A9, BA)

Input capacitance (RAS, CAS, WE, CKE, DSF)

Input capacitance (CLK0)

CIN1

CIN2

CIN3

CIN4

CIN5

COUT

-

18

14

15

pF

Input capacitance (CS0)

Input capacitance (DQM0 ~ DQM7)

Data input/output capacitance (DQ0 ~ DQ63)

Rev. 0.0 (Jul. 1999)

- 6 -

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V)

Speed

-6 -7

400 360 320 300

CAS

Latency

Parameter

Symbol

Test Condition

Unit Note

-5

-8

3

2

Operating Current

(One Bank Active)

Burst Length =1

tRC ³ tRC(min), tCC ³ tCC(min), Io = 0mA

ICC1

mA

2

-

300

ICC2P

CKE £ VIL(max), tCC = 15ns

4

Precharge Standby Current

in power-down mode

ICC2PS

CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

ICC2N

60

30

Input signals are changed one time during 30ns

Precharge Standby Current

in non power-down mode

mA

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC2NS

ICC3P

CKE £ VIL(max), tCC = 15ns

CKE £ VIL(max), tCC = ¥

6

Active Standby Current

in power-down mode

ICC3PS

CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns

ICC3N

100

60

Active Standby Current

in non power-down mode

(One Bank Active)

Input signals are changed one time during 30ns

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC3NS

3

540 520 460 400

320

400 360 320 300

300

Operating Current

(Burst Mode)

Io = 0 mA, Page Burst

All bank Activated, tCCD = tCCD(min)

ICC4

ICC5

2

3

2

3

2

-

Refresh Current

tRC ³ tRC(min)

mA

-

Self Refresh Current

ICC6

ICC7

CKE £ 0.2V

4

Operating Current

(One Bank Block Write)

tCC ³ tCC(min), Io=0mA, tBWC(min)

460 400 340 300 mA

Note :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open. Address are changed only one time during tcc(min).

3. Refresh period is 32ms. Address are changed only one time during tcc(min).

Rev. 0.0 (Jul. 1999)

- 7 -

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)

Parameter

Value

Vih/Vil = 2.4V / 0.4V

1.4V

AC input levels

Input timing measurement reference level

Input rise and fall time(See note 3)

Output timing measurement reference level

Output load condition

tR/tF=1ns/ 1ns

1.4V

See Fig. 2

3.3V

Vtt = 1.4V

1200W

50W

VOH (DC) = 2.4V, IOH = -2mA

·

Output

Z0=50W

VOL (DC) = 0.4V, IOL = 2mA

30pF

870W

(Fig. 1) DC Output Load Circuit

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

(Fig. 2) AC Output Load Circuit

-5

-6

-7

-8

Parameter

Symbol

tCC

Unit Note

Min

Max

Min

Max

Min

Max

Min

8

Max

CAS Latency=3

5

-

6

7

CLK cycle time

1000

ns

1

CAS Latency=2

CAS Latency=3

CAS Latency=2

-

10

-

4.5

5.5

-

5.5

6

-

CLK to valid

output delay

tSAC

1, 2

-

Output data hold time

CLK high pulse width

tOH

tCH

2

-

2.5

-

2.5

ns

2

3

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

CAS Latency=3

CAS Latency=2

-

3

-

3

-

2

-

2.5

-

3

CLK low

pulse width

ns

3

tCL

tSS

-

1.5

-

1.5

-

1.75

2

2.5

1

Input setup time

-

1

-

Input hold time

tSH

1

-

1

-

ns

3

2

CLK to output in Low-Z

tSLZ

1

CAS latency=3

CAS latency=2

4.5

-

5.5

-

5.5

-

6

CLK to output

in Hi-Z

tSHZ

ns

-

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Rev. 0.0 (Jul. 1999)

- 8 -

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

-5

-6

-7

-8

CAS Latency

CLK cycle time

CL

3

5

2

-

3

6

2

-

3

7

2

-

3

8

2

CLK

ns

tCC(min)

tRRD(min)

tRCD(min)

tRP(min)

tRAS(min)

tRAS(max)

10

Row active to row active delay

RAS to CAS delay

2

CLK

us

1

4

8

-

3

7

-

3

7

-

3

6

2

5

Row precharge time

Row active time

Row cycle time

100

tRC(min)

12

-

10

-

10

-

9

7

CLK

1

Last data in to row precharge

Last data in to new col.address delay

Last data in to burst stop

tRDL(min)

tCDL(min)

tBDL(min)

tCCD(min)

tBPL(min)

tBWC(min)

tMRS(min)

2

1

2

1

2

1

CLK

2, 5

2

Col. address to col. address delay

Block Write data-in to PRE command

Block write cycle time

3

4

Mode Register Set cycle time

CAS Latency=3

CAS Latency=2

Number of valid output data

ea

Version

Parameter

Symbol

Unit

-5

5

-6

-7

7

-8

CLK cycle time

tCC(min)

tRRD(min)

tRCD(min)

tRP(min)

6

8

ns

us

ns

Row active to row active delay

RAS to CAS delay

10

20

40

12

18

42

14

21

49

16

20

48

Row precharge time

tRAS(min)

tRAS(max)

tRC(min)

Row active time

Row cycle time

100

60

70

Note :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer. Refer to the following ns-unit based AC table.

2. Minimum delay is required to complete write.

3. This parameter means minimum CAS to CAS delay at block write cycle only.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. For -6/7/8, tRDL =1CLK product can be supported within restricted amounts and it will be distinguished by bucket code

"NV". From the next generation, tRDL will be only 2CLK for every clock frequency.

Rev. 0.0 (Jul. 1999)

- 9 -

SGRAM MODULE

SIMPLIFIED TRUTH TABLE

COMMAND

KMM965G511AQ(P)N / KMM966G511AQ(P)N

CKEn-1 CKEn CS RAS CAS WE DSF DQM A10 A9 A8~ A0

Note

1, 2

1,2,7

3

Register

Mode Register Set

Special Mode Register Set

Auto Refresh

L

H

L

X

L

X

OP CODE

H

Refresh

H

L

H

L

X

Entry

3

Self

L

H

X

H

X

H

X

3

Refresh

Exit

H

X

H

3

Bank Active

& Row Addr.

Write Per Bit Disable

Write Per Bit Enable

L

4, 5

4,5,9

4

H

L

H

L

H

L

V

Row Address

H

Read &

Column Address

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

L

H

L

Column

Address

L

4, 6

4, 5

4,5,6,9

4, 5

4,5,6,9

7

Write &

Column Address

Column

Address

H

L

Block Write &

Column Addr.

Column

Address

L

H

Burst Stop

Precharge

H

X

L

H

L

H

L

X

Bank Selection

Both Banks

V

X

L

X

H

L

H

X

L

H

X

H

X

V

X

H

X

H

X

V

X

H

X

H

X

V

X

Entry

H

L

X

Clock Suspend or

Active Power Down

X

Exit

L

H

L

X

Entry

H

L

Precharge Power Down Mode

V

X

Exit

L

H

X

H

DQM

H

X

V

X

8

L

H

X

H

X

H

X

No Operation Command

X

H

(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)

Note :

1. OP Code : Operand Code

A0 ~ A10 : Program keys. (@MRS)

A5, A6 : LMR or LCR select. (@SMRS)

Color register exists only one per DQi which both banks share.

So dose Mask Register.

Color or mask is loaded into chip through DQ pin.

2. MRS can be issued only at both banks precharge state.

SMRS can be issued only if DQ¢s are idle.

A new command can be issued at the next clock of MRS/SMRS.

Rev. 0.0 (Jul. 1999)

- 10

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

SIMPLIFIED TRUTH TABLE

3. Auto refresh functions as same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by "Auto".

Auto/Self refresh can be issued only at both precharge state.

4. A10 : Bank select address.

If "Low" at read, (block) write, Row active and precharge, bank A is selected.

If "High" at read, (block) write, Row active and precharge, bank B is selected.

If A9 is "High" at Row precharge, A10 is ignored and both banks are selected.

5. It is determined at Row active cycle.

whether Normal/Block write operates in write per bit mode or not.

For A bank write, at A bank Row active, for B bank write, at B bank Row active.

Terminology : Write per bit =I/O mask

(Block) Write with write per bit mode=Masked(Block) Write

6. During burst read or write with auto precharge, new read/(block) write command cannot be issued.

Another bank read/(block) write command can be issued at tRP after the end of burst.

7. Burst stop command is valid only at full page burst length.

8. DQM sampled at positive going edge of a CLK.

masks the data-in at the very CLK(Write DQM latency is 0)

but makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)

9. Graphic features added to SDRAM¢s original features.

If DSF is tied to low, graphic functions are disabled and chip operates as a 16M SDRAM with 32 DQ¢s.

SGRAM vs SDRAM

Function

MRS

Bank Active

Write

DSF

L

H

L

H

L

H

Bank Active

with

Write per bit

Disable

Bank Active

with

Write per bit

Enable

SGRAM

Function

Normal

Write

Block

Write

MRS

SMRS

If DSF is low, SGRAM functionality is identical to SDRAM functionality.

SGRAM can be used as an unified memory by the appropriate DSF control

--> SGRAM=Graphic Memory + Main Memory

Rev. 0.0 (Jul. 1999)

- 11

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Function

RFU

W.B.L

TM

CAS Latency

BT

Burst Length

Test Mode

Type

CAS Latency

Burst Type

Burst Length

A8

0

A7

0

A6

0

A5

0

A4

0

Latency

A3

0

Type

A2

0

A1

0

A0

0

BT=0

BT=1

Reserved

4

Mode Register Set

Reserved

-

Sequential

Interleave

1

2

0

1

Vendor

Use

Only

0

1

0

1

0

1

0

2

0

1

0

4

1

0

1

3

0

1

8

Write Burst Length

Length

1

0

Reserved

1

0

Reserved

256(Full)

Reserved

A9

1

0

1

0

1

0

Burst

1

0

1

0

1

Reserved

(Note 1)

Special Mode Register Programmed with SMRS

Address

A10

A9

A8

A7

A6

LC

A5

A4

A3

A2

A1

A0

Function

X

LM

X

Load Color

Load Mask

A6

Function

Disable

Enable

A5

Function

Disable

Enable

0

1

0

1

(Note 2)

POWER UP SEQUENCE

SGRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.

Note : 1. The full column burst(256bit) is available only at Sequential mode of burst type.

2. If LC and LM both high(1), data of mask and color register will be unknown.

Rev. 0.0 (Jul. 1999)

- 12

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

BURST SEQUENCE (BURST LENGTH = 4)

Initial address

Sequential

Interleave

A1

0

A0

0

1

2

3

1

2

3

0

2

3

0

1

3

0

1

2

0

1

2

3

1

0

3

2

3

0

1

3

2

1

0

1

0

1

BURST SEQUENCE (BURST LENGTH = 8)

Initial address

Sequential

Interleave

A2

0

A1

0

A0

0

1

2

3

4

5

6

7

1

2

3

4

5

6

7

0

2

3

4

5

6

7

0

1

3

4

5

6

7

0

1

2

4

5

6

7

0

1

2

3

5

6

7

0

1

2

3

4

5

7

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

1

2

3

0

1

6

7

4

5

3

2

1

0

7

6

5

4

5

6

7

0

1

2

3

5

4

7

6

1

0

3

2

6

7

4

5

2

3

0

1

7

6

5

4

3

2

1

0

1

6

7

0

1

2

3

4

0

3

2

5

4

7

6

0

1

0

1

0

1

0

1

0

1

PIXEL to DQ MAPPING(at BLOCK WRITE)

Column address

7 Byte

6 Byte

5 Byte

4 Byte

3 Byte

2 Byte

1 Byte

0 Byte

I/O7 - I/O0

DQ0

A2

0

A1

0

A0

0

I/O63 - I/O56 I/O55 - I/O48 I/O47 - I/O40 I/O39 - I/O32 I/O31 - I/O24 I/O23 - I/O16 I/O15 - I/O8

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ8

DQ9

0

1

DQ1

0

1

0

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ2

0

1

DQ3

1

0

DQ4

1

0

1

DQ5

1

0

DQ6

1

DQ7

Rev. 0.0 (Jul. 1999)

- 13

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

PACKAGE DIMENSIONS - Proposal (Based on JEDEC STD.)

Units : Inches (millimeters)

2.66

(67.60)

2.50

2-R 0.078 Min

(2.00 Min)

(63.60)

0.16 ± 0.039

(4.00 ± 0.10)

0.75

(19.20)

1.44

(36.80)

0.13

(3.30)

2- f 0.07

(1.80)

0.18

(4.60)

0.083

(2.10)

0.10

(2.50)

Z

Y

1.15

(3.70)

0.177 Max

(4.5 Max)

0.024 ± 0.001

(0.60 ± 0.05)

* Note 1

0.16 ± 0.0039

(4.00 ± 0.10)

0.01 Max

(0.25 Max)

0.06 ± 0.0039

(1.50 ± 0.1)

0.03 TYP

(0.80 TYP)

0.04 ± 0.0039

(1.00 ± 0.10)

Detail Z

Detail Y

Tolerances :±.0059(.15) unless otherwise specified

* Note 1 : This thickness is when using PQFP package. When using TQFP package, this value is 2.5mmMax.

The used device is 512Kx32, 16M SGRAM, 100pin (T)QFP

SGRAM Component Part No. : KM4132G512Q : PQFP (Height = 3.0mmMax)

KM4132G512TQ : TQFP (Height = 1.2mmMax)

Rev. 0.0 (Jul. 1999)

- 14

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

SERIAL PRESENCE DETECT INFORMATION

2

• Serial PD Interface Protocol : I C

• Current sink capability of SDA driver £ 3mA

• Maximum clock frequency : 80KHz

Contents ;

Function Supported

-6 -7

128bytes

Hex value

Byte #

Function Described

Note

-5

-8

-5

-6

-7

-8

0

1

# of bytes written into serial memory at module manufacturer

Total # of bytes of SPD memory device

Fundamental memory type

80h

08h

06h

0Ah

08h

01h

40h

00h

01h

256bytes (2K bit)

2

SGRAM

10

TBD

3

# of row address on this assembly

1

4

# of column address on this assembly

# of module banks on this assembly

Data width of this assembly

8

5

1 bank

64 bits

-

6

7

...... Data width of this assembly

8

Voltage interface standard of this assembly

SGRAM cycle time from clock @CAS latency of 3

SGRAM access time from clock @CAS latency of 3

DIMM configuraion type

LVTTL

9

5n

6ns

7ns

6ns

8ns

50h

45h

60h

55h

70h

60h

80h

65h

2

10

11

12

13

14

15

16

17

18

19

20

4.5n

5.5ns

6.5ns

Non parity

00h

80h

20h

00h

01h

8Fh

02h

06h

01h

Refresh rate & type

15.625us, support self refresh

Primary SGRAM width

x32

None

Error checking SGRAM width

Minimum clock delay for back-to-back random column

SGRAM device attributes : Burst lengths supported

SGRAM device attributes : # of banks on SGRAM device

SGRAM device attributes : CAS latency

SGRAM device attributes : CS latency

SGRAM device attributes : Write latency

tCCD = 1CLK

1, 2, 4, 8 & full page

2 banks

2 & 3

0 CLK

Non-buffered, non-registered

& redundant addressing

21

SGRAM module attributes

00h

+/- 10% voltage tolerance,

Burst Read Single bit Write

precharge all, auto precharge

22

SGRAM device attributes : General

4Eh

23

24

25

26

27

28

29

30

31

32

33

34

SGRAM cycle time @CAS latency of 2

SGRAM access time @CAS latency of 2

SGRAM cycle time @CAS latency of 1

SGRAM access time @CAS latency of 1

Minimum row precharge time (=tRP)

-

10ns

6ns

-

00h

14h

0Ah

14h

28h

00h

12h

0Ch

12h

2Ah

00h

15h

0Eh

15h

31h

A0h

60h

00h

14h

10h

14h

30h

2

-

20ns

10ns

20ns

40ns

18ns

12ns

18ns

42ns

21ns

14ns

21ns

49ns

20ns

16ns

20ns

48ns

Minimum row active to row active delay (tRRD)

Minimum RAS to CAS delay (=tRCD)

Minimum activate to precharge time (=tRAS)

Module bank density

1 bank of 4MB

01h

Address and Command signal Input setup time (=tSS)

Address and Command signal Input hold time (=tSH)

Data signal Input setup time (=tSS)

1.5ns

1ns

1.5ns

1ns

1.8ns

1ns

2ns

1ns

2ns

15h

10h

15h

10h

15h

18h

10h

18h

20h

10h

20h

2

1.5ns

1.8ns

Rev. 0.0 (Jul. 1999)

- 15

SGRAM MODULE

KMM965G511AQ(P)N / KMM966G511AQ(P)N

Function Supported

Hex value

Byte #

Function Described

Note

-5

-6

-7

-8

-5

-6

-7

-8

35

36

Data signal Input hold time (=tSH)

Block Write Size

1ns

10h

2

8 Columns

03h

37~61 Superset information (maybe used in future)

-

00h

62

63

64

SPD data revision code

Initial Release

TBD

Checksum for bytes 0 ~ 62

Manufacturer JEDEC ID code

-

A7h

C7h

F7h

1Bh

Samsung

CEh

00h

01h

4Bh

4Dh

39h

20h

36h

47h

20h

35h

31h

41h

65~71 ...... Manufacturer JEDEC ID code

Samsung

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Manufacturing location

Onyang Korea

Manufacturer part # (Samsung memory)

Manufacturer part # (Memory module)

Manufacturer part # (Memory type & edge connector)

Manufacturer part # (Data bits)

K

M

9

Blank

...... Manufacturer part # (Data bits)

Manufacturer part # (Mode & operating voltage)

Manufacturer part #

6

G

Blank

...... Manufacturer part #

5

Manufacturer part #

1

Manufacturer part #

1

Manufacturer part # (Component revision)

Manufacturer part # (Package type)

Manufacturer part # (PCB revision)

Manufacturer part # (Hyphen)

A(1st Rev.)

Q(PQFP) / P(TQFP)

51h / 50h

4Eh

N

" - "

G

2Dh

Manufacturer part # (Power)

47h

Manufacturer part # (Minimum cycle time)

Manufacturer revision code (For PCB)

...... Manufacturer revision code (For component)

Manufacturing date (Week)

5

6

7

8

35h

36h

4Eh

37h

38h

N

A(1st Rev.)

41h

-

3

4

Manufacturing date (Year)

-

95~98 Assembly serial #

-

99~12 Manufacturer specific data (may be used in future)

FFh

126

127

Reserved

128+ Unused storage locations

Note :

1. The bank select address is excluded in counting the total # of addresses.

2. This value is based on the component specification.

3. These bytes are programmed by code of Date Week & Date Year with BCD format.

4. These bytes are programmed by Samsung¢s own Assembly Serial # system. All modules may have different unique serial #.

Rev. 0.0 (Jul. 1999)

- 16


型号：	KMM965G511APN-G7
厂家：	SAMSUNG
描述：	Synchronous Graphics RAM Module, 512KX64, 5.5ns, CMOS, SODIMM-144 时钟动态存储器内存集成电路
文件：	总16页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KMM965G511APN-G7 [SAMSUNG]

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