KS0032 [SAMSUNG]

Dot Matrix LCD Driver, 16 X 80 Dots, CMOS;


型号：	KS0032
厂家：	SAMSUNG
描述：	Dot Matrix LCD Driver, 16 X 80 Dots, CMOS 时钟驱动 CD 外围集成电路
文件：	总39页 (文件大小：334K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KS0032

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

June. 1999.

Ver. 0.5

Prepared by:

Tae-Kwang, Park

parktk@samsung.co.kr

Contents in this document are subject to change without notice. No part of this document may be reproduced

or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express

written permission of LCD Driver IC Team.

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

KS0032 Specification Revision History

Content

Version

0.0

Date

Original

Feb.1999

ECKON pad added

POR circuit added

0.1

Mar.1999

Page 5: (4/5) x V0 ® (3/5) x V0

(3/5) x V0 ® (2/5) x V0

Page 6: E_RD signal description is changed

E_RD: Active low signal for writing command in 6800 mode or high enable

signal for reading command in 8080 mode. ®

0.2

Apr.1999

E_RD: Active low signal for writing command or high enable signal for reading

command in 6800 mode, low enable signal for reading command in

8080 mode.

Page 6: LCD DRIVER OUTPUT added

Page 18: Power ON / OFF timing added

Page 29: I_DD1(VDD = 2.4~3.6V): 150mA ® 50mA

Page 30: I_DD1(VDD = 3.6~5.5V): 250mA ® 80mA

0.3

May.1999

0.4

0.5

Page 1, 2, 11: CGROM character size is changed from 256 to 254.

Jun.1999

Page 6: RW_WR active low -> active high

Page 6: RW_WR active low -> low enable

Page 20: Wait for more than 1.2us or Busy Check -> delete “or Busy Check”

Page 21: Wait for more than 1.2us or Busy Check -> delete “or Busy Check”

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

CONTENTS

INTRODUCTION ......................................................................................................................................... 1

FEATURES ................................................................................................................................................. 1

BLOCK DIAGRAM ...................................................................................................................................... 2

PAD CONFIGURATION .............................................................................................................................. 3

PAD CENTER COORDINATES................................................................................................................... 4

PIN DESCRIPTION ..................................................................................................................................... 5

POWER SUPPLY................................................................................................................................. 5

SYSTEM CONTROL ............................................................................................................................ 5

MPU INTERFACE ................................................................................................................................ 6

LCD DRIVER OUTPUT ........................................................................................................................ 6

TEST.................................................................................................................................................... 6

FUNCTIONAL DESCRIPTION..................................................................................................................... 7

MICROPROCESSOR INTERFACE ...................................................................................................... 7

ADDRESS COUNTER (AC).................................................................................................................10

DISPLAY DATA RAM (DDRAM)..........................................................................................................10

CHARACTER GENERATOR ROM (CGROM) .....................................................................................11

CHARACTER GENERATOR RAM (CGRAM)......................................................................................12

LCD DRIVER CIRCUIT .......................................................................................................................13

INSTRUCTION DESCRIPTION...................................................................................................................14

INITIALIZING..............................................................................................................................................18

HARDWARE RESET...........................................................................................................................18

INSTRUCTION INITIALIZING WITH RESET .......................................................................................20

LCD DRIVING POWER SUPPLY CIRCUIT ................................................................................................22

MPU INTERFACE ......................................................................................................................................23

INTERFACING WITH 8080-SERIES MICROPROCESSORS...............................................................23

INTERFACING WITH 6800-SERIES MICROPROCESSORS...............................................................23

APPLICATION INFORMATION FOR LCD PANEL.....................................................................................24

FRAME FREQUENCY................................................................................................................................28

MAXIMUM ABSOLUTE RATE....................................................................................................................29

ELECTRICAL CHARACTERISTICS...........................................................................................................30

DC CHARACTERISTICS.....................................................................................................................30

AC CHARACTERISTICS.....................................................................................................................32

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

INTRODUCTION

This character driver and controller LSI for liquid crystal dot matrix display systems can display 2-line of 16

characters with the 5 x 8 dots format. It is capable of interfacing various microprocessors, supporting the 4-bit or

8-bit parallel mode. Voltage follower and bias circuit is built in the IC.

FEATURES

Driver Output Circuits

16 common outputs / 80 segment outputs

Applicable Duty Ratio

Font size

Display size

Duty

Contents of outputs

5 x 8

2-line x 16 characters

1/16

2 x 16 characters

On-chip Display Data RAM

Character Generator ROM (CGROM): 10,160 bits (254 characters x 5 x 8 dots)

Character Generator RAM (CGRAM): 80 bits (2 characters x 5 x 8 dots)

Display Data RAM (DDRAM): 256 bits (16 characters x 2-line)

Microprocessor Interface

8-bit parallel interface with 6800-series or 8080-series MPU

4-bit parallel interface with 6800-series or 8080-series MPU

Function Set

Simple instruction set

COM / SEG bi-directional (4 types of LCD application available)

Hardware reset (RESETB)

On-chip Analog Circuit

Internal RC oscillator circuit

Voltage follower & bias circuit

Automatic power on reset circuit

Operating Voltage Range

Supply voltage (VDD): 2.4 to 5.5V

LCD driving voltage (VLCD = V0 - VSS): 6.0V Max.

Low Power Consumption

Package Type

Gold bumped chip

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

BLOCK DIAGRAM

ECKON

DIRC

Power On

Reset (POR)

Oscillator

Timing Generator

RESETB

Instruction

(IR)

Instruction

Decoder

Input Buffer

COM1 to

COM16

16 bits

Shift

Common

Driver

CSB

Parallel

Address

Counter

Interface

RW_WR

4-/8-bit

E_RD

Display

Data RAM

(DDRAM)

256 bits

(6800/8080

-series)

Data

(DR)

DB7 to

DB4

Data Output

(OR)

SEG1 to

SEG80

80 bits

Shift

80 bits

Latch

Circuit

Segment

Driver

DB3 to

DB0

Busy

Flag

Character

Generator

RAM

Character

Generator

ROM

Cursor

and

LCD Driving

Voltage Selector

Blink

Controller

(CGRAM)

80 bits

(CGROM)

10,160 bits

Voltage Follower

& Bias Resistor

GND

Segment Data Conversion

DIRS

V0 V1 V2 V3 V4

Figure 1. Block Diagram

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

PAD CONFIGURATION

130

136

137

(0,0)

144

PAD

DUMMY_PAD

Figure 2. KS0032 Chip Configuration

Table 1. KS0032 Pad Dimensions

Size

Item

Pad No.

Unit

Chip size

Pad pitch

5430

1410

1 to 44

45 to 144

1 to 44

45 to 59

60 to 129

130 to 144

Bumped pad size

Bumped pad

height

1 to 144

17 (Typ.)

COG Align Key Coordinate

30 m 30 m 30 m

m m m

(-2600, +605)

(+2600, +590)

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: mm]

No.

Name

No.

Name

No.

Name

DUMMY

VSS

ECKON

VDD

-1935

-595

100

COM7

2605

-135

-65

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

SEG47

SEG48

SEG49

SEG50

SEG51

SEG52

SEG53

SEG54

SEG55

SEG56

SEG57

SEG58

SEG59

SEG60

SEG61

SEG62

SEG63

SEG64

SEG65

SEG66

SEG67

SEG68

SEG69

SEG70

SEG71

SEG72

SEG73

SEG74

DUMMY

SEG75

SEG76

SEG77

SEG78

SEG79

SEG80

COM16

COM15

COM14

COM13

COM12

COM11

COM10

COM9

-455

595

425

355

285

215

145

-1845

-1755

-1665

-1575

-1485

-1395

-1305

-1215

-1125

-1035

-945

-855

-765

-675

-585

-495

-405

-315

-225

-135

-45

-595

-555

-485

-415

-345

-275

-205

COM8

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

DUMMY

SEG7

2605

2415

2345

2275

2205

2135

2065

1995

1925

1855

1785

1715

1645

1575

1505

1435

1365

1295

1225

1155

1085

1015

945

-525

-595

-665

-735

-805

-875

-945

145

215

285

355

425

595

VDD

-1015

-1085

-1155

-1225

-1295

-1365

-1435

-1505

-1575

-1645

-1715

-1785

-1855

-1925

-1995

-2065

-2135

-2205

-2275

-2345

-2415

-2605

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

SEG45

SEG46

VDD

RESETB

RW_WR

VSS

E_RD

VDD

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

CSB

VSS

VDD

TEST

VSS

DIRC

VDD

DIRS

VSS

DUMMY

COM1

COM2

COM3

COM4

COM5

COM6

135

225

315

405

495

585

675

765

855

945

875

805

735

665

595

525

455

385

315

245

175

105

-35

1035

1125

1215

1305

1395

1485

1575

1665

1755

1845

1935

2605

-65

-135

-205

-275

-345

-415

-485

-555

-105

-175

-245

-315

-385

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

PIN DESCRIPTION

POWER SUPPLY

Table 3. Pin Description

Description

Name

VDD

VSS

I/O

Supply Power supply

Supply Ground

Bias voltage Input for LCD driving

LCD driving voltage outputs.

Voltages should have the following relationship;

V0 ³ V1 ³ V2 ³ V3 ³ V4 ³ VSS

These voltages are generated as following table.

LCD bias

(1/5) x V0

1/5 bias

(4/5) x V0

(3/5) x V0

(2/5) x V0

SYSTEM CONTROL

Table 3. Pin Description (Continued)

Description

Name

I/O

Clock source selection input

ECKON

When ECKON = "High", External clock by CK pin is used as system clock, and internal

oscillator circuit is turned OFF. When ECKON = "Low", internal oscillator is used.

External clock input (When ECKON = "High")

It must be fixed "High" or "Low" when the internal oscillation circuit is used (When

ECKON = "Low").

MPU interface selection input

MI = "Low", 8080-series MPU

MI = "High", 6800-series MPU

COM direction selection input

When DIRC = "Low",

DIRC

DIRS

COM1 ® COM2 - - - - ® COM15 ® COM16

When DIRC = "High",

COM16 ® COM15 - - - - ® COM2 ® COM1

SEG direction selection input

When DIRS = "Low",

SEG1 ® SEG2 - - - - ® SEG79 ® SEG80

When DIRS = "High",

SEG80 ® SEG79 - - - - ® SEG2 ® SEG1

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

MPU INTERFACE

Table 3. Pin Description (Continued)

Description

Name

I/O

Reset input

RESETB

Initialization is performed by "Low" level sensing of the RESETB signal.

Chip selection input

KS0032 is selected while CSB is "Low".

CSB

When RS = "Low", instruction register

When RS = "High", data register

In 8080-series MPU interface mode, this pin is connected to WR pin of MPU and is an

active high write signal.

RW_WR

E_RD

In 6800-series MPU interface mode, this pin is connected to R/W pin of MPU.

When RW_WR = "High", read mode

When RW_WR = "Low", write mode

In 8080-series MPU interface mode, this pin is connected to RD pin of MPU and is a

low enable read signal.

In 6800-series MPU interface mode, this pin is connected to E pin of MPU and enables

read or write command according to RW_WR signal.

When 8-bit interface mode, used as bi-directional data bus DB0 to DB7

During 4-bit bus mode, only DB4 to DB7 are used. In this case DB0 - DB3 pins are

don’t care (connect to "High", "Low" or open).

DB0 to DB3

DB4 to DB7

I/O

LCD DRIVER OUTPUT

Table 3. Pin Description (Continued)

Description

Name

I/O

COM1 to

COM16

Common signal output for character display

Segment signal output for character display

SEG1 to

SEG80

TEST

Table 3. Pin Description (Continued)

Description

Name

I/O

Test pin

TEST

This pin is not used for normal operation and should be connect to "Low".

*NOTE: DUMMY – These pins should be opened (floated).

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

KS0032 has two kinds of interface type with MPU: 4-bit bus or 8-bit bus. 4-bit bus and 8-bit bus is selected by the

DL bit in the instruction register, and 6800-series MPU or 8080-series MPU is selected by MI pin.

Table 4. Various Kinds of MPU Interface according to MI and DL Bit

CSB

E_RD

DB0 to DB3

DB4 to DB7

RW_WR

R/W

8-bit (H)

4-bit (L)

8-bit (H)

4-bit (L)

DB0 to DB3

6800

series (H)

DB0 to DB3

8080

series (L)

NOTE: "-" - Don’t care ("High", "Low" or Open)

(H): fixed "High" (VDD)

(L): fixed "Low" (VSS)

MI: "High" = 6800-series MPU, "Low" = 8080-series MPU

DL: "High" = 8-bit mode, "Low" = 4-bit mode

CSB: "High" = chip is not selected, "Low" = chip is selected

RS: "High" = data register, "Low" = instruction register

RW_WR: read / write indicating signal in 6800 mode, active high signal for writing command in 8080 mode.

E_RD: Active low signal for writing command or high enable signal for reading command in 6800 mode,

low enable signal for reading command in 8080 mode.

Parallel Interface

During writing operation, two 8-bit registers, data register (DR) and instruction register (IR), are used. The data

selected by RAM address set instruction. The Instruction register (IR) is used only to store instruction code

transferred from MPU. To select DR or IR register, RS input pin is used.

During reading operation, 8-bit output data register (OR) is used. The output data register (OR) is used as

temporary data storage place for being read from DDRAM / CGRAM. Destination RAM is selected by RAM

address set instruction. After RAM address set, the first reading in the 8-bit bus mode (first and second reading in

the 4-bit bus mode) is a dummy cycle (figure 3, 4, 5, 6). The valid data comes from the second reading in the 8-bit

bus mode (from the 3rd reading in 4-bit bus mode). The dummy cycle makes the address counter (AC) indicate

the correct address. So it is recommended to set address before writing. The instruction read operation is

supported for indicating internal operation is being processed (Busy Flag).

In the 4-bit bus mode, it is needed to transfer 4-bit data (through DB4 to DB7) by two times. The high order bits

(for 8-bit mode DB4 to DB7) are transferred before the low order bits (for 8-bit mode DB0 to DB3) in read and

write transaction. The DB0 to DB3 pins are floated in this 4-bit bus mode.

After RESETB operation, KS0032 considers the first 4-bit data from MPU as the high order bits in the 4-bit bus

mode.

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

CSB

RW_WR

E_RD

DB7 to DB0

Valid

Data

Instruction

W rite

Busy Flag

Read

Dummy

Valid

Data

W rite

Data Read Data Read

Figure 3. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (6800-series MPU Mode)

CSB

RW_WR

E_RD

Valid

Data

DB7 to DB0

Instruction

W rite

Busy Flag

Read

Dummy

Valid

Data

W rite

Data Read Data Read

Figure 4. Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (8080-series MPU Mode)

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

CSB

RW_WR

E_RD

Upper

4-bit

Lower

4-bit

A3 -

D7 -

D3 -

D7 -

D3 -

DB7 to DB0

Instruction W rite

Busy Flag &

Address Read

Dummy

Data Read

Valid

Data Read

Data W rite

Figure 5. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (6800-series MPU Mode)

CSB

RW_WR

E_RD

Upper

4-bit

Lower

4-bit

A3 -

D7 -

D3 -

D7 -

D3 -

DB7 to DB0

Instruction W rite

Busy Flag &

Address Read

Dummy

Data Read

Valid

Data Read

Data W rite

Figure 6. Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (8080-series MPU Mode)

Busy Flag

When DB7 is "High" in read status operation, it indicates that the internal operation is in busy status and can

accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag

before each instruction, except display clear instruction.

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

ADDRESS COUNTER (AC)

Address Counter (AC) in KS0032 stores DDRAM / CGRAM address. After writing into or reading from DDRAM /

CGRAM, AC is automatically increased or decreased by 1 according to the entry mode.

DISPLAY DATA RAM (DDRAM)

DDRAM stores display data of maximum 32 x 8 bits (32 characters). DDRAM address is set in the address

counter (AC) as a hexadecimal number.

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

(a) Display shift is not performed

01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 00

41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 40

(b) Display shift left is performed

0F 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E

4F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E

Figure 7. DDRAM Address

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

CHARACTER GENERATOR ROM (CGROM)

CGROM has 5 x 8-dot 254 characters. The CGROM character code 00h and 01h are CGRAM character data

area.

Table 5. CGROM Character Code (00)

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

CHARACTER GENERATOR RAM (CGRAM)

CGRAM has up to 5 x 8-dot 2 characters. By writing font data to CGRAM, user defined character can be used.

Table 6. Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)

Character code

CGRAM address

CGRAM data

Pattern

number

(DDRAM data)

D7 D6 D5 D4 D3 D2 D1 D0

A3 A2 A1 A0

P7 P6 P5 P4 P3 P2 P1 P0

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

- - - 0 1 0 1 0

- - - 1 0 1 0 1

- - - 0 1 0 1 0

- - - 1 0 1 0 1

- - - 0 1 0 1 0

- - - 1 0 1 0 1

- - - 0 1 0 1 0

- - - 1 0 1 0 1

0 0 0 0 0 0 0 0

(00h)

Pattern 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

- - - 0 0 0 0 0

- - - 1 1 1 1 1

- - - 0 0 0 0 0

- - - 1 1 1 1 1

- - - 0 0 0 0 0

- - - 1 1 1 1 1

- - - 0 0 0 0 0

- - - 1 1 1 1 1

0 0 0 0 0 0 0 1

(01h)

Pattern 2

NOTE: "-" - Don’t care

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

LCD DRIVER CIRCUIT

LCD Driver circuit has 16 common and 80 segment signals for driving LCD. Data from CGRAM / CGROM are

transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. COM1 to COM16 have

1/16 duty ratio. SEG bi-directional function is selected by DIRS input, and COM shift direction is selected by DIRC

input.

Table 7. SEG Data Shift Direction

DIRS pin

Low

SEG data shift direction

SEG1 ® SEG2 ® SEG3 ® - - - - - - - ® SEG78 ® SEG79 ® SEG80

SEG80 ® SEG79 ® SEG78 ® - - - - - - - ® SEG3 ® SEG2 ® SEG1

High

Table 8. COM Data Shift Direction

DIRC pin

Low

COM data shift direction

COM1 ® COM2 ® COM3 ® - - - - - - - - ® COM14 ® COM15 ® COM16

COM16 ® COM15 ® COM14 ® - - - - - - - - ® COM3 ® COM2 ® COM1

High

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

INSTRUCTION DESCRIPTION

Table 9. Instruction Table

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Instruction

RS R/W

Description

Write "20H" to DDRAM and set DDRAM

address to "00H" from AC

*Clear display

DDRAM address is set to 00h from AC

and the cursor returns to 00h position.

The contents of DDRAM are not changed.

Return home

Assign cursor moving direction and

enable the shift of entire display

Entry mode set

I/D SH

Display ON / OFF

control

Set display (D), cursor (C), and blinking of

cursor (B) ON / OFF control

Set cursor moving and display shift

control bit, and the direction, without

changing of DDRAM data

Cursor or display

shift

S/C R/L

Set interface data length (DL: 4-bit / 8-bit)

instruction

Function set

CGRAM

address set

A3 A2 A1 A0 Set CGRAM address in address counter.

DDRAM

address set

A6 A5 A4 A3 A2 A1 A0 Set DDRAM address in address counter.

Whether in internal operation or not can

Read busy flag

and address

be known by reading BF, The contents of

address counter can also be read

BF A6 A5 A4 A3 A2 A1 A0

Write data

Read data

D7 D6 D5 D4 D3 D2 D1 D0 Write data into DDRAM / CGRAM

D7 D6 D5 D4 D3 D2 D1 D0 Read data from DDRAM / CGRAM

("-": Don’t care)

NOTES:

1. Instruction execution time depends on the internal process time of KS0032, therefore it is necessary to provide a time larger

than one MPU interface cycle time (tc) between execution of two successive instructions.

2. "Clear Display" instruction has 850ms execution time (when fosc = 40.0kHz), so check the Busy flag or wait for more than

850ms after using "Clear Display" instruction.

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

Clear Display

PRELIMINARY SPEC. VER. 0.5

KS0032

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Clear all the display data by writing "20H" (space code of CGROM) to all the DDRAM address, and set the

DDRAM address to "00H" into AC (address counter). For this instruction, the CGROM address "20H" have to set

space code. If the display position has shifted then it returns to the original positions. Namely, when display data

is shifted and cursor or blinking is displayed, bring the cursor to the left edge on first line of the display. It makes

entry mode to increment (I/D = "High").

Return Home

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Return Home instruction field makes cursor return home. DDRAM address is set to 00h from AC and the cursor

returns to 00h position. The contents of DDRAM are not changed.

Entry Mode Set

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

I/D

Set the moving direction of cursor and display after data writing or reading instruction.

I/D: Increment / decrement of DDRAM / CGRAM address (cursor or blink)

After DDRAM / CGRAM data write/read operation, DDRAM/CGRAM address is increased (I/D = "High") or

decreased (I/D = "Low") by 1. So in case of DDRAM data transfer operation and cursor or blink is turned on,

cursor or blink moves to right (I/D = "High") or left (I/D = "Low"), but in CGRAM data transfer operation, cursor or

blink does not move.

SH: Shift of entire display

When DDRAM read (CGRAM read/write) operation or SH = "Low", entire display is not shift. Only when SH =

"High" and DDRAM write operation, entire display is shift according to I/D value (I/D = "1": shift left, I/D = "0": shift

right).

Display ON / OFF Control

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Control display / cursor/blink ON / OFF 1 bit register

D: Display ON / OFF Control Bit

When D = "High", entire display is turned ON.

When D = "Low", entire display is turned OFF, but display data is remained in DDRAM.

C: Cursor ON / OFF Control Bit

When C = "High", cursor is turned ON.

When C = "Low", cursor is disappeared in current display, but I/D register remains its data.

B: Cursor Blink ON / OFF Control Bit

When B = "High", cursor blink is ON, that performs alternate between all high data (black pattern) and display

character at the cursor position.

When B = "Low", blink is OFF.

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

Cursor or Display Shift

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

S/C

R/L

Without writing or reading of display data, shift right / left the cursor position or display. This instruction is used to

correct or search display data (refer to table 10). Note that display shift is performed simultaneously in all the line.

When displayed data is shifted repeatedly, each line shifted individually. When display shift is performed, the

contents of address counter are not changed.

Table 10. Shift Patterns According to S/C and R/L Bits

S/C

R/L

Operation

Shift cursor to the left, AC is decreased by 1

Shift cursor to the right, AC is increased by 1

Shift all the display to the left, cursor moves according to the display

Shift all the display to the right, cursor moves according to the display

Function Set

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DL: Interface Data Length Control Bit

When DL = "High", it means 8-bit bus mode with MPU.

When DL = "Low", it means 4-bit bus mode with MPU.

When 4-bit bus mode, it needs to transfer 4-bit data by two times.

CGRAM Address Set

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Set CGRAM address to AC. This instruction makes CGRAM data available from MPU for user defined character

pattern. CGRAM address is from 00h to 0Fh.

DDRAM Address Set

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Set DDRAM address to AC. Before writing / reading data into / from the RAM, set the address by RAM Address

Set instruction. Next, when data are written / read in succession, the address is automatically increased by 1

(when I/D = "High") or decreased by 1 (when I/D = "Low"). The address ranges are 00h to 0Fh (1st line) and 40h

to 4Fh (2nd line).

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

Read Busy Flag and Address

PRELIMINARY SPEC. VER. 0.5

KS0032

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

This instruction shows whether KS0032 is in internal operation or not. If the resultant BF is "High", it means the

internal operation is in progress and you have to wait until BF to be "Low", and then the next instruction can be

performed. In this instruction you can read also the value of address counter.

Write Data

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Write binary 8- / 5- bit data to DDRAM / CGRAM. The selection of RAM from DDRAM / CGRAM is set by the

previous address set instruction (DDRAM address set, CGRAM address set). After write operation, the address is

automatically increased / decreased by 1, according to the entry mode.

Read Data

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Read binary 8- / 5- bit data from DDRAM / CGRAM. The selection of RAM is set by the previous address set

instruction. If address set instruction of RAM is not performed before this instruction, the data that read first is

invalid, because the direction of AC is not determined. If you read RAM data several times without RAM address

set instruction before read operation, you can get correct RAM data from the second, and the first data would be

incorrect, because there is no time margin to transfer RAM data. In case of DDRAM read operation, cursor shift

instruction plays the same role as DDRAM address set instruction: it also transfers RAM data to output data

mode. After CGRAM read operation, display shift may not be executed correctly.

* In case of RAM write operation, after this operation, AC is increased/decreased by 1 like read operation. In this

time, AC indicates the next address position, but you can read only the previous data by read instruction. RAM

address is dummy data, so the correct RAM data come from the second read transaction. After reading operation,

the address is increased by 1 automatically.

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

INITIALIZING

HARDWARE RESET

When the power is turned on, KS0032 is initialized automatically by the power on reset circuit (refer to figure 8).

In case of RESETB pin becomes "Low" and durable the state for more than 1.2ms (VDD = 3V), KS0032 can be

initialized too. During the initialization, the following instructions are executed, and BF (Busy Flag) is kept "High"

(busy state) to the end of initialization.

Display Clear

All the DDRAM data is set to "20H"

Return Home

Address counter = "00H"

Entry Mode Set Instruction

I/D = 1: Address counter is set to increment mode.

SH = 0: Entire display shift is disabled.

Display ON / OFF Control Instruction

C = 0: cursor OFF

B = 0: blink OFF

D = 0: display OFF

Function Set Instruction

DL = 1: 8-bit interface mode

CGRAM / DDRAM Address

RAM address counter is set to "00H".

t_RDD

t_OFF

0.9V

0.1V

Rising Time

1 ms

t_RDD

t_OFF

Power OFF Time

Note: If the upper power conditions are not satisfied in power ON / OFF sequence, the

internal Power On Reset (POR) circuit will not operates normally.

Figure 8. Power ON / OFF Timing

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

t_R

t_RW

RESETB

Internal Reset Time

Reset Pulse Width

t_RW

1.2 s

Reset Time

t_R

850 s

Note: t

indicates the minimum RESETB duration for activate internal reset signal

indicates reset completion time of internal circuit from the start of the internal

reset signal (when fosc = 40.0kHz).

Figure 9. RESET Timing

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

INSTRUCTION INITIALIZING WITH RESET

8-bit Interface Mode (fosc = 40.0kHz)

VDD-VSS Power ON

When Using RESETB

input for Initializing

When just Using Internal

Power On Reset Circuit

Wait until Power is Stable

Set Reset (RESETB Pin = "Low")

Wait for more than 20ms

after VDD rises to 0.9 VDD

Wait for more than 1.2 s

Release Reset (RESETB Pin = "High")

Wait for more than 1ms

Command Input

Function Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

(1)

Entry Mode Set

I/D SH

Display ON / OFF Control

End of Initialization

RAM Address Set

RAM Data Write

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

4-bit Interface Mode (fosc = 40.0kHz)

VDD-VSS Power ON

When Using RESETB

Input for Initializing

When just Using Internal

Power On Reset Circuit

Wait until Power is Stable

Set Reset (RESETB Pin = "Low")

Wait for more than 20ms

after VDD rises to 0.9 VDD

Wait for more than 1.2 s

Release Reset (RESETB Pin = "High")

Wait for more than 1ms

Command Input

Function Set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

(0)

Entry Mode Set

I/D SH

Display ON / OFF Control

End of Initialization

RAM Address Set

RAM Data Write

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

LCD DRIVING POWER SUPPLY CIRCUIT

The Power Supply circuit produces LCD panel driving voltage at low power consumption. The LCD driving Power

Supply circuit consists of external voltage input and voltage follower.

VDD

KS0032

External

Power

Supply

VSS

GND

* Recommended Capacitance value is 0.1 to 4.7mF

Figure 10. LCD Driving Power Connection

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

MPU INTERFACE

INTERFACING WITH 8080-SERIES MICROPROCESSORS

VCC

VDD

VCC

A1 - A7

IORQ

CSB

DECODER

GND

MPU

KS0032

(8080-series) RD

E_RD

RW_WR

D0 - D7

DB0 - DB7

RESET

GND

RESETB

VSS

RESETB

GND

Figure 11. Interfacing with 8080-series MPU

INTERFACING WITH 6800-SERIES MICROPROCESSORS

VCC

VDD

A1 - A7

VMA

CSB

DECODER

MPU

(6800 -series)

KS0032

E_RD

R/W

RW_WR

D0 - D7

DB0 - DB7

RESET

RESETB

GND

VSS

RESETB

GND

Figure 12. Interfacing with 6800-series MPU

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

APPLICATION INFORMATION FOR LCD PANEL

Chip Bottom & Lower View (DIRC = "0", DIRS = "0")

COM8

COM7

COM6

···

COM2

COM1

COM16

COM15

···

COM11

COM10

COM9

BOTTOM VIEW

Figure 13. Chip Bottom & Lower View Interfacing with LCD Panel

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

Chip Bottom & Upper View (DIRC = "1", DIRS = "1")

PRELIMINARY SPEC. VER. 0.5

KS0032

COM9

COM1

COM2

···

COM6

COM7

COM8

BOTTOM VIEW

COM10

COM11

···

COM15

COM16

Figure 14. Chip Bottom & Upper View Interfacing with LCD Panel

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

Chip Top & Lower View (DIRC = "0", DIRS = "1")

COM16

COM15

···

COM11

COM10

COM9

COM8

COM7

COM6

···

COM2

COM1

TOP VIEW

Figure 15. Chip Top & Lower View Interfacing with LCD Panel

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

Chip Top & Upper View (DIRC = "1", DIRS = "0")

PRELIMINARY SPEC. VER. 0.5

KS0032

COM1

COM2

···

COM6

COM7

COM8

COM9

COM10

COM11

···

COM15

COM16

TOP VIEW

Figure 16. Chip Top & Upper View Interfacing with LCD Panel

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

FRAME FREQUENCY

1-line Selection Period

- - - -

15 16 1 2

1 2

15 16 1 2

15 16

COM1

1 FRAME

1-line Selection Period = 16 Clock Pulses x 2 Division

One Frame

= 32 x 16 x 25.0 s = 12.8ms (1 Clock = 25.0 s at fosc = 40.0kHz)

Frame Frequency

= 1 / 12.8ms = 78Hz

Figure 17. Frame Frequency

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

MAXIMUM ABSOLUTE RATE

Table 11. Maximum Absolute Rate

Characteristics

Power supply voltage (1)

Power supply voltage (2)

Input voltage

Symbol

VDD

Value

-0.3 to +7.0

-0.3 to + 8.0

-0.3 to VDD +0.3

-30 to +85

Unit

V_IN

Operating temperature

Storage temperature

T_OPR

T_STG

°C

-55 to +125

NOTE1: All the voltage levels are based on VSS = 0V.

NOTE2: Voltage greater than above may damage the circuit.

Voltage level: V0 ³ VDD ³ VSS

Voltage level: V0 ³ V1 ³ V2 ³ V3 ³ V4 ³ VSS

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS

Table 12. DC Characteristics

(VDD = 2.4V to 3.6V, Ta = -30 to +85 ^oC)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Operating voltage

VDD

2.4

3.6

Display operation

V0 = 6V without load

No access from MPU

I_DD1

Supply current

(VDD = 3V, Ta = 25 ^oC)

Access operation from MPU

fcyc = 200kHz

I_DD2

500

V_IH

V_IL

0.7VDD

VDD

0.3VDD

Input voltage

Input leakage current

RON resistance

VSS

-1

I_LEAK

R_COM

R_SEG

f_FR

V_IN= 0V to VDD

Io = ± 50mA

VDD = 3V, Ta = 25 ^oC

Frame frequency

101

External clock

frequency

f_CK

40.0

kHz

LCD driving voltage

V_LCD

V_LCD= V0 – VSS

3.0

6.0

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

PRELIMINARY SPEC. VER. 0.5

KS0032

Table 12. DC Characteristics (Continued)

(VDD = 3.6V to 5.5V, Ta = -30 to +85 ^oC)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Operating voltage

VDD

3.6

5.5

Display operation

V0 = 6V without load

No access from MPU

I_DD1

Supply current

(VDD = 5V, Ta = 25 ^oC)

Access operation from MPU

fcyc = 200kHz

I_DD2

1000

V_IH

V_IL

0.7VDD

VDD

0.3VDD

Input voltage

Input leakage current

RON resistance

VSS

-1

I_LEAK

R_COM

R_SEG

f_FR

V_IN= 0V to VDD

Io = ± 50mA

VDD = 3V, Ta = 25 ^oC

Frame frequency

101

External clock

frequency

f_CK

40.0

kHz

LCD driving voltage

V_LCD

V_LCD= V0 – VSS

3.6

6.0

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

AC CHARACTERISTICS

6800-series MPU Interface & Write Instruction

Table 13. AC Characteristics (6800-series Write Instruction)

Condition

Characteristic

Min.

Typ.

Max.

Unit

Symbol

E cycle time

Pulse rise / fall time

E pulse width high

E pulse width low

RS and CSB setup time

RS and CSB hold time

DB setup time

t_C

t_R, t_F

t_WH

t_WL

t_SU1

t_H1

650

450

150

VDD = 2.4V to 3.6V,

Ta = -30 to +85 ^oC

t_SU2

t_H2

100

DB hold time

E cycle time

t_C

350

Pulse rise / fall time

E pulse width high

E pulse width low

RS and CSB setup time

RS and CSB hold time

DB setup time

t_R, t_F

t_WH

t_WL

t_SU1

t_H1

250

100

VDD = 3.6V to 5.5V,

Ta = -30 to +85 ^oC

t_SU2

t_H2

DB hold time

RS, CSB

RW_WR

t_SU1

t_H1

t_WH

t_WL

t_F

E_RD

t_SU2

t_H2

t_R

DB0 to DB7

t_C

Figure 18. Write Bus Mode Timing (6800-series MPU Interface)

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

8080-series MPU Interface & Write Instruction

PRELIMINARY SPEC. VER. 0.5

KS0032

Table 14. AC Characteristics (8080-series Write Instruction)

Condition

Characteristic

Min.

Typ.

Max.

Unit

Symbol

WR cycle time

Pulse rise / fall time

WR pulse width high

WR pulse width low

RS and CSB setup time

RS and CSB hold time

DB setup time

t_C

t_R, t_F

t_WH

t_WL

t_SU1

t_H1

650

150

450

VDD = 2.4V to 3.6V,

Ta = -30 to +85 ^oC

t_SU2

t_H2

100

DB hold time

WR cycle time

t_C

350

Pulse rise / fall time

WR pulse width high

WR pulse width low

RS and CSB setup time

RS and CSB hold time

DB setup time

t_R, t_F

t_WH

t_WL

t_SU1

t_H1

100

250

VDD = 3.6V to 5.5V,

Ta = -30 to +85 ^oC

t_SU2

t_H2

DB hold time

RS, CSB

t_SU1

t_WL

t_H1

t_WH

t_R

RW_WR

t_F

t_SU2

t_H2

DB0 to DB7

t_C

Figure 19. Write Bus Mode Timing (8080-series MPU Interface)

KS0032

PRELIMINARY SPEC. VER. 0.5

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

6800-series MPU Interface & Read Instruction

Table 15. AC Characteristics (6800-series Read Instruction)

Condition

Characteristic

Min.

Typ.

Max.

Unit

Symbol

E cycle time

Pulse rise / fall time

E pulse width high

E pulse width low

t_C

t_R,t_F

t_WH

t_WL

t_SU

t_H

650

450

150

VDD = 2.4V to 3.6V,

Ta = -30 to +85 ^oC

RS and CSB setup time

RS and CSB hold time

DB output delay time

DB output hold time

E cycle time

t_D

360

t_DH

t_C

350

Pulse rise / fall time

E pulse width high

E pulse width low

t_R,t_F

t_WH

t_WL

t_SU

t_H

250

100

VDD = 3.6V to 5.5V,

Ta = -30 to +85 ^oC

RS and CSB setup time

RS and CSB hold time

DB output delay time

DB output hold time

120

t_D

t_DH

RS, CSB

RW_WR

E_RD

t_SU

t_H

t_WH

t_WL

t_F

t_D

t_DH

t_R

DB0 toDB7

t_C

Figure 20. Read Bus Mode Timing (6800-series MPU Interface)

16 COM / 80 SEG DRIVER & CONTROLLER FOR STN LCD

8080-series MPU Interface & Read Instruction

PRELIMINARY SPEC. VER. 0.5

KS0032

Table 16. AC Characteristics (8080-series Read Instruction)

Condition

Characteristic

Min.

Typ.

Max.

Unit

Symbol

RD cycle time

Pulse rise / fall time

RD pulse width high

RD pulse width low

RS and CSB setup time

RS and CSB hold time

DB output delay time

DB output hold time

RD cycle time

t_C

t_R,t_F

t_WH

t_WL

t_SU

t_H

650

150

450

VDD = 2.4V to 3.6V,

Ta = -30 to +85 ^oC

t_D

360

t_DH

t_C

350

Pulse rise / fall time

RD pulse width high

RD pulse width low

RS and CSB setup time

RS and CSB hold time

DB output delay time

DB output hold time

t_R,t_F

t_WH

t_WL

t_SU

t_H

100

250

VDD = 3.6V to 5.5V,

Ta = -30 to +85 ^oC

120

t_D

t_DH

RS, CSB

t_SU

t_WL

t_H

t_WH

t_R

E_RD

t_F

t_D

t_DH

DB0 to DB7

t_C

Figure 21. Read Bus Mode Timing (8080-series MPU Interface)

KS0032 [SAMSUNG]

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