KS0123 [SAMSUNG]
DIGITAL VIDEO ENCODER; 数字视频编码器
| 型号： | KS0123 |
| 厂家： | 
SAMSUNG |
| 描述： | DIGITAL VIDEO ENCODER |
| 文件： | 总44页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS0123 Data Sheet
MULTIMEDIA VIDEO
DIGITAL VIDEO ENCODER
The KS0123 multi-standard video encoder converts CCIR
656 8-bit multiplexed digital component video into analog
baseband signals. It outputs composite video (CVBS) and
S-Video simultaneously at three analog output pins.
44 PLCC
The encoder implements Macrovision revision 6.0 anti-
taping scheme. Additionally, it contains a color subcarrier
genlock to support analog/digital video splicing.
The video outputs conform to either SMPTE 170M (NTSC)
or CCIR 624 (PAL) standards.
ORDERING INFORMATION
FEATURES
Device
Package
44 PLCC
Temperature Range
0°~+70°C
• Macrovision revision 6.0 anti-taping support
• 8-bit parallel CCIR 656 CbYCr input format
KS0123
• Synchronizes to CCIR 656 AVE time reference codes
for horizontal and vertical timing generation inslave
mode operation
• 27 MHz DAC conversion rate
• Triple 10-bit DAC’s for simultaneous S-video
and composite output
• 2 -wire serial host interface
• 8 general purpose I/O pins
• JTAG test interface
• Generates HSYN and FIELD signals inmaster mode
operation
• Programmable subcarrier frequency, SCH phase,
and synchronous field display to support MPEG II
picture-coding-extension
• Optional subcarrier genlock to analog f
refer-
• Single 5 V supply with power down mode
• 44-pin PLCC package
sc_ref
ence
• 650 kHz or 1.3 MHz chrominance bandwidth selec-
tion
• Support NTSC, PAL, PAL-M and PAL-N
Application
• Settop Box Video Encoding
• MPEG Playback
• Multimedia
• Switchable pedestal with gain compensation
• Selectable 37 nsec YC delay pre-compensation
• Video outputs meet SMPTE 170M or CCIR 624 spec
BLOCK DIAGRAM
LPF
PXCK
B-Y
R-Y
10-bit
DAC
C
Chroma
Modulator
Interpolator
4:2:2/4:4:4
Demux
and
PD[7:0]
Sync
INT
extract
10-bit
DAC
LPF
Y
Y
Sync
HSYN
FIELD
& Blank
insert
10-bit
DAC
Video
Timing
Gen
CVBS
+
SDA
SCL
SA1
SA2
Subcarrier
Synthesizer
Analog
Interface
D/A
Ref.
Genlock
JTAG
RESET
CSync
Clamp
Genlock
Interface
General purpose
I/O
Modified on May/04/2000
PAGE 1 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
PIN ASSIGNMENT - 44 PLCC
39 38 37 36 35 34 33 32 31 30 29
PD5 40
PD4 41
PD3 42
PD2 43
PD1 44
28 RREF
27 VREF
26 VDDA
25 PXCK
24 VSS
23 VDD
22 RESET
21 TCK
20 TMS
19 TDI
VDD
VSS
PD0
SA2
SA1
SDA
1
2
3
4
5
6
KS0123
18 TDO
7
8
9
10 11 12 13 14 15 16 17
TYPICAL APPLICATION
The Encoder is shown in a typical settop box application.
MPEG
CHANNEL
ENCODER
KS0123
VIDEO
DECODER
DECODER
TV Monitor
Figure 1. Typical Application
Modified on May/04/2000
PAGE 2 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
PIN DESCRIPTION
Pin Name
CLOCK INPUT
PXCK
Pin #
Type
Description
25
I
I
27 MHz clock input. TTL/CMOS.
PIXEL DATA PORT
PD7 - PD0 38-44, 3
Pixel data inputs. TTL/CMOS.
GENERAL PURPOSE PORT AND OTHER SIGNALS
SC_REF
8
9
I
Subcarrier reference input. TTL.
D7/PAL_ID
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Port 7 or PAL_ID input. TTL/CMOS.
General Purpose I/O Port 6 or SC_SYNC input. TTL/CMOS.
General Purpose I/O Port 5. TTL/CMOS.
D6/SC_SYNC 10
D5
11
12
14
15
16
17
D4
General Purpose I/O Port 4. TTL/CMOS.
D3/HSYN
D2/FIELD
D1/CLAMP
D0/CSYN
General Purpose I/O Port 3 or HSYN output. TTL/CMOS.
General Purpose I/O Port 2 or FIELD output. TTL/CMOS.
General Purpose I/O Port 1 or CLAMP output. TTL/CMOS.
General Purpose I/O Port 0 or CSYN output. TTL/CMOS.
SERIAL MICROPROCESSOR PORT
SDA
6
7
5
4
I/O
Serial data I/O. Open drain.
Serial clock input.
SCL
I
I
I
SA1
Slave address select. TTL.
Slave address select. TTL.
SA2
RESET
RESET
22
I
Master reset input. TTL.
VIDEO OUTPUTS
CVBS
30
32
35
O
O
O
Composite video output.
Luminance output.
Y
C
Chrominance output.
DAC REFERENCE AND COMPENSATION
VREF
27
33
28
I/O
I/O
I/O
Voltage reference I/O. Connect a 0.1 mF capacitor to VSSA.
Compensation capacitor. Connect a 0.1 mF capacitor to VDDA.
Current setting resistor.
BYPASS
RREF
Modified on May/04/2000
PAGE 3 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
PIN DESCRIPTION (Continued)
Pin Name
JTAG PORT
TDI
Pin #
Type
Description
19
20
21
18
I
I
Data input port. TTL.
Scan select input. TTL.
Scan clock input. TTL.
Data output port. CMOS.
TMS
TCK
I
TDO
O
POWER
VDD
1,23,37
26,34
+5V
+5V
Digital power supply.
Analog power supply.
VDDA
GROUND
VSS
2,13,24,36
29,31
0V
0V
Digital ground.
Analog ground.
VSSA
Modified on May/04/2000
PAGE 4 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
PIN CROSS REFERENCE
Numerical Order by Pin Number
Pin #
Name
VDD
Pin #
12
Name
D4
Pin #
23
Name
VDD
Pin #
Name
VDDA
C
1
2
34
35
36
37
38
39
40
41
42
43
44
VSS
13
VSS
24
VSS
3
PD0
14
D3/HSYN
D2/FIELD
D1
25
PXCK
VDDA
VREF
RREF
VSSA
CVBS
VSSA
Y
VSS
VDD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
4
SA2
15
26
5
SA1
16
27
6
SDA
17
D0
28
7
SCL
18
TD0
29
8
SC_REF
D7/PAL_ID
D6/SC_SYNC
D5
19
TD1
30
9
20
TMS
31
10
11
21
TCK
32
22
RESET
33
BYPASS
Alphabetical Order by Pin Name
Name
BYPASS
C
Pin #
33
35
30
17
16
15
14
12
11
10
9
Name
PD0
Pin #
Name
Pin #
Name
VDD
VDDA
VDDA
VREF
VSS
Pin #
3
SA1
SA2
5
6
37
26
34
27
2
PD1
44
43
42
41
40
39
38
25
22
28
CVBS
PD2
SCL
7
D0
PD3
SC_REF
SDA
TCK
8
D1
PD4
6
D2/FIELD
D3/HSYN
D4
PD5
21
19
18
20
1
VSS
13
24
36
29
31
32
PD6
TDI
VSS
PD7
TDO
TMS
VDD
VDD
VSS
D5
PXCK
RESET
RREF
VSSA
VSSA
Y
D6/SC_SYNC
D7/PAL_ID
23
Modified on May/04/2000
PAGE 5 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
GENERAL DESCRIPTION
The encoder accepts 27 MHz 8-bit multiplexed digital component video in CCIR 656 CbYCr format at the Pixel
Data (PD) port. The pixel data are demultiplexed into luminance and chrominance components for interpolation
and low pass filtering to reduce cross luma/chroma interference. The filtered chrominance signals are modulated
onto a color subcarrier and added to the processed luminance components to form the composite video (CVBS).
The digital CVBS and S-Video signals are interpolated to 27 MHz rate and then converted to analog forms by 3 10-
bit D/A converters.
Anti-taping pulses, synch signals and color burst are generated internally. The rise and fall times of those pulses
are controlled to reduce ringing. The shaped signals are inserted into the video stream controlled by the timing
generator.
The encoder also contains a color subcarrier PLL, which when enabled will frequency and phase lock the color
subcarrier to an external analog fsc or 4 x fsc reference. The SCH phase can be adjusted to compensate for
additional external phase delay.
VIDEO DATA INPUT
VIDEO OUTPUTS
PD[7:0]
CVBS
Y
PXCK
C
HSYN
FIELD
DIGITAL
VIDEO
ANALOG INTERFACE
VREF
BYPASS
RREF
SDA
SCL
SA1
SA2
HOST
INTERFACE
ENCODER
RESET
JTAG TEST INTERFACE
GENERAL PURPOSE
TDI
TMS
PORT
D[7:0]
TCK
TDO
SC_REF
SC_SYNC
PAL_ID
GENLOCK
INPUT
Figure 2. Logic Diagram
Modified on May/04/2000
PAGE 6 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
DIGITAL VIDEO INPUT FORMAT
Video data enters the encoder on pins PD[7:0]. The encoder accepts and processes digital video data in
accordance with CCIR 656and CCIR 601standards. The input data are 8 bit multiplexed CbYCr component video,
encoded in the 4:2:2 format. The input bit stream may contain End of Active Video (EAV) and Horizontal Ancillary
Control (HANC) codes. The relationships of the digital video with analog timing are show in Figure 3.
CCIR 656 Timing Relationship Between Video Data and The Analog Sync Waveform
The digital active line begins at 244 words (in the 525-line standard) or at 264 words (in the 625-line standard) after
the leading edge of the analog line synchronization pulse, this time being specified between half-amplitude points.
Analog line blanking
O
O
TV line
64us (625)
H
H
63.5us (525)
16T (625)
8T (525)
20T (625)
10T (525)
24T (625)
32T (525)
Video data block
1448T
S
A
V
E
A
V
Multiplexed video data
E
A
V
HANC
HANC
C Y C Y C Y...
B
R
B
4T
4T
Digital line blanking
Digital active line
1440T
288T (625)
276T (525)
Digital line
1728T (625)
1716T (525)
T: clock period 37ns nom.
SAV: start of active video timing ref. code
EAV: end of active video timing ref. code
HANC: horizontal ancillary data
Figure 3. 656 Data Format and Timing Relationship
Modified on May/04/2000
PAGE 7 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Timing Reference Codes
Each video line can have two timing reference codes, one at the beginning of the data block (start of active video
SAV) and one at the end (end of active video EAV) as shown in Figure 3. Each timing reference code consists of a
four byte sequence in the form FF, 00, 00 and XX as shown in Table 1. The first three words are fixed, the fourth
byte contains field and line blanking information.
Table 1: Video Timing Reference Codes
Bit # 7(MSB)
6
1
0
0
F
5
1
0
0
V
4
1
0
0
H
3
1
0
0
2
1
0
0
1
1
0
0
0(LSB)
HEX
FF
First
Second
Third
1
0
0
1
1
0
0
00
00
Fourth
Notes:
P
P
P
P
0
XX
3
2
1
F = 0 during field 1
1 during field 2
V = 0 elsewhere
1 during field blanking
H = 0 in SAV
1 in EAV
P - - P : Protection bits (not used by the encoder)
3
0
The encoder decodes the video timing reference code that indicates the end of active video (EAV). The EAV code
shall contain the F (field) and V (blanking) bits as specified in CCIR 656. This information applies to the following
video line. The encoder ignores the start of active video (SAV) timing code.
The encoder uses the F bit for synchronization purposes. The transition of F bit is used to indicate the start of a
new field. The polarity is also used to indicate odd and even. Additional field information is supplied by the ancillary
data.
The V bit is not used for synchronization. A V of ‘1’ indicates line blanking. Certain lines and half lines are blanked
regardless of the state of the V bit. In general if the V bit is high, then the encoder blanks the line (Figure 10 and
Figure 11).
Modified on May/04/2000
PAGE 8 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Horizontal Ancillary Data Sequence (HANC)
The ancillary data contains additional timing information about the following video line. Table 2 shows the
sequence of the ancillary data. The HANC data, if present, should immediately follow the EAV code. The encoder
decodes the ancillary data if the ancillary data type code (TT) matches the data ID code stored in the internal
ANCDID register (index 07h).
The LSB of the ancillary data is a parity bit. The video encoder assumes that the data is error free and always
ignores this bit.
Table 2: Ancillary Data Sequence
Word ID
ANC(2)
ANC(1)
ANC(0)
TT
Description
B7
0
B6
0
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
Ancillary Data
Header
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Data Type
Reserved
TT6
(R)
(R)
(R)
TT5
(R)
(R)
(R)
TT4
(R)
(R)
(R)
TT3
(R)
(R)
SVF/
TT2
(R)
(R)
F2
TT1
(R)
(R)
F1
TT0
(R)
(R)
F0
P
P
P
P
FIELD Field number and
synchronous
video flag
PH(1)
PH(0)
Subcarrier
Instantaneous
Phase
PHV
PH6
PH12
PH5
PH11
PH4
PH10
PH3
PH9
PH2
PH8
PH1
PH7
PH0
P
P
FR(4)
FR(3)
FR(2)
FR(1)
FR(0)
Subcarrier
Frequency
FRV
FR27
FR20
FR13
FR6
(R)
(R)
FR31
FR24
FR17
FR10
FR3
FR30
FR23
FR16
FR9
FR29
FR22
FR15
FR8
FR28
FR21
FR14
FR7
P
P
P
P
P
FR26
FR19
FR12
FR5
FR25
FR18
FR11
FR4
FR2
FR1
FR0
Note: 1. P = odd parity bit
2. R = reserved bit; ignored by video encoder
The ancillary data header(ANC) consists of three bytes which indicate the start of the ancillary data. This is in
accordance with CCIR 656.
The data type code is used to specify the ancillary data type. The encoder compares this value with the value
programmed into the ANCDID register. If the two match, the encoder will process the ancillary data, otherwise the
encoder will ignore the ancillary data.
The field numberbits are used by the encoder to program the field counter. The field number will be loaded to the
counter if SVF/ is low and the ancillary timing reference enable (ATMEN) bit is ‘1’.
Modified on May/04/2000
PAGE 9 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
The subcarrier instantaneous phaseis a 13-bit integer which defines the phase of the reference subcarrier at the
synch tip. The subcarrier frequency synthesizer phase will be reset to this number at the synch tip when both
HANC datum PHV and control register APHEN are ‘1’s.
Table 3:Definition of Subcarrier Instantaneous Phase
subcarrier phase #
phase value
0
1
([3600 / 8192]) 0
*
([3600 / 8192]) 1
*
...
...
8191
([3600 / 8192]) 8191
*
The MPEG II system allows the 27 MHz clock frequency to vary to prevent the input buffer from overflow or
underflow. When this happens the color subcarrier frequency will shift if the addend of numerical oscillator is not
adjusted accordingly. If control register bit AFREN is ‘1’ the subcarrier synthersizer will select the latched HANC’s
subcarrier frequencydata (FR) as the addend instead of the programmable register (0x8-0xb) (Figure 6). The FR
is latched if HANC datum FRV = ‘1’. and the HANC control register’s AFREN bit is set. The FR’s value should be
calculated using the equation
Fsc
æ 32
FR = NINT 2
ö
----------
·
è
ø
Ck
where Fsc is the desired color subcarrier frequency,
Ck is the clock frequency,
and NINT is the nearest integer.
Modified on May/04/2000
PAGE 10 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
VIDEO ENCODING
The incoming digital video are gain and offset adjusted according to the output format, NTSC or PAL, controlled by
the format register. Both the luminance and chrominance are band limited and interpolated to 27 MHz sampling
rate for digital to analog conversion. The NTSC output can be selected to include a 7.5 IRE pedestal. The user can
also select either 650 kHz or 1.35 MHz chrominance bandwidth. The U and V components have equal
bandwidth.
Luminance Filter
The luminance signal is band-limited to 6 MHz. The filter is implemented with a 15 tap linear phase FIR filter. Figure
4 shows the frequency responses.
0
0
-5
-0.2
-10
-0.4
-15
-20
-25
-30
-35
-40
-45
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
0
2
4
6
8
10
12
0
1
2
3
Mhz
4
5
6
Mhz
Figure 4. Luminance Filter Frequency Response
Modified on May/04/2000
PAGE 11 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Chrominance Filter
Figure 6 shows the chrominance frequency response for different bandwidth selections.
0
0
-5
-5
-10
-15
-20
-25
-10
-15
-20
-25
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
Mhz
3
3.5
4
4.5
5
Mhz
CHRBW = ‘1’
CHRBW = ‘0’
Figure 5. Chrominance Filter Frequency Response
Modified on May/04/2000
PAGE 12 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
COLOR SUBCARRIER GENERATION
The chrominance signals are modulated onto a subcarrier. The nominal subcarrier frequency is determined by 4
registers (08h - 0Bh). The subcarrier generation also contains Subcarrier Horizontal Synch Phase, SCH, offset
control (Reg 0Ch - 0Dh), and genlock functions to support digital/analog video multiplexing.
PH
FR
Figure 6. Fsc Synthersizer
The color subcarrier synthesizer can operate in 3 modes: (a) free running mode, (b) HANC genlock mode, and (c)
analog genlock mode.
(a). In the free running modethe color subcarrier frequency is programmed via the host interface. The 4 field or 8
field SCH phase are maintained. The nominal frequency register values for different video standards are listed in
Table 4.
Table 4: Register Values for Subcarrier Frequencies
Frequency Register
Subcarrier
Standard
Frequency(MHz)
FREQD FREQC FREQB FREQA
NTSC
PAL-B,G,H,I
PAL-M
3.57954545
4.43361875
3.57561189
3.58205625
43
54
43
43
E0
13
F8
15
DF
28
3E
96
CD
ED
C7
8D
PAL-N
(b). In the HANC genlock modethe subcarrier frequency, FR, and instantaneous phase, PH, information are sent
to the encoder via the HANC data. The frequency and phase values are updated during the synch tip.
(c). If analog genlock modeis selected the subcarrier synthesizer is locked to an external reference signal, fsc or
4 fsc. An external PAL_ID signal is required to control the PAL phase alternation. The PLL has 2 kHz pull in range.
Analog Genlock Circuit
The analog genlock circuit will lock the frequency and phase of the subcarrier synthesizer to an external reference
signal. To activate the genlock circuit, first program the nominal FREQD-A value then set GENEN = 1.The external
Modified on May/04/2000
PAGE 13 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
reference signal is applied to the SC_REF input pin. The frequency of this squarewave is either Fsc or 4*Fsc
(program the 4FSCS bit accordingly). When using a 4*Fsc input, the SC_SYNC resets the internal divider’s phase
to the 0 count state as shown in Figure 7. The SCHM and SCHL registers can be programmed to compensate for
the propagation delay from the phase detector input to the DAC output.
1/(4 *SC_REF)
t
SC_REF(== 4fsc)
PWH;SC_REF
t
SU;SC_SYNC
t
HD;SC_SYNC
SC_SYNC
internal divided by 4 counter output
Figure 7. SC_REF and SC_SYNC Input Timing
PAL_ID Input
The PAL_ID input is used by the analog genlock circuit to control the PAL chroma V-axis inversion. PAL_ID is only
recognized when GENEN = 1 and the video format is PAL. PAL_ID is low for lines where the color burst phase is
o
o
135 , and high for lines where the color burst phase is -135 . PAL_ID is sampled and its value is used on the
following line. The PAL_ID should be valid during the time interval corresponding to video samples 1440 to 1449.
See Figure 8 for the PAL_ID timing requirement.
Pixel Data Input (PD[7:0])
Sample number
1442 1443 1444 1445 1446 1447 1448 1449
1439 1440 1441
1450
$00 $00 $XX
Y 719 $FF
Ancillary Data...
EAV Sequence
t
DUR;PAL_ID
PAL_ID Stable
D7 Input (PAL_ID)
Figure 8.PAL_ID Input Timing
Modified on May/04/2000
PAGE 14 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
SC_SYNC and PAL_ID Pins
The SC_SYNC and PAL_ID inputs are shared with the D6 and D7 general purpose I/O pins respectively. To
configure D6 as the SC_SYNC input, the register value of [DDR6, GENEN, 4FSCS] must be set to [0, 1, 1]. To
activate the PAL_ID input, the register value of [DDR7, GENEN, FORMAT] must be set to [0, 1, 01] or [0, 1, 10].
SCH Phase Control
The video encoder maintains a constant 4-field (NTSC) or 8-field (PAL) sub-carrier/horizontal synch phase
relationship in the free running mode by resetting the subcarrier synthesizer every 8 fields. In all mode of
operations the SCH phase can be adjusted via SCHM and SCHB registers to compensate external phase delay.
VIDEO TIMING GENERATION
The decoder can operate either in master mode or slave mode. In the salve mode, the encoder extracts the
horizontal and vertical sync timing, blanking, and field count information from the timing reference codes (EAV) in
the pixel data stream. Additional timing data may be extracted from horizontal ancillary (HANC) data. The ancillary
data definition is shown in Table 2.
In the master mode, the encoder generates horizontal synch (HSYN) and field (FIELD) signals. The FIELD signal
is high for the even field period. To enable the master mode the direction register DDR3 and DDR2 must be set to
‘1’s and the reserved register 0x83 must be set to 0x18.
Figure 9. Master Mode Video Interface Timing
Modified on May/04/2000
PAGE 15 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Analog Fields 1&3
(blanked, V=X)
F=0
V=0 (active video) or
V=1 (blanked)
Digital Fields 1&3
524
525
10
11-19 20
21
22
1
2
3
4
5
6
7
8
9
COMP SYNC
VVSYNC\
Analog
Fields 2&4
V=0 (active video) or
V=1 (blanked)
F=1
Digital Fields 2&4
(blanked,
V=X)
274-
281 282
273
262
263
283
284
264 265 266 267 268 269 270 271 272
COMP SYNC
VVSYNC\
Figure 10.NTSC Vertical Interval
Modified on May/04/2000
PAGE 16 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
V=0 (active video) or
V=1 (blanked)
(blanked,
V=X)
F=0
Analog and digital
Fields 1,3,5 & 7
623
6
7
8-22
23
24
25
621 622
624 625
1
2
3
4
5
COMP SYNC
VVSYNC\
F=1
(blanked,
V=X)
V=0 (active video) or
V=1 (blanked)
Digital Fields 2,4,6 & 8
Analog Fields 2,4,6 & 8
322-
320 321 334
319
336
309 310
335
311 312 313 314 315 316 317 318
COMP SYNC
VVSYNC\
Figure 11.PAL-B, G, H, I, N Vertical Interval
Modified on May/04/2000
PAGE 17 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Internal Test Ramp Signal Generation
The modulated ramp test signal is enabled through the host interface by setting the RAMPEN bit high. Additionally
the PDEN must be set to zero to disable the pedestal and reserved registers 0x10 and 0x11 be set to ‘0’s as well.
The ramp signal can be used for differential gain and phase measurements. The luminance component ramps
from blanking level (0 IRE) to maximum white (100 IRE). The chroma has 40 IRE constant amplitude.
Macrovision Anti-taping
The Macrovision anti-taping revision 6 for PPV application is implemented. For more information please contact
Samsung LA Design Center.
Power on Reset
The reset line is an active low signal that is used to initialize the device. Setting RESET low sets all internal state
machines and control registers to their initial conditions, disables all digital and analog outputs (high impedance),
and places the encoder in a power-down mode.
The reserved register (0x10 - 0x1f) must be set to zero manually for proper operation.
Modified on May/04/2000
PAGE 18 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
General Purpose I/O Port and Other Signals
Pins D7 through D0 form a general purpose I/O port where some pins have a dual function. The list below indicates
the pin functionality. The directions of the I/Os are controlled by the DDR register.
Table 5:General Purpose I/O Functions
Pin
Function
D7 / PAL_ID
General purpose I/O port; also used as the PAL_ID (PAL phase identification) signal
input in the analog genlock mode. (see page 15)
D6 / SC_SYNC General purpose I/O port; also used as the SC_SYNC (subcarrier sync) signal
input.(see page 15)
D5 - D4
General purpose I/O ports only.
D3/HSYN
General purpose I/O port in slave mode. HSYN output in Master mode.(see
page 15)
D2/FIELD
General purpose I/O port in slave mode. FIELD output in Master mode.(see
page 15)
D1/CLAMP
D0/CSYN
General purpose I/O port; also used as the CLAMP (clamp gate) output signal.
General purpose I/O port; also used as the CSYN (composite sync) output signal.
The CSYN (composite sync) output is shared with D0 pin, and is programmed with the DDR0 and CSDIS control
bits as shown below.
Table 6: Control of Pin D0/CSYN
DDR0 CSDIS
Effect of a GPP0 write on
D0/CSYN
GPP0 read value
Configuration
reg.
reg.
0
X
Logic state applied to D0
not defined
no effect
general purpose input
general purpose output
CSYN output
1
1
outputs GPP0 logic state
no effect
1
0
not defined
The CLAMP output is shared with D1 pin, and is programmed with the DDR1 and CLMDIS control bits as shown
below.
Table 7: Control of Pin D1/CLAMP
DDR1 CLMDIS
Effect of a GPP1 write on
D1/CLAMP
GPP1 read value
Configuration
reg
reg
0
X
Logic state applied to D1
not defined
no effect
general purpose input
general purpose output
CLAMP output
1
1
outputs GPP1 logic state
no effect
1
0
not defined
Modified on May/04/2000
PAGE 19 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
D/A Converters
The analog outputs of the encoder come from the three 10-bit D/A converters, operating at a 27 MHz clock rate.
The outputs can drive standard video levels into a 75 or 37.5 ohm load. An internal voltage reference can be used
to provide reference current for the three D/A converters. For accurate video levels, an external fixed or variable
voltage reference source can be used. The video signal levels from the encoder may be adjusted to overcome the
insertion loss of analog low-pass output filters by varying RREF or VREF
.
There are three analog video outputs, one composite, one luminance, and one chrominance. The composite and
S-video DACs can be disabled independently to save power.
The components required for the DAC voltage and current reference is shown below. The 787 ohm resistor should
be used for single end 75 ohm termination while the 394 ohm resistor for double end 75 ohm termination.
VDD
0.1mF
Vref
COMP
VREF
+
_
0.1mF
IREF
787
(394)
Figure 12. Voltage and Current Reference Components
Two reconstruction filters are suggested for the output of the D/A converters. The one shown in Figure 13 is
designed to be a single 75 ohm load to the D/A output; while the one shown in Figure 14 is for the double ended
termination.
10pF 1%
Video Op Amp
5.6 mH 5%
(Av = 2)
DAC
Output
75
Output
+
_
180pF
1%
100
1%
100pF
1%
301
1%
1K
1K
75
Figure 13.Reconstruction Filter for Single Ended Termination
Modified on May/04/2000
PAGE 20 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
2.0mH
1.3mH
75W
75W
100pF
300pF
100pF
Figure 14.Reconstruction Filter for Double Ended Termination
Modified on May/04/2000
PAGE 21 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Serial Host Interface
The internal control registers of the encoder are read and written via a two wire serial port. The two wire port
consists of a serial I/O data line (SDA) and a clock (SCL) input. Each of the SDA and SCL line is connected to
+VDD with a pull-up resistor. The data on the SDA line must be stable when the clock (SCL) is high. Data can only
change while SCL is low. Transitions on SDA while SCL is high indicate start (high to low transition) and stop (low
to high) conditions. When both lines are high, the bus is considered to be free.
Communication consists of five parts: the START signal, slave address transmission, (register address
transmission), data transfer, and the STOP signal. When the bus is free, a master initiates communication by
sending a start signal (high to low of SDA while SCL is high). The first byte transferred after the start signal is a
seven bit long slave address followed by the eighth R/W bit. The R/W bit indicates the direction of data transfer
(high = read). If the slave address matches that of the encoder (set with pins SA1 and SA2), the encoder will
acknowledge by pulling SDA low during the 9th clock. The bytes following the slave address are the data to or from
the encoder. Each byte is 8 bits long with the MSB transferred first. Each byte is followed by an acknowledge by
the receiving device by pulling the SDA line low during the 9th clock. A stop signal is created when the master
sends a low to high on the SDA line with SCL high. Figure 15 shows the data transfer and acknowledge on the
serial bus.
SDA
acknowledgment
MSB
1
acknowledgment
signal from receiver
signal from receiver
clock line held low while
interrupts are serviced
byte complete,
interrupt in receiver
SCL
2
7
8
9
ACK
1
2
3 8
9
ACK
S
P
START CONDITION
STOP CONDITION
SERIAL DATA TRANSFER
Data output
by transmitter
not acknowledge
Data output
by receiver
acknowledge
8
SCL from
master
1
9
2
S
clock pulse for
acknowledgment
START CONDITION
ACKNOWLEDGE ON THE SERIAL BUS
Figure 15. Serial Bus Timing
Modified on May/04/2000
PAGE 22 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
The master must specify a base address (BAR) when it accesses the encoders registers. The base address is
written to the encoder following the slave address when the R/W bit is low. For encoder register writes, data bytes
are sent to the control registers starting with the register selected by the BAR and incremented by one address for
each additional data byte transferred (auto increment). To read data from the encoder control registers, two data
transfer operations are required. The first one writes the BAR (R/W = 0) and the second one is to read the data (R/
W = 1). Figure 16 explains the data transfer operations.
Write to Control Registers
Read from Control Registers
START signal
START signal
Slave address (R/W = 0)
Base address (BAR)
Data transfer (master to
encoder, one or more bytes)
STOP signal
Slave address (R/W = 0)
Base address (BAR)
STOP signal
START signal
Slave address (R/W = 1)
Data transfer (encoder to
master, one or more bytes)
STOP signal
Figure 16. Typical Write and Read Operations
Two address select pins are used to select one of four slave addresses, the slave address is seven bits long. Refer
to Table 8 for the possible slave addresses.
Table 8: Serial Port Slave Addresses
A1
(SA2)
A0
(SA1)
A6
A5
A4
A3
A2
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
The serial port timing parameters are shown below, refer to the timing tables at the end of this data sheet for the
values.
Modified on May/04/2000
PAGE 23 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
REPEATED
START
STOP START
STOP
SDA
t
BUF
t
F
t
HD;STA
t
t
SU;STO
LOW
t
R
t
HIGH
SCL
t
HD;STA
t
SU;STA
t
t
SU;DAT
HD;DAT
Figure 17.Serial Port Timing Parameters
JTAG Test Interface
The encoder includes a 4-line JTAG test interface port (as modified herein), providing access to all digital input/
output data pins except the JTAG test port pins, analog pins, power and ground. This is provided to facilitate
component and board-level testing. Table 9 shows the sequence of the test registers. The register number
indicates the order in which the register data is loaded and read. The scan is 23 registers long.
The test data input (TDI) and test mode select (TMS) inputs are referred to the rising edge of the test clock (TCK)
input. The test data output (TDO) is referred to the falling edge of TCK.
Table 9: JTAG Sequence List
JTAG Reg
Pin
RESET
PXCK
PD7
JTAG Reg
Pin
PD1
JTAG Reg
Pin
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
17
18
19
20
21
22
23
10
11
12
13
14
15
16
PD0
SA2
PD6
SA1
PD5
SDA
SCL
PD4
PD3
SC_REF
D7
PD2
Modified on May/04/2000
PAGE 24 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
The JTAG test port timing is shown below, refer to the timing tables at the end of this data sheet for the values.
t
t
PWHTCK
PWLTCK
TCK
t
t
HTP
STP
TDI
TMS
t
DOTP
t
HOTP
TDO
Figure 18.JTAG Test Port Timing
Modified on May/04/2000
PAGE 25 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
CONTROL REGISTERS
The encoder is controlled by a set of registers which allow adjustment of its operating parameters. The registers
are written to and read from via the serial bus interface. Unless otherwise specified, all registers are read/write
registers. The suffix “h” denotes hex numbers. In the detailed register description, the default value is followed by
an “*”.
Table 10:Control Registers
Index Mnemonic Default
Description
Part ID Register C (read only)
Part ID Register B (read only)
Part ID Register A (read only)
Part Revision Number (read only)
Global Control Register
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10-FFh
PIDC
91h
88h
79h
01h
00h
00h
00h
00h
43h
E0h
F8h
3Eh
00h
00h
00h
00h
PIDB
PIDA
REVID
GCR
VOCR
HANC
ANCDID
FREQD*
FREQC*
FREQB*
FREQA
SCHM
SCHL
GPP
Video Output Control Register
Horizontal Ancillary Data Control Register
Ancillary Data ID Register
Subcarrier Frequency Byte 3 (MSBs)
Subcarrier Frequency Byte 2
Subcarrier Frequency Byte 1
Subcarrier Frequency Byte 0 (LSBs)
Subcarrier Phase Offset MSBs
Subcarrier Phase Offset LSBs
General Purpose Port
DDR
General Purpose Port Data Direction Control
Reserved
* double buffer registers; newly loaded FREQD-B’s values will not take effect until
FREQA has been updated.
Modified on May/04/2000
PAGE 26 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Part ID Register
Index
00h
01h
02h
Mnemonic
PIDC
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PID23
PID15
PID07
PID22
PID14
PID06
PID21
PID13
PID05
PID20
PID12
PID04
PID19
PID11
PID03
PID18
PID10
PID02
PID17
PID09
PID01
PID16
PID08
PID00
PIDB
PIDA
PID[23:00] Chip part ID number. This is a read only set of registers. The numbers contained in the registers
are:
PIDA = 79h
PIDB = 88h
PIDC = 91h.
Part Revision ID Number
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
REVID7
REVID6
REVID5
REVID4
REVID3
REVID2 REVID1
REVID0
03h
REVID
REVID
Chip revision ID number. This read only register is used to indicate the silicon revision level number.
Modified on May/04/2000
PAGE 27 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Global Control Register
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
4FSCS
GENEN
YCDLY
RMPEN
YCDIS
CDIS
FMT1
FMT0
04h
GCR
4FSCS
Subcarrier select.
1
0
SC_REF frequency equals 4 times color subcarrier frequency.
SC_REF frequency.*
GENEN
Genlock (to external reference) mode enable.
1
The encoder will lock its internal subcarrier synthesizer to an external reference subcarrier
input.
0
Normal operation.*
YCDLY
Luma to chroma delay. This may be used to compensate for luma and chroma group delay
variations of the external analog lowpass filter
1
0
The luminance signal is delayed by 37 nS relative to the chrominance signal.
Normal operation.*
RMPEN
YCDIS
CDIS
Modulated ramp enable.
1
0
The encoder outputs a modulated ramp for differential phase and gain measurements.
Normal operation.*
Y/C output disable.
1
0
The Y and C outputs are disabled, and in a high impedance state.
Normal operation.*
Composite output disable.
1
0
The CVBS output is disabled, and in a high impedance state.
Normal operation.*
FMT
Video format select. Note: the subcarrier frequency, pedestal level, and chroma bandwidth are
programmed individually and are independent of the format register.
00
01
10
11
NTSC.*
PAL-B,G,H,I,N(Argentina).
PAL-M.
reserved.
Modified on May/04/2000
PAGE 28 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Video Output Control Register
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CLMDIS CHRBW SYNDIS BURDIS LUMDIS CHRDIS PEDEN
05h
VOCR
CSDIS
CSDIS
Composite sync (COMPS) output disable. Control depends on the state of the DDR0 bit. See Table
6.
CLMDIS
CHRBW
Clamp gating signal (CLAMP) output disable.
Control depends on the state of the DDR1 bit. See Table 6.
Chroma bandwidth select.
1
0
Chrominance bandwidth is 1.3 MHz.
Chrominance bandwidth is 650 kHz.*
SYNDIS
Sync disable. When active, the horizontal and vertical sync pulses are disabled, and the encoder will
output blanking level during this time. Active video and color burst are not affected.
1
0
Disable active.
Normal operation.*
BURDIS
LUMDIS
CHRDIS
PEDEN
Chroma burst (color burst) disable. Chroma data at the output is not affected by this register.
1
0
The chroma reference burst output is disabled.
Normal operation, burst is enabled.*
Luminance input disable. Color burst and sync are not affected by this register.
1
0
Luminance data into the IC are forced to black level.
Normal operation. Incoming luminance data (Y) is enabled.*
Chroma input disable. The color burst output is not affected by this register.
1
0
Chroma data into the IC is suppressed, enabling monochrome operation.
Normal operation. Incoming chroma (C) data is enabled.*
Pedestal (setup) enable. When active, a 7.5 IRE (nominal) pedestal is inserted into the output video
for lines 23-262 and 286-525 only. The gain factors are adjusted to keep chrominance from
exceeding prescribed levels. Lines 1-22 and 263-285 don’t contain setup. This register is valid for
NTSC and PAL-M only.
1
0
Active (use only for NTSC and PAL-M).
Pedestal (setup) is disabled for all lines. The black and blanking levels are the same.*
Note: when SYNDIS=BURDIS=LUMDIS=CHRDIS=1, then the encoder outputs fixed DC at the blanking level.
Modified on May/04/2000
PAGE 29 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Horizontal Ancillary Data (HANC) Control Register
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Reserved NOLCK
FIELD2
FIELD1
FIELD0
AFREN
APHEN
ATMEN
06h
HANC
Reserved Reserved. Do Not Use.
NOLCK Genlock status. Read only. NOLCK is valid only when GENEN = 1.
1
0
Indicates that lock has not been achieved.
Indicates that the internal subcarrier synthesizer is locked to the external reference.*
FIELD2-0 Field identification number Read only. These 3 bits indicate the digital field number.
000
001
010
011
100
101
110
111
Field 1
Field 2
Field 3
Field 4
Field 5
Field 6
Field 7
Field 8
AFREN
APHEN
ATMEN
Ancillary frequency data enable. When GLKEN = 1 (genlock to external reference), the encoder may
assume that AFREN will be set to 0 by the firmware. In this case, the FREQ register value will be
controlled by the genlocking circuit.
1
The encoder programs the subcarrier FREQ register from the ancillary data stream
(depending on the state of the FRV bit).
0
The FREQ register is programmed through the microprocessor interface.*
Ancillary phase data enable. When GENEN = 1 (genlock to external reference), the encoder may
assume that APHEN will be set to 0 by the firmware. In this case, the PHASE register value will be
controlled by the genlocking circuit.
1
The encoder programs the subcarrier PHASE register from the ancillary data stream
(depending on the state of the PHV bit).
0
A value of 0 is used for the PHASE register.*
Ancillary timing reference data enable.
1
The encoder uses the timing reference data contained in the ancillary data stream (FIELD
and SVF/).
0
The ancillary timing reference data is ignored.*
Modified on May/04/2000
PAGE 30 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Ancillary Data ID Register
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ANCD7
ANCD6
ANCD5
ANCD4
ANCD3
ANCD2
ANCD1
PARITY
07h
ANCDID
ANCD[7:1] The seven bits, ANCD7 through ANCD1, determine the data ID. The encoder uses the data ID to
determine if the ancillary data it is receiving is meant for the encoder.
PARITY
Bit 0 is an odd parity bit for the ancillary data ID byte mentioned above. The encoder does not use
this bit.
Subcarrier Frequency Register
Index
08h
09h
0Ah
0Bh
Mnemonic
FREQD
FREQC
FREQB
FREQA
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
FRQ31
FRQ23
FRQ15
FRQ07
FRQ30
FRQ22
FRQ14
FRQ06
FRQ29
FRQ21
FRQ13
FRQ05
FRQ28
FRQ20
FRQ12
FRQ04
FRQ27
FRQ19
FRQ11
FRQ03
FRQ26
FRQ8
FRQ25
FRQ7
FRQ24
FRQ16
FRQ08
FRQ00
FRQ10
FRQ02
FRQ09
FRQ01
FRQ[31:00] These registers hold the 32 bit subcarrier frequency value. The FREQD-B registers are double
buffered; the newly loaded msb values will not take effect until the lsb (FREQA) has been written.
Subcarrier Phase Offset Register
Index
0Ch
0Dh
Mnemonic
SCHM
SCHL
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SCH15
SCH07
SCH14
SCH06
SPH13
SCH05
SCH12
SCH04
SCH11
SCH03
SCH10
SCH02
SCPH9
SCH01
SCPH8
SCH00
SPH[15:00] These registers hold the static subcarrier phase offset. This is used to adjust the phase of the
subcarrier relative to the 50% point of the leading edge of hsync (SCH phase). The nominal value
is 0. This register is used to compensate for delays external to the encoder.
Modified on May/04/2000
PAGE 31 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
General Purpose Port
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GPP7
GPP6
GPP5
GPP4
GPP3
GPP2
GPP1
GPP0
0Eh
GPP
GPP7 - GPP0
Registers GPP7 through GPP0 are used to read and write to I/O pins D0 through D7. The
direction of flow of these pins is set by the data direction register. Note that pins D7, D6,
D1, and D0 are shared with other signals.
GPP7 = D7 I/O Pin.
GPP6 = D6 I/O Pin.
GPP5 = D5 I/O Pin.
GPP4 = D4 I/O Pin.
GPP3 = D3 I/O Pin.
GPP2 = D2 I/O Pin.
GPP1 = D1 I/O Pin.
GPP0 = D0 I/O Pin.
General Purpose Port Data Direction Control
Index
Mnemonic
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DDR7
DDR6
DDR5
DDR4
DDR3
DDR2
DDR1
DDR0
0Fh
DDR
DDR7 - DDR0
Registers DDR7 through DDR0 are used to control the direction of data flow of I/O pins D0
through D7. Setting DDR(i) (where i = 7 to 0) to a low will make that pin an input. Setting
DDR(i) high will make that pin an output.
DDR7 = Data direction control for pin D7.
DDR6 = Data direction control for pin D6.
DDR5 = Data direction control for pin D5.
DDR4 = Data direction control for pin D4.
DDR3 = Data direction control for pin D3.
DDR2 = Data direction control for pin D2.
DDR1 = Data direction control for pin D1.
DDR0 = Data direction control for pin D0.
Modified on May/04/2000
PAGE 32 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Min
-0.5
Max
Unit
V
Supply Voltage (Measured to GND)
V
+7.0
DD
2
Digital Input Applied Voltage
V
GND-0.5
-100
V
V
+0.5
DD
V
I
I
3,4
Digital Input Forced Current
A
100
+0.5
mA
V
2
Digital Output Applied Voltage
V
GND-0.5
-100
O
O
DD
3,4
Digital Output Forced Current
A
100
mA
sec
sec
°C
°C
°C
°C
°C
°C
Digital Short Circuit Duration (single high output to VSS)
Analog Short Circuit Duration (single output to VSSA)
Ambient Operating Temperature Range
Storage Temperature Range
TD
TA
1
SC
infinite
+130
+150
+150
+300
+220
+150
SC
Ta
-60
-65
Tstg
Tj
Junction Temperature
Soldering Temperature (10 sec., 1/4” from pin)
Vapor Phase Soldering (1 min.)
Tsol
Tvsol
Storage Temperature
T
-65
stor
Notes: 1. Absolute maximum ratings are limiting values applied individually, while all other parameters are within
specified operating conditions. Functional operation under any of these conditions is NOT implied.
2. Applied voltage must be current limited to specified range, and measured with respect to VSS.
3. Forcing voltage must be limited to a specified range.
4. Current is specified as conventional current, flowing into the device.
RECOMMENDED OPERATING CONDITIONS
o
Unless otherwise specified, all specifications shall be met over the operating temperature range (0 to 70 C, case),
with a digital supply voltage (V ) of 5.00 VDC ± 5% and analog supply voltage (V
) of 5.00 VDC ± 5%.
DD
DDA
Characteristics
Supply Voltage
Ambient Operating Temperature Range
Symbol
Min
4.75
0
Typ
Max
5.25
70
Unit
V
V
5
DD
Ta
°C
Modified on May/04/2000
PAGE 33 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
DC ELECTRICAL CHARACTERISTICS
Characteristics
Symbol
Min
Typ
Max
Unit
Total Power Supply Current (Digital Plus
I
160
mA
DD
1
Analog , F
= 27 MHz)
PXCK
2
Total Power Supply Current (DACs Disabled ,
= 27 MHz)
I
110
mA
V
DDQ
F
PXCK
Digital Input Voltage, Logic HIGH
TTL Compatible Inputs
V
V
2.0
0.7
V
V
IH
IH
DD
DD
Digital Input Voltage, Logic HIGH
Serial Port (SDA, SCL)
V
Digital Input Voltage, Logic LOW
TTL Compatible Inputs
V
V
V
V
0.8
0.3
V
IL
IL
SS
SS
Digital Input Voltage, Logic LOW
Serial Port (SDA, SCL)
V
Digital Input Current, Logic HIGH (V = 4.0 V)
I
10
-10
7
mA
mA
pF
V
IN
IH
Digital Input Current, Logic LOW (V =0.4 V)
I
IL
IN
Digital Input Capacitance(f=1MHz,V =2.4 V)
C
IN
IN
Digital Output Voltage, Logic HIGH
V
3.7
V
DD
OH
CMOS Compatible Outputs (I =-1 mA)
OH
Digital Output Voltage Logic LOW
V
V
0.4
V
V
OL
SS
SS
SS
CMOS Compatible Outputs (I =4.0 mA)
OL
Digital Output Voltage Logic LOW
V
V
V
0.4
0.6
10
OL1
OL2
OZH
Serial Port (SDA) (I =3.0 mA)
OL
Digital Output Voltage Logic LOW
V
V
Serial Port (SDA) (I =6.0 mA)
OL
Hi-Z Leakage Current, HIGH (V =Max,
I
mA
mA
DD
V =V
)
IN
DD
Hi-Z Leakage Current, LOW (V =Max,
I
-10
DD
OZL
V =V
)
IN
SS
o
Digital Input Capacitance (T =25 C, F=1 MHz)
C
8
pF
pF
A
I
o
Digital Output Capacitance (T =25 C, F=1
C
10
A
O
MHz)
o
Notes: 1.Maximum I
and I
with V = V
= +5.25 VDC and T = 0 to 70 C. D/A converters loaded with
DDA A
DDD
DDA
DD
R = 75 W.
L
2. I
when RESET = HIGH, CDIS = YCDIS = HIGH (DACs disabled).
DDQ
Modified on May/04/2000
PAGE 34 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
PIXEL DATA PORT
Characteristics
Symbol
Min
Typ
27.0
13.5
18.5
18.5
Max
Unit
Master Clock Rate (PXCK input)
F
26.9999
27.0001
MHz
PXCK
Pixel Rate (F
= F
/2)
F
M
pps
PCK
PXCK
PCK
PWH;PXCK
PXCK Pulse Width, HIGH
PXCK Pulse Width, LOW
T
10
ns
T
14.5
ns
ns
ns
ns
ns
PWL;PXCK
PXCK Rise Time (10% to 90% points)
PXCK Fall Time (10% to 90% points)
PD7-0 Setup Time
T
TBD
TBD
RP
T
FP
T
T
5
3
SU;PD
HD;PD
PD7-0 Hold Time
Process Delay (from PD input to DAC inputs)
T
48
PXCX
PD
Periods
Note: Timing reference points are at the 50% level. Digital C
< 40 pF.
LOAD
Modified on May/04/2000
PAGE 35 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
SERIAL MICROPROCESSOR PORT
Characteristics
Symbol
Min
Typ
Max
Unit
kHz
ms
SCL Clock Frequency (F
SCL Clock LOW period
SCL Clock HIGH period
= 27.0 MHz)
F
T
Note 3
500
PXCK
SCL
1.0
LOW
HIGH
T
0.48
ms
SDA & SCL input rise time
SDA & SCL input fall time
SDA output fall time from V
T
T
240
240
200
ns
R
ns
F
to V
;
;
T
ns
IH MIN
IL MAX
OF1
OF2
BUF
bus capacitance = 10 pF to 400 pF.
Up to 3 mA current at V
OL1.
SDA output fall time from V
to V
T
200
ns
IH MIN
IL MAX
bus capacitance = 10 pF to 400 pF.
Up to 6 mA current at V
OL2.
Bus free time between a STOP and START
condition.
T
1.0
ms
ms
Hold time for START or repeated START
condition. After this period, the first clock pulse
is generated.
T
0.48
HD;STA
Setup time for a repeated START condition.
Data Setup Time
T
T
T
T
0.48
80
ms
ns
SU;STA
SU;DAT
HD;DAT
Data Hold Time
0
0.72
400
ms
ms
pF
Setup Time for a STOP condition
SDA output load capacitance
0.48
SU;STO
C
B
Note:
1. All timing values are referred to V
and V
levels.
IH MIN
IL MAX
2
2. Timing specifications have been obtained by scaling the Philips I C Fast Mode Bus specs by 80%.
3. The nominal F to be used by this device is: F = (F /56) = (27.0MHz/56) = 482.143 KHz.
SCL
SCL
PXCK
Modified on May/04/2000
PAGE 36 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
JTAG INTERFACE
Characteristics
Test Clock (TCK) Rate
Symbol
Min
Typ
Max
Unit
MHz
ns
F
10
TCK
TCK Pulse Width, LOW
T
10
10
10
0
PWLTCK
PWHTCK
TCK Pulse Width, HIGH
T
ns
Test Port Setup Time (TDI, TMS)
Test Port Hold Time (TDI, TMS)
Output Delay, TCK to TDO Valid
Output Hold Time, TCK to TDO Valid
T
T
ns
STP
ns
HTP
T
T
30
ns
DOTP
HOTP
5
ns
Note: Timing reference points are at the 50% level. Digital C
< 40 pF.
LOAD
MISCELLANEOUS DIGITAL SIGNALS
Characteristics
RESET/ Active (LOW) Time
Symbol
Min
Typ
Max
Unit
ms
ns
T
1
SR
SC_SYNC Setup Time
SC_SYNC Hold Time
PAL_ID Setup Time
PAL_ID Hold Time
PAL_ID Duration
T
T
10
0
SU;SC_SYNC
HD;SC_SYNC
ns
T
T
10
0
ns
SU;PAL_ID
HD;PAL_ID
ns
T
9
PXCK
DUR;PAL_ID
periods
Note: Timing reference points are at the 50% level. Digital C
< 40 pF.
LOAD
Modified on May/04/2000
PAGE 37 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
ANALOG (DAC) OUTPUTS
Characteristics
Symbol
RES
Min
10
Typ
Max
Unit
bits
dB
DAC Resolution
Power Supply Rejection Ratio (Full scale
output) CBYPS = 0.1mF, f = DC to 1MHz, V
= 100 mVp-p
PSRR
TBD
RIP
Voltage Reference Output
VREF Output Impedance
DAC Gain Factor
V
1.112
1000
10.31
-5
1.235
10.85
1.359
V
RO
Z
W
R
K
11.39
+5
DAC
K
Imbalance Between DACs
K
%
mA
W
DAC
IMBAL
DAC Reference Current (R
= Nom.)
I
1.569
787
REF
REF
Reference Resistor (V = Nom.)
R
REF
RO
Blanking Level Output Voltage (NTSC and PAL
modes)
V
0.300
V
BLANK
Video Output Compliance Voltage
Video Output Resistance
V
-0.3
1.6
V
OC
R
15
kW
pF
OUT
OUT
Video Output Capacitance (I
MHz)
=0 mA, f=1
C
15-25
OUT
Total Output Load Resistance
R
75
2
W
L
DAC Output Current Risetime (10% to 90% of
full scale)
T
ns
R
DAC Output Current Falltime (90% to 10% of
full scale)
T
2
ns
ns
F
Analog Output Delay
T
20
DOV
Notes: Timing reference points are at the 50% level. Analog C
< 10 pF Digital C
< 40 pF.
LOAD
LOAD
GENLOCK PERFORMANCE
Parameter
Locking Range
SC_REF Duty Cycle
Lock Time
Units
+2 kHz
50 + 10%
40 lines maximum
2 deg. p-p maximum
Jitter
Modified on May/04/2000
PAGE 38 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
Video Performance
The encoder meets the requirements listed in the table below when configured using the application circuit of
Figure 14. The test methods and test signals meet the requirements of NTC Report No. 7 or EIA/TIA-250. A
Tektronix TSG1001 Programmable TV Generator and a Tektronix VM700A Video Measurement Set are used for
measurement verification.
VIDEO PERFORMANCE CHARACTERISTICS
Test Name
Symbol
Test Waveform
Min
Typ Max
Unit
AMPRESP
Amplitude Response vs.
Frequency
Multiburst to 4.2 MHz
0.25 dBp-p
Differential Gain
DG
DP
Modulated Staircase or Ramp
(NTC-7 Composite)
1.5
% p-p
Differential Phase
Modulated Staircase or Ramp
(NTC-7 Composite)
1.0 deg p-p
Chroma Nonlinear Gain
Distortion
CNLG
CNLP
CLIMD
CLGI
Three Level Chroma Signal
(NTC-7 Combination)
1.0
1.0
IRE
deg
IRE
%
Chroma Nonlinear Phase
Distortion
Three Level Chroma Signal
(NTC-7 Combination)
Chroma-to-Luma
Intermodulation
Three Level Chroma Signal
(NTC-7 Combination)
1
Chroma/Luma Gain Equality
12.5T Modulated Pulse
(NTC-7 composite)
97.5
102.5
CHRBW = HIGH (1.3 MHz)
YCDELAY = LOW.
Chroma/Luma Delay Inequality.
(Analog filter delay excluded)
CLDI
12.5T Modulated Pulse NTC-7
composite)
0
5
ns
CHRBW = HIGH (1.3 MHz)
YCDELAY = LOW.
Luma Nonlinear Distortion
LNLD
5-Step Unmodulated Staircase
2.5
%
1
Noise Level
NOISE1 100% Unmodulated Ramp
NOISE2 100% Unmodulated Ramp
-61 dBrms
-72 dBrms
-56 dBrms
-58 dBrms
1.5 IREp-p
0.5 IREp-p
2
Noise Level
Chroma AM Noise
CAMN
CPMN
FTWD
LTWD
Red Field, 500 kHz BW
Red Field, 500 kHz BW
Field Square Wave
Chroma PM Noise
Field Time Waveform Distortion
Line Time Waveform Distortion
18 mS 100 IRE Bar (NTC-7
Composite)
Long Time Waveform Distortion:
Initial Peak Overshoot
LOTWD 10% / 90% APL Bounce
15
IRE
Peak Overshoot after 5 seconds
1.5
Modified on May/04/2000
PAGE 39 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
VIDEO PERFORMANCE CHARACTERISTICS
Test Name
Symbol
Test Waveform
Min
Typ Max
Unit
Short Time Waveform Distortion
STWD
100 IRE Step, 125 ns rise time
(NTC-7 COmposite)
1
% SD
Line-by-Line DC Offset
Dynamic Gain
LDCOFF 10% / 90% APL Bounce
DYNG
-1
-1
1
1
IRE
IRE
Notes: 1. Noise level is unified weighted, 10 kHz to 5.0 MHz bandwidth, with Tilt Null ON measuring using VM700
“Measure Mode”. A trap at the color burst frequency may be used.
2. Noise level is unified weighted, 10 kHz to 5.0 MHz bandwidth, measured using VM700 “Auto Mode”.
Modified on May/04/2000
PAGE 40 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
KS0123 Design Hints
Figure 19 describes power supply decoupling. A clean power supply is crucial for proper operation of the device.
Noise on the power supply lines will couple onto the analog inputs and ultimately result in poor picture quality. The
digital and analog VDD supplies should be separately decoupled with external filter components. This is achieved
by using a ferrite bead with a capacitor on either side. In addition to this filter, 0.1mF capacitors should be placed by
each IC power pin. Additional decoupling can be achieved by placing 0.01mF capacitors in parallel with the 0.1mF
capacitors. These components should be located close to the ENCODER device. The ENCODER ideally should be
located near the input power supply and close to the video inputs connectors.
Board Regulated
Power
+5V
VDD
0.1mF
22mF
22mF
22mF
0.1mF
FERRITE
ENCODER
BEADS
Place 0.1mF caps near
each IC power pin
VDDA
0.1mF
22mF
0.1mF
All Grounds are connected together
Figure 19. Power Supply Filtering
A number of different ferrite beads can be used for power supply decoupling. Wire wound ferrite beads are generally
large, but offer greater current capacity and higher impedance for a given frequency (this depends on the ferrite
material and number of windings). A larger current capacity is useful for decoupling many components, such as a
board power supply. Bead on lead and surface mount ferrites do not afford a large impedance to AC, but the
capacitors on each side of the ferrite should eliminate any excessive digital switching noise. Generally, pick a ferrite
with the lowest DC resistance and highest impedance to signals centered around 27 MHz. The large capacitor on
the component side of the ferrite provides low frequency filtering, and acts as a charge reservoir for rapid current
requirements by the ENCODER. Generally, this is located near the ferrite. Some suggested ferrite beads are:
• TDK: Wire wound ZBF113T-01; Bead on lead BF45-4001; Surface mount CB50-1206. TDK can be reached at
(708) 803-6100.
• Fair-Rite: Wire wound beads Fair-Rite 2943666671; Bead on lead 274300111; SM beads 2743021447. Fair-Rite
is at (914) 895-2055.
Applications that reside in noisy environments or utilize a switching power supply should have local power
regulation. For example, designs for the PC should use the 12 volt power supply and locally regulate the supply to
5 volts with a linear regulator.
For decoupling, use high quality RF capacitors. Type COG or NPO should be used. Avoid Z5U capacitors. Surface
mounting of the filter components is highly recommended. If leaded components are used, keep the leads and
traces as short as possible.
Use a multilayer PC board with separate power and ground planes. The surface mount package requires the top
layer to be a signal layer. The top layer should contain the analog traces, avoid running digital signal traces (clocks
and data lines) or other high speed lines directly under the device. The ground plane should be placed directly
Modified on May/04/2000
PAGE 41 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
below the top signal layer. A low impedance ground path from the device is essential to proper operation and
isolation. Use one solid ground plane under the ENCODER, do not split the ground plane. The power plane is next
with additional signal planes following. Surface mount passive components can be placed on the under side
(solder side) of the final signal plane. Mounting passive components (which could not be located close to the
ENCODER on the top signal layer) directly under the device should provide superior performance. A four layer PC
board is sufficient for most applications, but noisy densely populated designs may require more layers.
The output video connectors should be located close to the ENCODER. Orient the package so that short leads can
be used. The crystal oscillator components should also be mounted very close to the oscillator pins.
The edge rates of clocks and other high speed digital signals should be limited to reduce ringing and noise.
Termination with a small series damping resistor (~15 ohms, depends on trace and board characteristics), located
at the driving end of a long transmission line, may reduce ringing.
Modified on May/04/2000
PAGE 42 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
NOTES:
Modified on May/04/2000
PAGE 43 OF 44
MULTIMEDIA VIDEO
KS0123 Data Sheet
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NORTHEAST
NORTHWEST
NORTH CENTRAL
119 Russell Street
Littleton, MA 01460
TEL (508) 486-0700
FAX (508) 486-8209
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TEL (408) 954-7000
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FAX (714) 753-7544
TECHNICAL SUPPORT HOT LINE
Phone: (714)-236-9507
Fax: (714)-236-9664
E-mail: video@sldc.com
Circuit diagrams utilizing SAMSUNG and/or SAMSUNG ELECTRONICS products are included as a means of illustrating typical
semiconductor applications; consequently, complete information sufficient for construction purposes is not necessarily given.
The information has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for
inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described herein
any license under the patent rights of SAMSUNG and/or SAMSUNG ELECTRONICS, or others. SAMSUNG and/or SAMSUNG
ELECTRONICS, reserve the right to change device specifications.
LIFE SUPPORT APPLICATIONS
SAMSUNG and/or SAMSUNG ELECTRONICS products are not designed for use in life support applications, devices, or
systems where malfunction of a SAMSUNG product can reasonably be expected to result in a personal injury. SAMSUNG and/
or SAMSUNG ELECTRONICS’ customers using or selling SAMSUNG and/or SAMSUNG ELECTRONICS products for use in
such applications do so at their own risk and agree to fully indemnify SAMSUNG and/or SAMSUNG ELECTRONICS for any
damages resulting from such improper use or sale.
Modified on May/04/2000
PAGE 44 OF 44
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