KS0676_技术文档

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

November. 1999.

Ver. 0.1

Prepared by:

Yun-Hak, Koh

mail to: yhkoh1@samsung.co.kr

Contents in this document are subject to change without notice. No part of this document may be reproduced

or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express

written permission of LCD Driver IC Team.

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676 Specification Revision History

Content

Version

Date

0.0

0.1

Original

The contents of page 16 and 18 have been modified

Aug.1999

Nov.1999

2

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676

CONTENTS

INTRODUCTION ................................................................................................................................................. 4

FEATURES ......................................................................................................................................................... 4

BLOCK DIAGRAM .............................................................................................................................................. 5

PIN ASSIGNMENTS............................................................................................................................................ 6

PIN DESCRIPTIONS ........................................................................................................................................... 7

OPERATION DESCRIPTION............................................................................................................................... 8

DISPLAY DATA TRANSFER............................................................................................................................ 8

EXTENSION OF OUTPUT ............................................................................................................................... 8

RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE .................................................. 8

ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 15

RECOMMENDED OPERATION CONDITIONS.................................................................................................. 15

DC CHARACTERISTICS................................................................................................................................... 16

AC CHARACTERISTICS................................................................................................................................... 17

WAVEFORMS................................................................................................................................................... 18

RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD........................ 19

3

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

INTRODUCTION

The KS0676 is a 480 channel output, TFT LCD source driver for 64 gray scale displays. Data input is based on

digital input consisting of 6 bits by 6 dots, which can realize a full-color display of 260,000 colors by output of 64

values gamma-corrected.

This device has an internal D/A (Digital-to-Analog) converter for each output and 10 (5-by-2) external power

supplies. Because the output dynamic range is as large as 4.8 - 7.8 Vp-p, it is unnecessary to operate level

inversion of the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a

single-side, output gray scale voltages with different polarity can be output to the odd number output pins and the

even number output pins.

KS0676 can be adopted to larger panel, and SHL (shift direction selection) pin makes use of the LCD panel

connection convenient. Maximum operation clock frequency is 65 MHz at a 2.7 V logic operation. it can be applied

to the TFT-LCD panel of SXGA/UXGA standards.

FEATURES

·

TFT active matrix LCD source driver LSI

64 gray scale is possible through 10 (5 by 2) external power supply and D/A converter

Both dot inversion display and N-line inversion display are possible

CMOS level input

Compatible with gamma-correction

Input data inversion function (DATPOL1, 2)

Logic supply voltage: 2.7 - 3.6 V

LCD driver supply voltage: 5.0 - 8.0 V

Output dynamic range: 4.8 - 7.8 Vp-p

Maximum operating frequency: fMAX = 65 MHz (internal data transmission rate at 2.7 V operation)

Output: 480 outputs

TCP

4

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676

BLOCK DIAGRAM

RPO2 RPO1

Line Repair

Amp

Output Buffer

D/A Converter

Data Latch

RPI2

RPI1

POL

VGMA1 -

VGMA10

10

6

CLK1

DATPOL1

DATPOL2

Data Register

6

D00 - D05

D10 - D15

D20 - D25

D30 - D35

D40 - D45

D50 - D55

18

80 Bit Shift Register

SHL

TEST

DIO2

DIO1

CLK2

Figure 1. KS0676 Block Diagram

5

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

PIN ASSIGNMENTS

RPI1

RPO1

DIO1

D00

Y001

Y002

Y003

Y004

D01

D02

D03

D04

D05

D10

D11

D12

D13

D14

D15

D20

D21

D22

D23

D24

D25

TEST

DATPOL2

DATPOL1

POL

CLK1

CLK2

VSS1

VGMA1

VGMA2

VGMA3

VGMA4

VGMA5

VSS2

VDD2

VGMA6

VGMA7

VGMA8

VGMA9

VGMA10

SHL

VDD1

D30

D31

D32

D33

D34

D35

D40

D41

D42

D43

D44

D45

D50

D51

Y477

Y478

Y479

Y480

D52

D53

D54

D55

DIO2

RPO2

RPI2

Figure 2. KS0676 Pin Assignments

6

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676

PIN DESCRIPTIONS

Symbol

VDD1

Pin Name

Logic power supply

Driver power supply

Logic ground

Description

2.7 - 3.6 V

VDD2

5.0 - 8.0 V

VSS1

Ground (0 V)

VSS2

Driver ground

Y1 to Y480

Driver outputs

The D/A converted 64 gray-scale analog voltage is output.

D0<0:5>

- D5<0:5>

The display data is input with a width of 36 bits,

gray-scale data (6 bits) by 6 dots (R,G,B) DX0: LSB, DX5: MSB

Display data input

This pin controls the direction of shift register in cascade connection.

The shift direction of the shift registers is as follows.

SHL = H: DIO1 input, Y1 ® Y480, DIO2 output

Shift direction control

input

SHL

SHL = L: DIO2 input, Y480 ® Y1, DIO1 output

SHL = H: Used as the start pulse input pin.

SHL = L: Used as the start pulse output pin.

DIO1

DIO2

Start pulse input / output

SHL = H: Used as the start pulse output pin.

SHL = L: Used as the start pulse input pin.

DATPOL1, 2 = L: Display data is not inverted

DATPOL1 = H: Display data of D0<0:5> - D2<0:5> is inverted

DATPOL2 = H: Display data of D3<0:5> - D5<0:5> is inverted

DATPOL1

DATPOL2

Data inversion input

POL = H: The reference voltage for odd number outputs are VGMA1 –

VGMA5 and those for even number outputs are VGMA6 – VGMA10.

POL = L: The reference voltage for odd number outputs are VGMA6 –

VGMA10 and those for even number outputs are VGMA1 – VGMA5.

POL

Polarity input

Refer to the shift register's shift clock input. The display data is loaded

to the data register at the rising edge of CLK2.

CLK2

Shift clock input

Latches the contents of the data register at rising edge and transfers

them to the D/A converter. Also, after CLK1 input, clears the internal

shift register contents. After 1 pulse input on start, operates normally.

CLK1 input timing refers to the "Relationships between CLK1 start

pulse (DIO1, DIO2) and blanking period" of the switching characteristic

waveform. Outputs the G/S data at falling edge.

CLK1

Latch input

Input the gamma corrected power supplies from external source.

VDD2 > VGMA1 > VGMA2 > ¼ ¼ ¼ > VGMA9 > VGMA10 > VSS2

Keep gray-scale power supply unchanged during the gray-scale

voltage output.

VGMA1

–

VGMA10

Gamma corrected power

supplies

The Structure of the line-repair amp is the same as that of the analog

output.

RPI1 (RPI2) ® impedance changed ® RPO1 (RPO2)

RPI1, RPO1 Line-repair AMP input /

RPI2, RPO2

output

TEST = L: Normal operation mode

TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 15 kW)

TEST

Test input

7

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

OPERATION DESCRIPTION

DISPLAY DATA TRANSFER

When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse

enables the operation of data transfer, so data-display is valid on the next rising edge of CLK2. Once all the

data of 480 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data

is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is

provided, new data-display is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or DIO2).

EXTENSION OF OUTPUT

Output pin can be adjusted for an extended screen by cascade connection.

(1) SHL = "L"

Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins

except DIO1 and DIO2 are connected together in each device.

(2) SHL = "H"

Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins

except DIO2 and DIO1 are connected together in each device.

RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE

The LCD drive output voltages are determined by the input data and 10 (5 by 2) gamma corrected power

supplies (VGMA1 - VGMA10). Besides, to be able to deal with dot line inversion when mounted on a single-

side, gradation voltages with different polarity can be output to the odd number output pins and the even

number output pins. Among 5-by-2 gamma corrected voltages, 5 input gray-scale voltages have the same

polarity with respect to the common voltage, VGMA1 - VGMA5 and VGMA6 - VGMA10 respectively.

SHL = H

Y1

Y2

Y3

......

Y479

Last

D30 - D35 D40 - D45 D50 - D55

Y480

OUTPUT

Y478

First

D00 - D05 D10 - D15 D20 - D25

-

DATA

SHL = L

OUTPUT

-

Y1

Y2

Last

D00 - D05 D10 - D15 D20 - D25

Y3

......

Y479

First

D30 - D35 D40 - D45 D50 - D55

Y480

Y478

DATA

Figure 3. Relationship between Shift Direction and Output Data

8

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676

VDD2

VGMA1

VGMA2

VGMA3

VGMA4

VGMA5

VGMA6

VCOM

VGMA7

VGMA8

VGMA9

VGMA10

VSS2

00H

08H

10H

18H

20H

28H

30H

38H

3FH Input data

Figure 4. Gamma Correction Curve

9

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

Table 1. Resistor Strings (R0 - R62, unit: W)

Name

Value

500

450

400

370

Name

R16

R17

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

R31

Value

330

320

300

280

270

260

250

240

230

220

210

200

190

180

Name

R32

R33

R34

R35

R36

R37

R38

R39

R40

R41

R42

R43

R44

R45

R46

R47

Value

175

170

165

170

175

180

200

Name

R48

R49

R50

R51

R52

R53

R54

R55

R56

R57

R58

R59

R60

R61

R62

Value

210

220

230

240

250

260

270

290

300

310

320

340

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

10

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676

Table 2. Relationship between Input Data and Output Voltage Value

Input data

G/S

Output voltage

DX5 DX4 DX3 DX2 DX1 DX0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VGMA1

00H

01H

02H

03H

04H

05H

06H

07H

VH0

VH1

VH2

VH3

VH4

VH5

VH6

VH7

VGMA1 + (VGMA2 - VGMA1) ´ 500 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 1000 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 1500 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 2000 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 2500 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 3000 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 3500 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 4000 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 4500 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 5000 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 5500 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 6000 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 6450 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 6900 / 7670

VGMA1 + (VGMA2 - VGMA1) ´ 7300 / 7670

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

VH8

VH9

VH10

VH11

VH12

VH13

VH14

VH15

VGMA2

10H

11H

12H

13H

14H

15H

16H

17H

VH16

VH17

VH18

VH19

VH20

VH21

VH22

VH23

VGMA2 + (VGMA3 - VGMA2) ´ 330 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 660 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 990 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 1310 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 1610 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 1890 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 2160 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 2420 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 2670 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 2910 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 3140 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 3360 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 3570 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 3770 / 4140

VGMA2 + (VGMA3 - VGMA2) ´ 3960 / 4140

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

VH24

VH25

VH26

VH27

VH28

VH29

VH30

VH31

NOTE: VDD2 > VGMA1 > VGMA2 > VGMA3 > VGMA4 > VGMA5

11

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

Table 2. Relationship between Input Data and Output Voltage Value (Continued)

Input data

G/S

Output voltage

DX5 DX4 DX3 DX2 DX1 DX0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VGMA3

20H

21H

22H

23H

24H

25H

26H

27H

VH32

VH33

VH34

VH35

VH36

VH37

VH38

VH39

VGMA3 + (VGMA4 - VGMA3) ´ 175 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 350 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 520 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 690 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 855 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 020 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 1185 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 1350 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 1520 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 1690 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 1860 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 2035 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 2210 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 2385 / 2765

VGMA3 + (VGMA4 - VGMA3) ´ 2565 / 2765

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

VH40

VH41

VH42

VH43

VH44

VH45

VH46

VH47

VGMA4

30H

31H

32H

33H

34H

35H

36H

37H

VH48

VH49

VH50

VH51

VH52

VH53

VH54

VH55

VGMA4 + (VGMA5 - VGMA4) ´ 210 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 430 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 660 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 900 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 1150 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 1410 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 1680 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 1970 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 2270 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 2580 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 2900 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 3240 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 3580 / 4260

VGMA4 + (VGMA5 - VGMA4) ´ 3920 / 4260

VGMA5

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

VH56

VH57

VH58

VH59

VH60

VH61

VH62

VH63

12

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676

Table 2. Relationship between Input Data and Output Voltage Value (Continued)

Input data

G/S

Output voltage

DX5 DX4 DX3 DX2 DX1 DX0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VGMA10

00H

01H

02H

03H

04H

05H

06H

07H

VL0

VL1

VL2

VL3

VL4

VL5

VL6

VL7

VGMA10 + (VGMA9 - VGMA10) ´ 500 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 1000 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 1500 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 2000 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 2500 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 3000 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 3500 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 4000 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 4500 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 5000 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 5500 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 6000 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 6450 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 6900 / 7670

VGMA10 + (VGMA9 - VGMA10) ´ 7300 / 7670

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

VL8

VL9

VL10

VL11

VL12

VL13

VL14

VL15

VGMA9

10H

11H

12H

13H

14H

15H

16H

17H

VL16

VL17

VL18

VL19

VL20

VL21

VL22

VL23

VGMA9 + (VGMA8 - VGMA9) ´ 330 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 660 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 990 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 1310 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 1610 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 1890 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 2160 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 2420 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 2670 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 2910 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 3140 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 3360 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 3570 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 3770 / 4140

VGMA9 + (VGMA8 - VGMA9) ´ 3960 / 4140

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

VL24

VL25

VL26

VL27

VL28

VL29

VL30

VL31

NOTE: VGMA6 > VGMA7 > VGMA8 > VGMA9 > VGMA10 > VSS2

13

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

Table 2. Relationship between Input Data and Output Voltage Value (Continued)

Input data

G/S

Output voltage

DX5 DX4 DX3 DX2 DX1 DX0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VGMA8

20H

21H

22H

23H

24H

25H

26H

27H

VL32

VL33

VL34

VL35

VL36

VL37

VL38

VL39

VGMA8 + (VGMA7 - VGMA8) ´ 175 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 350 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 520 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 690 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 855 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 1020 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 1185 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 1350 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 1520 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 1690 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 1860 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 2035 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 2210 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 2385 / 2765

VGMA8 + (VGMA7 - VGMA8) ´ 2565 / 2765

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

VL40

VL41

VL42

VL43

VL44

VL45

VL46

VL47

VGMA7

30H

31H

32H

33H

34H

35H

36H

37H

VL48

VL49

VL50

VL51

VL52

VL53

VL54

VL55

VGMA7 + (VGMA6 - VGMA7) ´ 210 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 430 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 660 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 900 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 1150 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 1410 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 1680 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 1970 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 2270 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 2580 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 2900 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 3240 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 3580 / 4260

VGMA7 + (VGMA6 - VGMA7) ´ 3920 / 4260

VGMA6

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

VL56

VL57

VL58

VL59

VL60

VL61

VL62

VL63

14

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676

ABSOLUTE MAXIMUM RATINGS

Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V)

Parameter

Symbol

VDD1

Ratings

-0.3 to 5.0

Unit

V

Logic supply voltage

Driver supply voltage

VDD2

-0.3 to 9.0

V

VGMA1 - 10

RPI1, RPI2

Others

-0.3 to VDD2 + 0.3

-0.3 to VDD1 + 0.3

-0.3 to VDD2 + 0.3

150

Input voltage

V

DIO1, 2

Y1 to Y480

RPO1, RPO2

Pd

Output voltage

Operating power dissipation

Operation temperature

Storage temperature

mW

°C

Top

-20 to 75

Tstg

-55 to 125

°C

CAUTIONS:

If LSIs are stressed beyond those listed above “absolute maximum ratings”, they may be permanently

destroyed. These are stress ratings only, and functional operation of the device at these or any other

condition beyond those indicated under “recommended operating conditions” is not implied. Exposure to

absolute maximum rated conditions for extended periods may affect device reliability.

Turn-on power order: VDD1 ® control signal input ® VDD2 ® VGMA1 - VGMA10

or VDD1 & VDD2 ® control signal input & VGMA1 - VGMA10

Turn-off power order: VGMA1 - VGMA10 ® VDD2 ® control signal input ® VDD1

RECOMMENDED OPERATION CONDITIONS

Table 4. Recommended Operation Conditions (Ta = -20 to 75 °C, VSS1 = VSS2 = 0 V)

Parameter

Symbol

Min.

2.7

Typ.

Max.

3.6

Unit

Logic supply voltage

Driver supply voltage

VDD1

3.0

V

VDD2

5.0

7.0

8.0

V

VGMA1 - VGMA5

0.5 VDD2

VSS2 + 0.1

-

VDD2 - 0.1

0.5 VDD2

VDD2 - 0.1

65

Gamma corrected voltage

VGMA6 - VGMA10

V

Driver part output voltage

Maximum clock frequency

Output load capacitance

Vyo

fmax

CL

V

VDD1 = 2.7 V

MHz

pF/PIN

-

200

15

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

DC CHARACTERISTICS

Table 5 . DC Characteristics (Ta = -20 to 75 °C, VDD1 = 2.7 to 3.6 V, VDD2 = 5.0 to 8.0 V, VSS1 = VSS2 = 0 V)

Parameter

Symbol

VIH

Condition

Min.

Typ.

Max.

VDD1

0.2VDD1

1

Unit

V

High level input voltage

Low level input voltage

Input leakage current

0.8VDD1

-

SHL, CLK2, D00 - D55, CLK1,

POL, DATPOL1, DATPOL2,

DIO1 (DIO2)

VIL

0

IL

-1

mA

High level output

voltage

VOH

VOL

DIO1 (DIO2), IO = -1.0 mA

DIO1 (DIO2), IO = +1.0 mA

VDD1-0.5

-

V

Low level output

voltage

-

0.5

Refer to Table 1. Resistor

Strings

Resistor

R0 - R62

IVOH1

IVOL1

IVOH2

IVOL2

Rn ´ 0.7

-

Rn ´ 1.3

W

VDD2 = 8.0 V,

Vx = 2.5 V, Vyo = 7.5 V

-

-1.0

1.0

-3.0

3.0

-0.5

mA

Driver output current

VDD2 = 8.0 V,

Vx = 5.5 V, Vyo = 0.5 V

0.5

-

-1.5

-

VDD2 = 8.0 V,

Vx = 2.5 V, Vyo = 7.5 V

Line-repair Driver

output current

VDD2 = 8.0 V,

Vx = 5.5 V, Vyo = 0.5 V

1.5

VSS2 + 0.1 V ~ VDD2 - 1.5 V

VDD2 – 1.49 V ~ VDD2 – 0.1 V

VSS2 + 1.5 V ~ VDD2 - 1.5 V

-

±10

±15

±5

±20

±25

±15

Output voltage

deviation

DVO

mV

Output RMS voltage

deviation

dVrms⁽²⁾

mV

V

VSS2 + 0.1 V ~ VSS2 + 1.49 V

VDD2 – 1.49 V ~ VDD2 – 0.1 V

-

±15

±30

VDD2 - 0.1

6.5

Output voltage range

Vyo

Input data : 00H to 3FH

VDD1 = 3.0 V ⁽³⁾

VSS2 + 0.1

-

Logic part dynamic

current

IDD1

5.0

VDD1 = 3.0 V, VDD2 = 8.0 V,

VGMA1 = 7.5 V,

mA

Driver part dynamic

current

IDD2

VGMA5 = 4.5 V,

-

5.0

7.0

VGMA6 = 3.5 V,

VGMA10 = 0.5 V ^{(3) (4)}

NOTES:

1. Vyo is the output voltage of analog output pins Y1 to Y480. Vx is the voltage applied to analog output pins Y1 to Y480.

2. dVrms is a maximum deviation value from ideal difference between high output and low output at the same gray scale.

3. CLK1 period is defined to be 15.6 ms at fCLK2 = 54 MHz, data pattern = 10101010 (checkerboard pattern), Ta = 25 °C

4. The current consumption per driver when SXGA single-sided mounting (8 drivers) is connected in cascade

16

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676

AC CHARACTERISTICS

Table 6. AC Characteristics (Ta = -20 to 75 °C, VDD1 = 2.7 to 3.6 V , VDD2 = 5.0 to 8.0 V, VSS1 = VSS2 = 0 V)

Parameter

Symbol

PWCLK

Condition

-

Min.

15

5

Typ.

Max.

Unit

Clock pulse width

-

Clock pulse low period

Clock pulse high period

Data setup time

PWCLK(L)

PWCLK(H)

tSETUP1

tHOLD1

tSETUP2

tHOLD2

tSETUP4

tHOLD4

tPLH1

-

5

-

Refer to NOTE1

CL = 20pF

3

-

Data hold time

0

-

ns

Start pulse setup time

Start pulse hold time

DATPOL-CLK2 setup time

DATPOL-CLK2 hold time

Start pulse delay time

3

-

0

-

3

-

0

-

12

CLK2

period

CLK1 setup time

tSETUP3

-

1

-

Driver output delay time1

Driver output delay time2

CLK1 pulse high period

Data invalid period

Last data timing

tPHL1

tPHL2

Refer to NOTE2, 4

Refer to NOTE3, 4

-

5

10

-

ms

PWCLK1

tINV

0.2

-

1

-

DIO1 (2) • ® CLK2 •

-

CLK2

period

tLDT

1

6

5

-

CLK1-CLK2 time

tCLK1 - CLK2

tPOL - CLK1

-

ns

CLK1 • ® CLK2 •

POL • or ¯ ® CLK1 •

POL-CLK1 time

-

NOTES:

1. Input condition (VIH = 0.8 VDD1, VIL = 0.2 VDD1)

2. The value is specified when the drive voltage value reaches the target output voltage level of 90%

3. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy.

4. Yout Load Condition

10kW

20kW

YOUT

30pF

VCOM = 0.5VDD2

Figure 5. Yout Load Condition

17

KS0676

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

WAVEFORMS (VIH=0.8VDD1, VIL=0.2VDD1)

Figure 6. Waveforms

18

6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER

KS0676

RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND

BLANKING PERIOD

Figure 7. Waveforms

19


型号：	KS0676
厂家：	SAMSUNG
描述：	6 BIT 480 CHANNEL TFT-LCD SOURCE DRIVER 6位480沟道TFT -LCD源极驱动器显示驱动器驱动程序和接口接口集成电路 CD
文件：	总19页 (文件大小：190K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KS0676 [SAMSUNG]

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