KS1453 [SAMSUNG]
Consumer Circuit, PQFP128, QFP-128;
| 型号： | KS1453 |
| 厂家： | 
SAMSUNG |
| 描述： | Consumer Circuit, PQFP128, QFP-128 商用集成电路 |
| 文件： | 总73页 (文件大小：504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DVDP DATA PROCESSOR IC
KS1453
1
PRODUCT OVERVIEW
INTRODUCTION
128-QFP
KS1453 is a data processing IC that can operate in 1x DVDP or 4x CD (audio/
VCD) mode. It receives the sliced output (EFM signals) of the RF signal from the
disc and carries out data demodulation and error correction. It includes a buffer
control feature that allows the demodulated data to be continuously output in
hand shake mode.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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External plck input
EFM/EFMPLUS demodulator
Sync protection/insertion
CIRC/RS-PC error correction (4/16 erasure correction)
Cross/row deinterleave
4 - 16 Mbits DRAM interface (external component for error correction/track buffering)
Descramble
ID error correction
Main data error detection (EDC)
Error flag monitoring
MICOM interface
MICOM direct memory access feature (DVD/CD)
DSI detection and DSI data output
A/V decoder parallel interface
Built-in CD-DA decoder
Sub-code data serial output
Spindle servo control signal generation
DVD playback
CD/VCD playback
CLV/CAV feature
CD/VCD repeat correcting feature
Technology
- Application mode: CD_Player, CD_ROM, Video-CD, DVDP player
1
KS1453
DVDP DATA PROCESSOR IC
BLOCK DIAGRAM
Figure 1. Block Diagram
2
DVDP DATA PROCESSOR IC
KS1453
PIN CONFIGURATION
SDATA4_OUT
SDATA3_OUT
SDATA2_OUT
SDATA1_OUT
SDATA0_OUT
DVDD
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
RFCK_OUT
PLCK_IN
DVSS
PLLLOCK_OUT
CLVLOCK_OUT
SERLOCK_LOCK
MDP_OUT
MDS_OUT
DVSS
DATACK_OUT
TOS_OUT
DVSS
DVSS
DVSS
DADR3_OUT
DADR4_OUT
DADR2_OUT
DADR5_OUT
DADR1_OUT
DADR6_OUT
DADR0_OUT
DVSS
MON_OUT
FG_IN
FSW_OUT
EFMI_IN
KS1453
DVDD
DVDD
DVDD
CK16M_OUT
DEMPHA_OUT
TEST3_IN
DVSS
DADR7_OUT
DADR8_OUT
ZRAS_OUT
ZOE0_OUT
DVDD
ZRST_IN
ZWAIT_OUT
ZIRQZD_OUT
MRD_IN
ZOE1_OUT
ZWE0_OUT
ZWE1_OUT
MWR_IN
Figure 2. Pin Configuration
3
KS1453
DVDP DATA PROCESSOR IC
PIN DESCRIPTION
Table 1. Pin Description
Description
No
1
Pin Name
DVSS
I/O
Note
Digital GND (0V)
2
ZCS_IN
MRZA_IN
Chip select (active low), pull_up pin
I
I
MICOM
MICOM
3
MICOM register select, pull_up pin
(L ® register, H ® data)
4
DVSS
MDAT7_BI
MDAT6_BI
MDAT5_BI
MDAT4_BI
MDAT3_BI
MDAT2_BI
MDAT1_BI
MDAT0_BI
DVDD
Digital GND (0V)
MICOM data bus
MICOM data bus
MICOM data bus
MICOM data bus
MICOM data bus
MICOM data bus
MICOM data bus
MICOM data bus
Digital power (+5V)
System clock input for 26.16MHz
System clock output for 26.16MHz
Digital GND (0V)
DRAM data bus
5
B
B
B
B
B
B
B
B
MICOM
MICOM
MICOM
MICOM
MICOM
MICOM
MICOM
MICOM
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
XTI_IN
I
XTAL
XTAL
XTO_OUT
DVSS
O
DD15_BI
DD0_BI
B
B
B
B
DRAM
DRAM
DRAM
DRAM
DRAM data bus
DD14_BI
DD1_BI
DRAM data bus
DRAM data bus
DVSS
Digital GND (0V)
DRAM data bus
DD13_BI
DD2_BI
B
B
B
B
DRAM
DRAM
DRAM
DRAM
DRAM data bus
DD12_BI
DD3_BI
DRAM data bus
DRAM data bus
DVDD
DIGITAL power (+5V)
DRAM data bus
DD11_BI
DD4_BI
B
B
B
B
DRAM
DRAM
DRAM
DRAM
DRAM data bus
DD10_BI
DD5_BI
DRAM data bus
DRAM data bus
DVSS
DIGITAL GND (0V)
DRAM data bus
DD9_BI
B
B
B
B
DRAM
DRAM
DRAM
DRAM
DD6_BI
DRAM data bus
DD8_BI
DRAM data bus
DD7_BI
DRAM data bus
4
DVDP DATA PROCESSOR IC
KS1453
Table 1. Pin Description (Continued)
Description
No
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Pin Name
DVSS
I/O
Note
Digital GND (0V)
ZLCAS_OUT
ZUCAS_OUT
ZWE1_OUT
ZWE0_OUT
ZOE1_OUT
DVDD
DRAM low column address strobe
DRAM upper column address strobe
DRAM write enable 1 (8M only)
DRAM write enable 0 (4M, 8M, 16M)
DRAM output enable 1 (DADR9 in 16M mode)
Digital power (+5V)
O
O
O
O
O
DRAM
DRAM
DRAM
DRAM
DRAM
ZOE0_OUT
ZRAS_OUT
DADR8_OUT
DADR7_OUT
DVSS
DRAM output enable 0
O
O
O
O
DRAM
DRAM
DRAM
DRAM
DRAM row address strobe
DRAM address bus
DRAM address bus
Digital GND (0V)
DADR0_OUT
DADR6_OUT
DADR1_OUT
DADR5_OUT
DADR2_OUT
DADR4_OUT
DADR3_OUT
DVSS
DRAM address bus
O
O
O
O
O
O
O
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM
DRAM address bus
Address bus
DRAM address bus
DRAM address bus
DRAM address bus
DRAM address bus
Digital GND (0V)
DVSS
Digital GND (0V)
TOS_OUT
Top of sector
O
O
AV Decoder
AV Decoder
DATACK_OUT
DVDD
Data acknowledge signal output
Digital power (+5V)
SDATA0_OUT
SDATA1_OUT
SDATA2_OUT
SDATA3_OUT
SDATA4_OUT
SDATA5_OUT
SDATA6_OUT
SDATA7_BI
DVSS
DVD data/CD data bit stream (CDATA)
DVD data/CD data L/R clock (LRCK)
DVD data/CD data bit clock (BLCK)
DVD data/CD data error plug (C2PO)
DVD data/sub-code serial data (SQDT)
DVD data/sub-code frame sync (WFSY)
DVD data/sub-code block sync (S0S1)
DVD data/sub-code serial clock (SQCK)
Digital GND (0V)
O
O
O
O
O
O
O
B
AV Decoder
AV Decoder
AV Decoder
AV Decoder
AV Decoder
AV Decoder
AV Decoder
AV Decoder
CSTROBE_OUT Data strobe (clock) output
O
I
AV Decoder
AV Decoder
AV Decoder
DATREQ_IN
DTER_OUT
DVSS
Data request from A/V decoder or ROM Ecuador
DVD data error output
Digital GND (0V)
O
5
KS1453
DVDP DATA PROCESSOR IC
Table 1. Pin Description (Continued)
Description
No
73
Pin Name
PWMO7_OUT
PWMO6_OUT
PWMO5_OUT
PWMO4_OUT
DVDD
I/O
O
Note
RF
PWM output signal
74
PWM output signal
O
RF
75
PWM output signal
O
RF
76
PWM output signal
O
RF
77
Digital power (+5V)
78
PWMO3_OUT
PWMO2_OUT
PWMO1_OUT
PWMO0_OUT
DVSS
PWM output signal
O
O
O
O
RF
RF
RF
RF
79
PWM output signal
80
PWM output signal
81
PWM output signal
82
Digital GND (0V)
83
DVSS
Digital GND (0V)
84
DVSS
Digital GND (0V)
85
DVDD
Digital power (+5V)
86
DVDD
Digital power (+5V)
87
DVSS
Digital GND (0V)
88
DVSS
Digital GND (0V)
89
DVSS
Digital GND (0V)
90
DVSS
Digital GND (0V)
91
FRSYZ_OUT
TX_OUT
Frame sync out
O
O
O
Monitor
Monitor
Monitor
92
Digital out (3-state)
93
GFS_OUT
DVSS
Good frame sync detection status output (OK at H)
Digital GND (0V)
94
95
CK33MI_IN
CK33MO_OUT
DVDD
System clock input for 33.8688MHz
System clock output for 33.8688MHz
Digital power (+5V)
I
XTAL
XTAL
96
O
97
98
TEST0_IN
TEST1_IN
TEST2_IN
EFMO_OUT
WFCK_OUT
RFCK_OUT
PLCK_IN
DVSS
Test mode select signal, pull_down pin
Test mode select signal, pull_down pin
Test mode select signal, pull_down pin
EFM out
I
I
99
100
101
102
103
104
105
106
107
108
109
I
O
O
O
I
Monitor
Monitor
Monitor
Servo
Write frame pulse
Reference frame pulse
Phase locked clock
Digital GND (0V)
PLLLOCK_OUT Lock signal for pll
CLVLOCK_OUT Lock signal for CLV
SERLOCK_OUT Lock signal for servo
O
O
O
O
Servo
Monitor
Servo
MDP_OUT
Spindle motor phase control signal (3-state)
Servo
6
DVDP DATA PROCESSOR IC
KS1453
Table 1. Pin Description (Continued)
No
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Pin Name
MDS_OUT
DVSS
Description
Spindle motor speed control signal (3-state)
Digital GND (0V)
I/O
Note
O
Servo
DVSS
Digital GND (0V)
MON_OUT
FG_IN
Spindle motor on/off control output
Reference signal for CAV
O
I
Servo
Servo
Servo
Servo
FSW_OUT
EFMI_IN
DVDD
Spindle motor output filter conversion output (3-state)
EFM/EFM + signal input
O
I
Digital power (+5V)
DVDD
Digital power (+5V)
DVDD
Digital power (+5V)
CK16M_OUT
DEMPHA_OUT
TEST3_IN
DVSS
CK33M's 1/2 clock/16.9344MHz
Deemphasis on when “high”
O
O
I
Monitor
Monitor
Test mode select signal, pull_down in
Digital GND (0V)
ZRST_IN
ZWAIT_OUT
ZIRQZD_OUT
MRD_IN
Hardware reset (active low) pull_up pin
MICOM read/write access wait (wait at L)
Interrupt request to MICOM
I
O
O
I
MICOM
MICOM
MICOM
MICOM
MICOM
MICOM read strobe (active low) pull_up pin
MICOM write strobe (active low) pull_up pin
MWR_IN
I
7
KS1453
DVDP DATA PROCESSOR IC
2
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(VDD = 5.0V ± 5%, VSS = 0V, Ta = 0 - +70°C)
Item
Conditions
Min
Max
Unit
Note
Input voltage
Input voltage
“H” level
VIH
VIL
-
0.7VDD
-
V
1
Input voltage
“L” level
-
-
0.3VDD
VDD
0.4
V
V
Output voltage Output voltage
“H” level
VOH
VOL
IIH1
IIL1
IOH = -2, -4mA
IOL = 2, 4mA
Vin = VDD
2.4
0
2
3
4
Output voltage
“L” level
V
Input voltage
Input voltage
Input voltage
“H” level
-10
-10
10
10
mA
mA
mA
Input voltage
“L” level
Vin = VSS
10
Input voltage
“H” level
IIH2
Vin = VDD
100
Input voltage
“L” level
IIL2
Vin = VSS
-100
-10
-10
10
mA
mA
5
1
Input current leak
I
VI = 0 - 5.25V
LI
NOTES:
1. All CMOS input signals, BIDIR PAD's input mode signals
2. All output signals
3. All CMOS input signals, BIDIR PAD's input mode signals
4. All input signals with pull-down
5. All input signals with pull-up
8
DVDP DATA PROCESSOR IC
KS1453
ABSOLUTE MAXIMUM RATINGS
No
1
Item
Symbol
Vin
Spec
-0.3 - VDD + 0.3
-0.3 - +7.0
10
Unit
V
DC input voltage
C supply voltage
C input current
2
VDDmax
Lin
V
3
mA
°C
4
Storage temperature
Tstg
-40 - 125
RECOMMENDED OPERATING CONDITIONS
No
1
Item
Operating temperature
DC supply voltage
Symbol
Topr
Spec
0 - 70
Unit
2
VDD
4.75 - 5.25
V
9
KS1453
DVDP DATA PROCESSOR IC
3
BLCOK CHARACTERISTICS
ECC FEATURE
Euclid's algorithm used.
Same circuit used for DVD and CD.
DVD (PRIMITIVE POLYNOMIAL: X8 + X4 + X3 + X2 + 1)
: Error correcting ability for DVD data.
®
®
PI (182, 172, 11) code: 5 error correct/10 errata correct
PO (208, 192, 17) code: 8 error correct/16 errata correct
38.8688MHz clock: 1X operation (PI+PO+PI)/1 EFM block satisfaction ® basic operation
CD (PRIMITIVE POLYNOMIAL: X8 + X4 + X3 + X2 + 1)
®
®
C1 (32, 28, 5) code: 2 error correct
C2 (28, 24, 4) code: 2 error correct/4 errata correct
Repeat correction carried at for video-CD (C1 ® C2 ® C1 ® C2)
10
DVDP DATA PROCESSOR IC
KS1453
MEMORY CONTROL FEATURE
CD data processor and DVD data processor has an external 4M or 8M DRAM in common.
EFM data write, ECC data R/W, descrambler R/W, and transfer read addressing feature.
DVD
•
•
•
•
•
•
•
•
33.8688MHz crystal clock used.
Continuous storage according to input order regardless of data format (PO deinterleave).
13 ECC block areas guaranteed in 4M bit DRAM. (EFM, ECC, descrambler, and transfer cyclically processed)
MICOM user area guaranteed (can use blocks 1 - 8 selectively in units of ECC blocks)
EFM data Write in units of sectors.
Data transfer in units of sectors.
Block copy feature (sector number selection possible)
MICOM direct access on DRAM
External 4M bit DRAM
DRAM Control
EFM
- ECCMEM
- DVDMEM
- CDMEM
Dscramble & EDC
EFM + Demodulator
MICOM
ECC
Transfer
Figure 3. Block Diagram of Memory Control
CD
•
•
•
•
•
•
•
CD-DA, CD-ROM, V-CD: 33.8688MHz crystal clock used.
Video-CD: Repeat correction possible.
8Kbyte memory area used.
EF M, ECC, transfer feature.
EFM: referenced by WFCK.
ECC, transfer: referenced by RFCK.
MICOM direct access on DRAM.
11
KS1453
DVDP DATA PROCESSOR IC
DESCRAMBLER & EDC & TRANSFER FEATURE
•
•
•
•
•
•
•
Descramble on/off control possible in MICOM
EDC flag output to MICOM
2048-byte or 2064-byte output selection possible
Transfer sector number selection possible
Maximum transfer rate: 5.4MBytes/s.
Parallel synchronous I/F support
Request, TOS, ACK, DATCLK, and EDCFLG'S active “L/H” selection possible.
DRAM Data
DRAM
Descrambler
Descramble Data
DRAM Control Signal
EDCFLG
EDC & Built-in
SRAM
Transmission
Address Generator
Transmission
Enable Signal
Data Transmitter
REQ, TOS, ACK, DATCLK with CSS
MICOM Setting
Value
MICOM I/F
Figure 4. Block Diagram of the Transfer Part
12
DVDP DATA PROCESSOR IC
KS1453
CD AUDIO FEATURE
Receives data that has been completely corrected of errors in units of byte, and outputs it serially.
Interpolation, mute, and attenuation carried out for CD-DA.
SUBCODE I/F FEATURE
CD graphic processing subcode data (P, Q, R, S, T, U, V, W) is serially output.
Errors existing in the disc controlling subcode data (Q) are checked and output.
(p(x) = x16 + x12 + x5 + 1)
MICOM I/F FEATURE
Address/command data: 1byte
Write register access
: CS enable ® W_reg address write ® Command data write ® CS disable
Read register access
: CS enable ® R_reg address write ® R_reg data read ® CS disable
EFM DEMODULATOR FEATURE
CD player, CD-ROM, and DVD player mode
Demodulator
: EFM + demodulation (DVD)
EFM demodulation (CD)
ID sync, frame sync detection/protection/insertion
: 4 step ID sync/frame sync protection window section select
4 step ID sync/ frame sync insertion frame number select
SID error correction
ID (frame) sync continuous check
13
KS1453
DVDP DATA PROCESSOR IC
4
MICOM REGISTER
MICOM WRITE REGISTER & READ/WRITE REGISTER
Table 2. MICOM Write Register & Read/Write Register Table (R/W unmarked; W)
Name
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RESERVED (00 - 09)
INTCTL1
0A
0B
0C
0D
0E
OF
10
DVDIEN
SBQIEN
-
DSIEN
TOSEN
TSCMPEN
ECCIEN
-
EMPTYEN OVEREN
UNDEREN
-
INTCTL2
MCPEN
-
-
-
-
INTCTL3
-
-
IFRQ2
RCF1
ISPROT
IFRQ1
RCF0
IFRQ0
-
CLRINT
DISC0
-
SYSCONT1
USER1CON
USER2CON
DVDDSET
MRESET
WIDEWIN
ABTH7
-
-
-
DISC2
DISC1
-
GFSPRO
ABTH6
-
SYNCDEC
ABTH5
FWSEL1
-
FNADJ
ABTH3
FGSEL1
INSEN
RFNCON
ABTH2
FGSEL0
WNDEN
AB
TH4
ABTH1
IGSEL1
WNDRT
ABTH0
IGSEL0
FCLDS
FWSEL0
-
DVDCONTR
OL1
11
DSCREN
STRST
DVDCONTR
OL2
12
13
14
15
16
WRST
PGAIN1
MDSCON1
FALTHR1
SDWP
TRST
PGAIN0
MDSCON0
FALTHR1
SDWB
ECCST
SGAIN1
PLLC1
RISTHR1
-
ECNEGLT
SGAIN0
PLLC0
RISTHR0
-
ECMOD2
ECMOD1
-
ECMOD0
-
MCPST
-
CLVCONTR
OL1
-
CLVCONTR
OL2
-
MDPC
SERVOC
SDCM2
P_RES1
CLVC1
SDCM1
P_RES0
CLVC0
SDCM0
CLVCONTR
OL3
REFSEL
SDCM3
CLVMODE
RESERVED (17 - 18)
TRMODE
19
1A
1B
1C
IFMOD2
IFMOD1
IFMOD0
-
CDIF0
-
DRATE
CDSPD2
MUTE
-
DVDIF0
CDSPD0
ATTN
CDSPEED
CDMUTCNT
-
-
-
-
CDSPD1
ZCMT
CBITIN2
-
CBITIN1
-
CBITIN0
-
DGOEN
-
DEMPHA
BYPASS
CDCONTR
OL
INFR
T3_SEL
T3_MODE
ECCREG1
ECCREG2
ECCREG3
1D
1E
1F
ERAMODF
ERAMODL maxmode2f maxmode2l
c2eccf
c2eccl
c2err
onlyf
c2err
onlyl
-
-
cdecc
-
eccmode
-
c2fgtype
[4]
c2fgtype
[3]
c2fgtype
[2]
c2fgtype
[1]
c2fgtype
[0]
-
SETFLG
[3]
SETFLG
[2]
SETFLG
[1]
SETFLG
[0]
Address Setting on MICOM Direct Access Buffer Mode (Read/Write)
WADRH
WADRM
WADRL
20
21
22
-
-
-
ADR20
ADR12
ADR4
ADR19
ADR11
ADR3
ADR18
ADR10
ADR2
ADR17
ADR9
ADR1
ADR16
ADR8
ADR0
ADR15
ADR7
ADR14
ADR6
ADR13
ADR5
Data Write to Buffer (When MDAB = 1)
14
DVDP DATA PROCESSOR IC
KS1453
Table 2. MICOM Write Register & Read/Write Register Table (R/W unmarked; W) (Continued)
Name
WDATA
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
23
WDT7
WDT6
WDT5
WDT4
WDT3
WDT2
WDT1
WDT0
RESERVED (24 - 2F)
Buffering Start Sector Unit Number
WBAH
WBAL
30
31
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
ECC Start Block Unit Number
WEAH
WEAL
32
33
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
Transfer Start Sector Unit Number
WTAH
WTAL
34
35
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
Over Threshold Size (Number of Sector Units) (Read/Write)
OTSH
OTSL
36
37
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
Under Threshold Size (Number of Sector Units) (Read/Write)
UTSH
UTSL
38
39
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
Number of Transfer Sectors select (Read/Write)
TNH
TNL
3A
3B
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B9
B1
B8
B0
Size of Buffer for MICOM use select (Read/Write)
B3
Decoder Direct Data Block Copy Source Sector Address select
MBS
3C
-
-
-
-
B2
B1
B0
BCPSH
BCPSL
3D
3E
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
Reserved (3F)
Decoder Direct Data Block Copy Target Sector Address select
BCPTH
BCPTL
40
41
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
Descramble Start Sector Unit Number
WDAH
WDAL
42
43
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
15
KS1453
DVDP DATA PROCESSOR IC
Table 2. MICOM Write Register & Read/Write Register Table (R/W unmarked; W) (Continued)
Name
Address
Bit7
Bit6
Bit5
RESERVED (44 - 49)
RESERVED (A0 - A7)
TSTWRD ECTEST
RESERVED (A9)
Bit4
Bit3
Bit2
Bit1
Bit0
USERREG
A8
AA
-
-
-
-
-
-
MONITOR3 MONITOR2 MONITOR1 MONITOR0
MPRSTZ TSTENDM TSTPORE TSTPIREN
UX
ND
D
RESERVED (AB - AD)
AE
REGEG
ACKEG
STREG
TOSEG
DTREG
-
TSTID
TSTIDSY
RESERVED (AF - BF)
C0
C1
C2
C3
C4
C5
C6
C7
C8
PWM07
PWM17
PWM27
PWM37
PWM47
PWM57
PWM67
PWM77
PWM06
PWM16
PWM26
PWM36
PWM46
PWM56
PWM66
PWM76
PWM05
PWM04
PWM14
PWM24
PWM34
PWM44
PWM54
PWM64
PWM74
-
PWM03
PWM13
PWM23
PWM33
PWM43
PWM53
PWM63
PWM73
-
PWM02
PWM12
PWM22
PWM32
PWM42
PWM52
PWM62
PWM72
PWM01
PWM11
PWM21
PWM31
PWM41
PWM51
PWM61
PWM71
PWM00
PWM10
PWM20
PWM30
PWM40
PWM50
PWM60
PWM70
PWM15
PWM25
PWM35
PWM45
PWM55
PWM65
PWM75
-
CAVCKSEL CAVCKSEL
CAVVAL
10
CAVVAL
9
CAVVAL
8
1
0
C9
CAVVAL7
CAVVAL6
CAVVAL5
CAVVAL4
CAVVAL3 CAVVAL2 CAVVAL1
CAVVAL0
RESERVED (CA - DF)
RESERVED (E0 - EF)
16
DVDP DATA PROCESSOR IC
KS1453
MICOM READ REGISTER & READ/WRITE REGISTER
Table 3. MICOM Read Register & Read/Write Register Table (R/W unmarked; R)
Name
INTSTAT1
Address
4A
Bit7
DVDSINT
SBQINT
EIDERR
-
Bit6
DSINT
MCPINT
DSIERR
-
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TOSINT
TRSCMPLT ECCMPLT EMPTY
OVER
UNDER
INTSTAT2
4B
-
-
-
-
-
-
-
-
-
ERRSTAT
4C
IDCONERR
ECCERR EDCFLG
-
ILSY
-
SBQERR
DVDSTATUS
DVDSVSTAT
4D
-
GFS
SYOK
-
NOSY
-
-
-
4E
-
LOCK
RESERVED (4F)
SBQ77
¯
CDSUBQ
50
¯
SBQ79
¯
SBQ78
¯
SBQ76
¯
SBQ75
¯
SBQ74
¯
SBQ73
¯
SBQ72
¯
59
SBQ07
SBQ06
SBQ05
SBQ04
SBQ03
SBQ02
SBQ01
SBQ00
RESERVED (5A - 5F)
SEEKIDADR
TRANSIDADR
60
61
62
63
64
65
66
67
SID31
SID23
SID15
SID07
TID31
TID23
TID15
TID07
SID30
SID29
SID21
SID28
SID20
SID12
SID04
TID28
TID20
TID12
TID04
SID27
SID19
SID11
SID03
TID27
TID19
TID11
TID03
SID26
SID18
SID10
SID02
TID26
TID18
TID10
TID02
SID25
SID17
SID09
SID01
TID25
TID17
TID09
TID01
SID24
SID16
SID08
SID00
TID24
TID16
TID08
TID00
SID22
SID14
SID06
TID30
TID22
TID14
TID06
SID13
SID05
TID29
TID21
TID13
TID05
RESERVED (68 - 6F)
Address Reading on Micom Direct Access Buffer Mode (Read/Write)
RADRH
RADRM
RADRL
70
71
72
-
-
-
ADR20
ADR12
ADR4
ADR19
ADR11
ADR3
ADR18
ADR10
ADR2
ADR17
ADR9
ADR1
ADR16
ADR8
ADR0
ADR15
ADR7
ADR14
ADR6
ADR13
ADR5
Data Read from Buffer
RDATA
73
RDT7
RDT6
RDT5
RDT4
RDT3
RDT2
RDT1
RDT0
RESERVED (74 - 7F)
Buffering End Sector Unit Number
RWAH
RWAL
80
81
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
ECC End Sector Unit Number
REAH
REAL
82
83
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
Transferring End Sector Unit Number
RTAH
RTAL
84
85
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
DSI Unit Number
DSIH
DSIL
86
87
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
Descramble End Sector Unit Number
RDAH
RDAL
88
89
-
-
-
-
-
-
B9
B1
B8
B0
B7
B6
B5
B4
B3
B2
17
KS1453
DVDP DATA PROCESSOR IC
Table 3. MICOM Read Register & Read/Write Register Table (R/W unmarked; R) (Continued)
Name
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RESERVED (8A - 93)
ECC End ID Address
EEIDA
94
95
96
97
ID31
ID23
ID15
ID07
ID30
ID22
ID14
ID06
ID29
ID28
ID20
ID12
ID04
ID27
ID19
ID11
ID03
ID26
ID18
ID10
ID02
ID25
ID17
ID09
ID01
ID24
ID16
ID08
ID00
ID21
ID13
ID05
RESERVED (98 - 9B)
DSI ID Address
DSIDA
9C
9D
9E
9F
ID31
ID23
ID15
ID07
ID30
ID22
ID14
ID06
ID29
ID21
ID13
ID05
ID28
ID20
ID12
ID04
ID27
ID19
ID11
ID03
ID26
ID18
ID10
ID02
ID25
ID17
ID09
ID01
ID24
ID16
ID08
ID00
Remaining Data Size (Number of Sector Units)
RDSH
RDSL
F0
F1
-
-
-
B5
-
--
-
B9
B1
B8
B0
B7
B6
B4
B3
B2
RESERVED (F2 - FF)
18
DVDP DATA PROCESSOR IC
KS1453
MICOM REGISTER DESCRIPTION
MICOM WRITE REGISTER & READ/WRITE REGISTER (R/W UNMARKED; W)
INTCTL1: Interrupt Control Register 1
Address
0A
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DVDIEN DSIEN TOSEN TSCMPTEN ECCIEN EMPTYEN OVEREN UNDEREN
Reset Value
0
0
0
0
0
0
0
0
< DVD Interrupt Masking Register >
•
DVDIEN: DVD ID-sync interrupt request enable
Enable/Disable control bit of the ID-sync Interrupt generated in the DVD decoder.
1: Enable 0: Disable
•
•
DSIEN: DSI interrupt
1: Enable
0: Disable
TOSEN: Top of sector interrupt request enable
Enable/Disable control bit of the interrupt that marks the first data in the sector being transferred from the DVD
decoder to the A/V decoder or host.
1: Enable 0: Disable
•
•
TSCMPTEN: Transfer complete interrupt request enable
Control bit for Interrupt signal generation when transfer is complete for the number of bytes demanded in DVD
ROM application (TNH, L).
1: Enable 0: Disable
ECCIEN: ECC complete interrupt request enable
Enable/Disable control bit of the ECC complete interrupt generated in the DVD decoder.
1: Enable 0: Disable
•
•
EMPTYEN: Buffer memory empty interrupt (for transfer) request enable
1: Enable 0: Disable
OVEREN: Buffer memory over interrupt request enable
Interrupt request enable generated when the filled area in the buffer memory is more than the over threshold
size (OTS) set by MICOM (hysteresis).
1: Enable
0: Disable
•
UNDEREN: Buffer memory under interrupt request enable
Interrupt request enable generated when the filled area in the buffer memory is less than the under threshold
size set by MICOM (hysteresis).
1: Enable
0: Disable
19
KS1453
DVDP DATA PROCESSOR IC
INTCTL2: Interrupt Control Register 2
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0B
SBQIEN MCPEN
-
-
-
-
-
-
-
-
-
-
-
-
Reset Value
0
0
< CD interrupt Masking Register >
•
SBQIEN: CD subcode-sync interrupt request enable
Enable/Disable control bit for subcode-sync interrupt generated in the CD decoder.
1: Enable 0: Disable
•
MCPEN: Micom block copy mode
1: Enable 0: Disable
INTCTL3: Interrupt Control Register 3
Address
0C
Reset Value
Bit7
Bit6
Bit5
Bit4
IFRQ2
0
Bit3
IFRQ1
0
Bit2
IFRQ0
0
Bit1
Bit0
CLRINT
1
-
-
-
-
-
-
-
-
•
IFRQ2 - 0: Interrupt request frequency select register (only applicable to DVDSINT)
IFRQ2
IFRQ1
IFRQ0
Number of Interrupts/Number of ID Sectors
1/1 ID sector
0
0
0
0
1
0
0
1
0
1
0
0
1/2 ID sectors
1
1
1/4 ID sectors
1/8 ID sectors
0
1/16 ID sectors
Other
Reserved
•
CLRINT: Interrupt clear register
Decides whether or not to clear the interrupt status register after MICOM has read it.
1: Clear 0: Don't clear
20
DVDP DATA PROCESSOR IC
KS1453
SYSCONT1: System Control Register 1
Address
0D
Bit7
Bit6
Bit5
Bit4
RCF1
0
Bit3
RCF0
0
Bit2
DISC2
1
Bit1
DISC1
0
Bit0
DISC0
0
MRESET
1
-
-
-
-
Reset Value
•
•
MRESET: Master reset ® reset Z-decoder.
(Setting all registers to predefined reset value. Same as ZRST) the decoder automatically sets to "1" after
MICOM turns on the reset.
0: Reset on, 1: Reset off
RCF1 - 0: RAM configuration ® buffer size select.
RCF1
RCF0
DRAM Configuration
0
0
1
1
0
1
0
1
4Mbits
8Mbits
N.A
16Mbits
•
Z-Decoder control register.
DISC2 - 0: Shows the operating disc type.
DISC2
DISC1
DISC0
Disc Type
1
1
0
0
0
0
0
0
0
1
0
DVD
DVD-ROM
CD-DA
1
0
0
V-CD
1
CD-ROM
Reserved
Other
21
KS1453
DVDP DATA PROCESSOR IC
USERCONT1: User Control Register1 (Sync Control)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
WIDEWIN GFSPRO SYNCDEC ISPROT FNADJ RFNCON
Address
Bit1
Bit0
0E
-
-
-
-
Reset Value
1
1
1
0
1
1
•
WIDEWIN: Sync protection window control
H ® If frame sync doesn't occur for more than the insertion number (N) designated by the protection window,
again set the widest protection window for sync detection. If sync is detected, immediately correct to that
value and protect to the window with the selected width. If sync isn't detected, immediately cancel
window.
L ® Find sync by immediately cancelling the protection window without wide window operating mode.
•
•
•
GFSPRO: Good frame sync detecting conditions
H ® Complete match between detected sync and inserted sync
L ® A ±1 difference between detected sync and inserted sync
SYNCDEC: Frame sync detecting conditions
H ® Sync detect by sync code (32bit)
L ® Sync detect using specified pattern (22bit)
ISPROT: ID sync protection starting conditions
H ® Immediately start ID sync protection when sector sync is detected.
L ® ID Sync protection is started when ID sync is detected in the expected frame after frame sync protection
has begun. Frame number (FN) match:/S0 detected in FN0 set to low after system reset.
•
•
FNADJ: Frame number (address) correcting conditions
H ® Correct counter value within a ±5 difference between the detected frame number and frame counter
value.
L ® Correct counter value within a ±2 difference.
Valid conditions: Frame sync continuity must be maintained. If continuity isn't maintained, it is changed to
insertion mode.
RFNCON: Frame number correction to the detected value.
H ® Frame number correction (if detected frame number is continuous for more than 3 times)
L ® Frame number correction (according to FNADJ conditions)
Valid conditions: Frame sync continuity must be maintained. If continuity isn't maintained, it is changed to
insertion mode.
22
DVDP DATA PROCESSOR IC
KS1453
USERCONT2: User Con. Register2 (Channel Clock PLL Control)
Address
0F
Bit7
ABTH7
1
Bit6
ABTH6
1
Bit5
ABTH5
1
Bit4
ABTH4
1
Bit3
ABTH3
0
Bit2
ABTH2
0
Bit1
ABTH1
0
Bit0
ABTH0
0
Reset Value
•
BTH[7:0]
: Flag generated if the absolute value of the input data difference (|L0-L1|) is larger than the set ABTH value
during L-ch/ R-ch data serial output.
: If the flag pattern is
0
0
1
1
0
0
¬ Flag
|L0-L1| |L1-L2| |L2-L3| |L3-L4| |L4-L5| |L5-L6| ¬ Data
® L3 = (L2+L4)/2
0
0
1
1
1
0
¬ Flag
|L0-L1| |L1-L2| |L2-L3| |L3-L4| |L4-L5| |L5-L6| ¬ Data
® L3 = (L2+L5)/2, L4 = (L3+L5)/2
23
KS1453
DVDP DATA PROCESSOR IC
DVDDSET: DVD Decoder Set (Sync Detect Conditions)
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
10
-
-
-
-
FWSEL1 FWSEL0 FGSEL1 FGSEL0 IGSEL1 IGSEL0
Reset Value
0
0
0
0
0
0
•
•
•
FWSEL1 - 0: Frame sync protection window section select
FWSEL1
FWSEL0
Frame Sync Protection Window (DVD)
Frame Sync Protection Window (CD)
0
0
1
1
0
1
0
1
± 6 clocks
± 12 clocks
± 20 clocks
± 24 clocks
± 3 clocks
± 6 clocks
± 10 clocks
± 12 clocks
FGSEL1 - 0: Number of frame sync inserted frames
FGSEL1
FGSEL0
Number of Frame Sync Inserted Frames
0
0
1
1
0
1
0
1
4 Frames
13 Frames
16 Frames
28 Frames
IGSEL1 - 0: Number of ID sync inserted sectors
IGSEL1
IGSEL0
Number of ID Sync Inserted Sectors
0
0
1
1
0
1
0
1
1 Sector
2 Sectors
3 Sectors
4 Sectors
24
DVDP DATA PROCESSOR IC
KS1453
Bit0
DVDCONTROL1: DVD Decoder (Sync) Control Register 1
Address
11
Bit7
DSCREN
1
Bit6
STRST
0
Bit5
Bit4
Bit3
INSEN
1
Bit2
Bit1
-
-
-
-
WNDEN WNDRT FCLDS
Reset value
1
0
1
•
•
•
•
DSCREN: Descramble on/off
1: Descramble on
0: Descramble off
STRST: Forced TR mode cancellation
1: Cancel
0: Normal
INSEN: Insert enable
1: Carry out frame, ID sync insertion.
0: Don't carry out sync insertion.
WNDEN: Window enable (frame)
1: Enable sync protection window. Sync detected outside the window is illegal, and isn't used in resets such as
insertion timing. If illegal syncs are consecutively found N times, the protection window is reset and opened.
0: Open the window and make all detected syncs valid.
•
•
WNDRT: Window reset
Window is opened if this bit is 1. It is used when you want to lock the window quickly by detecting new sync
during track jump.
FCLDS: Frame counter value load conditions
1: Load the frame counter value continuously detected while continuity was being maintained.
0: Load the frame counter value detected within the frwin section while continuity was being maintained. In
other sections, load the inserted frame counter.
25
KS1453
DVDP DATA PROCESSOR IC
DVDCONTROL2: DVD Control Register 2
Address
Bit7
WRST
0
Bit6
TRST
0
Bit5
ECCST
0
Bit4
Bit3
Bit2
Bit1
Bit0
12
ECNEGLT ECMOD2 ECMOD1 ECMOD0 MCPST
Reset Value
0
0
1
0
0
•
•
•
•
WRST: Enables/Disables EFM demodulated data write to the buffer.
1: Buffer write enable
0: Buffer write disable
TRST: Data transfer enable/disable from the buffer to the A/V decoder or host.
1: Transfer enable
0: Transfer disable
ECCST: Error correction enable/disable.
1: Error correction enable
0: Error correction disable
ECNEGLT: Disregard error correction (used when error still remains in an ECC completed block, but MICOM
decides an ECC retry isn't necessary.)
1: Repeat error correction (until ECC stop {ECCST = “0”} or {ECNEGLT = “1”})
0: Disregard error correction (skip current correction block and move to next block.)
•
ECMOD2 - 0: Error correction mode select
ECMOD2
ECMOD1
ECMOD0
Disc Speed
No error correction
PI+PO
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
PI+PO+PI (normal)
PI+PO+PI+PO
Repeat correction (PIPO)
Reserved
In repeat correction mode (ECMOD2 = “1”), if errors still exist after correction and there is enough buffer space,
ECC is automatically retried until the ECCNEGLT signal is input. (buffer space is determined by MICOM)
•
MCPST: MICOM block copy start command
When it is “1”, the decoder automatically moves 1 sector of data in the MICOM-selected address.
MCPEND is output when the operation is complete, and MICOM resets the MCPST bit to “0”.
26
DVDP DATA PROCESSOR IC
KS1453
CLVCONTROL1: CLV Control Register 1
Address
13
Bit7
Bit6
Bit5
Bit4
SGAIN0
0
Bit3
Bit2
Bit1
Bit0
PGAIN1 PGAIN0 SGAIN1
-
-
-
-
-
-
-
-
Reset Value
0
0
0
•
PGAIN(1:0): DVD/CD CLV's MDP gain select
PGAIN1
PGAIN0
MDP Gain
-6dB
0
0
1
1
0
1
0
1
-12dB
-18dB
0dB
•
SGAIN(1:0): DVD/CD CLV's MDS gain select and CAV control's MDS gain select.
SGAIN1
SGAIN0
MDS Gain
-6dB
0
0
1
1
0
1
0
1
-12dB
-18dB
0dB
27
KS1453
DVDP DATA PROCESSOR IC
CLVCONTROL2: CLV Control Register 2
Address
Bit7
Bit6
Bit5
PLLC1
0
Bit4
PLLC0
0
Bit3
Bit2
MDPC
0
Bit1
PRES1
0
Bit0
PRES0
0
14
MDSCON1 MDSCON0
-
-
Reset Value
0
0
•
MDSCON(1:0): DVD/CD CLV's MDS linear motion range select
Linear Range
MDSCON1
MDSCON0
DVDROM
±9%
CDROM
0
0
1
1
0
1
0
1
±4.5%
±9%
±18%
±36%
±18%
±33%
Reserve
•
PLLC(1:0): Threshold value select for DVD/CD pll lock signal cancellation
PLLC1
PLLC0
Threshold
Pll lock falling after WFCK 16
0
0
1
1
0
1
0
1
Pll lock falling after WFCK 32
Pll lock falling after WFCK 64
Pll lock falling after WFCK 128
•
•
MDPC: MDP output select outside of MDS linear range
MDPC
Operation
0
1
Error signal output outside the MDS linear range
Hi-Z output outside the MDS linear range
PRES(1:0): WFCK/RFCK reference signal for MDP select within CLVP mode of DVD/CD CLV
PRES1
PRES0
WFCK Standard
WFCK/2
RFCK Standard
0
0
1
1
0
1
0
1
RFCK/2
RFCK/4
RFCK/8
RFCK/16
WFCK/4
WFCK/8
WFCK/16
28
DVDP DATA PROCESSOR IC
KS1453
Bit0
CLVCONTROL3: CLV Control Register 3
Bit6 Bit5 Bit4 Bit3
Address
15
Bit7
Bit2
Bit1
FALTHR1 FALTHR0 RISTHR1 RISTHR0 REFSEL SERVOC CLVC1 CLVC0
Reset Value
0
0
0
0
0
0
0
0
•
FALTHR(1:0): DVD/CD's CLV lock signal falling time select
FALTHR1
FALTHR0
Threshold
0
0
1
1
0
1
0
1
CLV lock falling after WFCK/RFCK 32
CLV lock falling after WFCK/RFCK 64
CLV lock falling after WFCK/RFCK 128
CLV lock falling after WFCK/RFCK 256
•
RISTHR(1:0): DVD/CD's CLV lock signal rising time select
RISTHR1
RISTHR0
Threshold
CLV lock rising after WFCK/RFCK 1
CLV lock rising after WFCK/RFCK 2
CLV lock rising after WFCK/RFCK 4
CLV lock rising after WFCK/RFCK 8
0
0
1
1
0
1
0
1
•
•
REFSEL: DVD/CD's CLV lock signal generating GFS sample signal select
REFSEL
CLV Lock Reference Signal
0
1
WFCK
RFCK
SERVOC: DVD/CD's servo lock signal falling time select
Rising is carried out if GFS is detected twice in a row in RFCK standard.
SERVOC
Threshold
0
1
Servo lock falling after RFCK 64
Servo lock falling after RFCK 128
•
CLVC(1:0): Mode select for DVD/CD's CLV lock on/off
CLV Lock decision signal in wide mode: GFS
CLV Lock decision signal in narrow mode: GFS narrow
The narrow signal means the pll operates within the linear range selected by MDSCON(1:0). Narrow means
GFS = high, and the 'not saturated' condition.
CLVC1
CLVC2
CLVLOCK On
(Active High)
CLVLOCK Off
(Active Low)
0
0
1
1
0
1
0
1
Wide
Wide
Wide
Narrow
Wide
Narrow
Narrow
Narrow
29
KS1453
DVDP DATA PROCESSOR IC
CLVMODE: CLV Mode Register
Address
Bit7
SDWP
1
Bit6
SDWB
1
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDCM0
0
16
-
-
-
-
SDCM3 SDCM2 SDCM1
Reset Value
0
0
0
•
•
•
SDWp: Small section sample signal
0: Sample every RFCK/4
1: Sample every RFCK/2
SDWb: Large section sample signal
0: Sample every RFCK/32
1: Sample every RFCK/16
SDCM3 - SDCM0: CLV mode select
SDCM3
SDCM2
SDCM1
SDCM0
CLV Mode
STOP
KICK
MDP Block
Hi-Z
MDS Block
Hi-Z
0
1
1
1
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
0
1
0
1
H
Hi-Z
BRAK
CLVS
CLVH
CLVP
CLVA
L
Hi-Z
L,Z,H
L,Z,H
L,Z,H
L,Z,H
Hi-Z
Hi-Z
Hi-Z
L,H
L,Z,H
L,Z,H
CAV
Other
Reserve
MDP must output to Hi-Z in stop mode.
30
DVDP DATA PROCESSOR IC
KS1453
TRMODE: Data Transfer Mode Register
Address
19
Bit7
Bit6
Bit5
Bit4
Bit3
CDIF0
0
Bit2
DRATE
1
Bit1
Bit0
DVDIF0
1
IFMOD2 IFMOD1 IFMOD0
-
-
-
-
Reset Value
0
0
0
•
•
IFMOD2 - 0: Transfer I/F method to A/V decoder or ROM decoder select
IFMOD2
IFMOD1
IFMOD0
Transfer I/F Method
C (A/V decoder: Synchronous)
Reserved
0
-
0
-
0
-
CDIF0: CD Interface format select
CDIF0
Transfer Format
Format 1
0
1
Format 2
•
•
DRATE: Transfer speed to A/V decoder or ROM decoder select
1: Byte/240nS
0: Byte/480nS
Fixed to byte/240nS in DVD-ROM mode.
DVDIF0: DVD interface format select
DVDIF0
Transfer Format
Mode 1
Transfer Data
2048 Bytes Main
2064 Bytes Sector
0
1
Mode 2
CDSPEED: CD Speed Control Register
Address
1A
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CDSPD0
0
-
-
-
-
-
-
-
-
-
-
CDSPD2
0
CDSPD1
0
Reset Value
•
CD speed control register
CDSPD2
CDSPD1
CDSPD0
DISC Speed
0
0
0
0
0
0
1
0
1x
2x
1
4x
Other
Reserved
31
KS1453
DVDP DATA PROCESSOR IC
CDMUTCNT: CD Mute Control Register
Bit6 Bit5 Bit4 Bit3
CBITIN2 CBITIN1 CBITIN0 DGOEN DEMPHA
Address
Bit7
Bit2
MUTE
1
Bit1
ZCMT
0
Bit0
ATTN
0
1B
Reset Value
0
0
0
0
0
•
CBITIN(2:0): Digital audio output control mode select
CBITIN0 = 0: For common use (mode II)
CBITIN1 = 0: Audio
CBITIN2 = 0: Digital copy prohibited,
1: Digital copy possible
•
•
•
•
•
DGOEN: Digital audio output mode select
0: Hi-Z
1: Output
DEMPHA: CD audio's deemphasis control
0: Deemphasis off
1: Deemphasis on
MUTE: CD-DA data mute
0: Mute off
1: Mute on
ZCMT: Zero cross mute control bit
0: Zero cross mute on
1: Zero cross mute off
ATTN: Attenuation on/off
0: Attenuation off
1: Attenuation on
ATTN
MUTE
dB
0
0
0
1
1
0
1
0
1
-¥
-12
-12
32
DVDP DATA PROCESSOR IC
KS1453
CDCONTROL: CD Control Register
Address
1C
Bit7
Bit6
Bit5
Bit4
Bit3
BYPASS
1
Bit2
INFR
1
Bit1
T3_SEL
0
Bit0
-
-
-
-
T3_MODE
0
Reset Value
0
0
0
0
•
•
BYPASS:
H: Normal L-ch/ R-ch data serial output
L: Error value correcting circuit application.
INFR: Decides whether to release the frame window right after the inserted frame number set by FGSEL (1:0),
or wait until after seeing a few more frame syncs detected by FWID.
0: Release frame window right after the inserted frame number set by FGSEL (1:0). Inserted counter is reset
by the frame sync detected first, and the frame window is locked again within a regular period.
1: Don't release frame window right after the inserted frame number set by FGSE (1:0). Lock frame window
when detected frame syncs are generated continuously within a regular period, after the inserted counter
is reset by the frame sync detected first.
•
•
T3_SEL: When 2T is generated in the EFM input data, and more than 4T of data is maintained before and
after, decides the direction change that will increase data by 2T in either direction to change to 3T.
H: Increase to previous 4T data direction.
L: Increase to later 4T data direction.
T3_MODE: Carry out 3T correction using EFM input data
H: On
L: Off
33
KS1453
DVDP DATA PROCESSOR IC
CDCONTROL: CD Control Register
Bit5 Bit4 Bit3
ERAMOF ERAMOL maxmode maxmode c2eccf
Address
Bit7
Bit6
Bit2
Bit1
Bit0
1D
c2eccl
c2erro
onlyf
c2erro
onlyl
2f
2l
Reset Value
[ERAMODF]
1
1
0
0
1
1
0
0
•
1: Erasure correction mode in DVD mode during max erasure generation
Erasure correction mode in CD-first-C2 mode during max erasure generation
0: Erasure correction mode in DVD mode during max erasure generation
Erasure correction mode in CD-first-C2 mode during max erasure generation
•
•
[ERAMODL] There is no DVD mode.
1: Erasure correction mode in CD-last-C2 mode during max erasure generation
0: Erasure correction mode in CD-last-C2 mode during max erasure generation
[maxmode2f]
1: Don't error correct max erasure generation in DVD mode
Don't error correct max erasure generation in CD-first-C2 mode
0: Error correct max erasure generation in DVD mode
Error correct max erasure generation in CD-first-C2 mode
•
•
•
•
•
[maxmode2l] There is no DVD mode.
1: Don't error correct max erasure generation in CD-last-C2 mode
0: Error correc2eccf] There is no DVD Mode
[c2eccf] There is no DVD mode
1: Don't error correct overflow generation in CD-first-C2 mode
0: Error correct overflow generation in CD-first-C2 mode
[c2eccl] There is no DVD mode
1: Don't error correct overflow generation in CD-last-C2 mode
0: Error correct overflow generation in CD-last-C2 mode
[c2erronlyf]
1: Only error correct in CD-first-C2 mode (Ignore flag)
0: Error correct in CD-first-C2 mode (erasure or error)
[c2erronlyl]
1: Only error correct in CD-last-C2 mode
0: Error correct in CD-last-C2 mode (erasure or error) CT max erasure generation in CD-last-C2 mode
34
DVDP DATA PROCESSOR IC
KS1453
Bit0
CDCONTROL: CD Control Register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
1E
-
cdecc
eccmode c2fgtype
[4]
c2fgtype
[3]
c2fgtype
[2]
c2fgtype
[1]
c2fgtype
[0]
Reset Value
-
1
0
1
1
1
1
1
•
•
•
[cdecc] Repeat correction in CD mode (change name to existing VCDREP bit)
1: Repeat correction
0: Correct once
[eccmode]
1: In CD repeat correction mode (cdecc = 1), don't correct errors in the firstsection, but correct the last section.
0: Correct the errors in both the first and last sections in CD repeat correction Mode.
c2fgtype[4:0] Flag setting condition select in CD mode
c2fgtype[4];
1: If maxmodc2f/maxmodc2l = “1” in CD-C2 mode, C1 flag copy [11]
0: If maxmodc2f/maxmodc2l = “1” in CD-C2 mode, C2 flag out [01]
•
•
•
•
c2fgtype[3];
1: If an overflow occurs in CD-C2 mode, C1 flag copy [11]
0: If an overflow occurs in CD-C2 mode, C2 flag out [01]
c2fgtype[2]; CD repeat correction mode
1: Max correcting (both error and erasure) in CD-last-C2 mode, C1 flag copt [11] ® default
0: Max correcting (both error and erasure) in CD-last-C2 mode, C2 flag out [01]
c2fgtype[1]; CD one time correction mode
1: Max correcting (both error and erasure) in CD-C2 mode, C1 flag copt [11] ® default
0: Max correcting (both error and erasure) in CD-C2 mode, C2 flag out [01]
c2fgtype[0];
1: Uncorrectable code in CD-C2 mode, C1 flag copy [11]
0: Uncorrectable code in CD-C2 mode, C2 flag out [01]
35
KS1453
DVDP DATA PROCESSOR IC
CDCONTROL: CD Control Register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1F
-
-
-
-
-
-
-
-
SETFLG[3] SETFLG[2] SETFLG[1] SETFLG[0]
Reset Value
1
1
1
1
•
SETFLG[3:0]
SETFLG[3];
- PI flag in DVD mode
1: Flag setting only when correction is impossible. (error or erasure) ® Must be 'default'
- C1-first flag in CD mode
1: Flag setting only when correction is impossible (more than 2 errors)
0: Flag setting even during 2 error correction
•
SETFLG[2];
- PO flag in DVD mode
1: Flag setting only when correction is impossible (error or erasure) ® Must be 'default'
- C2-first flag in CD mode
1: Flag setting only when correction is impossible (more than 2 errors) ® Must be 'default'
•
•
SETFLG[1]; No DVD mode. C1-last flag in CD mode.
1: Flag setting only when correction is impossible (more than 2 errors)
0: Flag setting even during 2 error correction
SETFLG[0]; No DVD mode. C1-last flag in CD mode.
1: Flag setting only when correction is impossible (more than 2 errors) ® Must be 'default'
WADRH/M/L: Address Setting on MICOM Direct Access Buffer Mode (Read/Write)
Address
Bit7
-
Bit6
-
Bit5
-
Bit4
Bit3
Bit2
Bit1
ADR17
ADR9
ADR1
Bit0
ADR16
ADR8
ADR0
20
21
22
ADR20
ADR12
ADR4
ADR19
ADR11
ADR3
ADR18
ADR10
ADR2
ADR15
ADR7
ADR14
ADR6
ADR13
ADR5
WDATA: Data write to buffer (when MDAB = 1)
WDT6 WDT5 WDT4 WDT3
20 - 23 register: all-zero
23
WDT7
WDT2
WDT1
WDT0
Reset Value
36
DVDP DATA PROCESSOR IC
Buffer Writing
KS1453
ZCS
MRZA
MWR
MRD
MDAT (7:0)
*ZWAIT
$23
WDATA1
WDATA2
Set register
ADR. $23
- Store WDATA1
(WDT7 ~ WDT0)
value to $23 register.
- When the ZWAIT
signal is disabled (high), MICOM
prepares the next data for transfer
(WDATA2).
- ZWAIT signal enable
(low) until WDATA1
is completely stored
in the buffer.
- $23 register pointer doesn't
change. WDATA2 is stored in the
register.
- WADR ($20 ~ $22)'s buffer point
(ADR20 ~ 0) increases automatically.
- Enable the ZWAIT signal until WDATA2
is completely stored in the buffer
pointer. MICOM stores the next value
(WDATA3, ..) in the register when
ZWAIT is high.
Figure 5. Buffer Writing
37
KS1453
DVDP DATA PROCESSOR IC
Last Writed Address Reading
Read the buffer pointer value (+ 1) last written in the buffer.
ZCS
MRZA
MWR
MRD
MDAT (7:0)
$20
Data ($20)
Data ($21)
Set register
ADR. $20
Read $20
ADR. register value
- Automatically change register pointer
to $21
- Read register value of $21
Figure 6. Last Writed Address Reading
Buffering Start Sector Unit Number
Address
30
Bit7
Bit6
Bit5
Bit4
B9 - B8
Bit3
Bit2
Bit1
Bit0
31
B7 - B0
3FF
Reset Value
Select the start sector unit number for storing EFM data in the buffer. Set W sector unit.
ECC Start Sector Unit Number
Address
32
Bit7
Bit6
Bit5
Bit4
B9 - B8
Bit3
Bit2
Bit1
Bit0
33
B7 - B0
3FF
Reset Value
Select the sector unit number for error correction. (Set in units of blocks with B3 - B0 = “0”) Set X sector unit.
38
DVDP DATA PROCESSOR IC
KS1453
Bit0
Transfer Start Sector Unit Number
Bit6 Bit5 Bit4 Bit3
B9 - B8
Address
34
Bit7
Bit2
Bit1
35
B7 - B0
1FF
Reset Value
Select sector unit number for starting data transfer. Set Z sector unit.
The unit number above is automatically incremented in units of sectors when all applicable start signals are
enabled and completed.
Unit Number definition
B9 - 8: Bank 0 - 3
B7 - 4: Block 0 - 12
B3 - 0: Sector 0 - 15
Over Threshold Size (Sector Unit Number) (Read/Write)
Address
36
Bit7
Bit6
Bit5
Bit4
B9 - B8
Bit3
Bit2
Bit1
Bit0
37
B7 - B0
All High
Reset Value
Set buffer memory's over threshold size (maximum 16 blocks). In other words, set the maximum allowable value
for the absolute value of (unit number W-unit number Z). When the section filled with memory is larger than the
selected value, the Z-decoder generates an over interrupt.
Under Threshold Size (Sector Unit Number) (Read/Write)
Address
38
Bit7
Bit6
Bit5
Bit4
B9 - B8
Bit3
Bit2
Bit1
Bit0
39
B7 - B0
All Zero
Reset Value
Set buffer memory's under threshold size (maximum 16 blocks). In other words, set the minimum allowable value
for the absolute value of (unit number w - unit number Z). When the section filled with memory is less than the
selected value, the Z-Decoder generates an under interrupt.
39
KS1453
DVDP DATA PROCESSOR IC
Transfer Sector Number Select (Read/Write)
Bit6 Bit5 Bit4 Bit3
B15 - B8
Address
Bit7
Bit2
Bit1
Bit0
3A
3B
B7 - B0
All High
Reset Value
Sets the number of bytes of the data to be transferred to the A/V decoder or ROM decoder. Maximum number of
sectors to be transferred is 64K sectors. After trasferring the predetermined number of sectors, the Z-decoder
generates the transfer complete interrupt (TRSCMPLT).
Buffer Size for MICOM select (Read/Write)
Address
3C
Bit7
Bit6
Bit5
Bit4
Bit3
B3
0
Bit2
B2
0
Bit1
B1
0
Bit0
B0
1
-
-
-
-
-
-
-
-
Reset Value
Select the size of the buffer for MICOM. The size is in units of ECC blocks (16KBytes), and a maximum of 8 blocks
is possible in bank units.
(LSB 4 bits: For DVDs '0001'[Block 1] - '1000' [Block 8]
For CDs '0001' - '0111')
The initial value is 1 block.
Bank: composed in units of 4 Mbit. There are 4 banks in a 16M bit, so a buffer for MICOM with a maximum of 32
Block (512K byte ® 4Mbits) can be guaranteed.
Decoder Direct Block Copy Source Sector Address Select (Read/Write)
Address
3D
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
B9 - B8
B7 - B0
All Zero
3E
Reset Value
Source sector address which is used in the mode that automatically moves the data to be used by MICOM within
the buffer in units of sectors.
Decoder Direct Block Copy Target Sector Address Select (Read/Write)
Address
40
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
B9 - B8
B7 - B0
41
Reset Value
All Zero
Target sector address which is used in the mode that automatically moves the data to be used by MICOM within
the buffer in units of sectors.
40
DVDP DATA PROCESSOR IC
KS1453
Bit0
Descramble Start Sector Unit Number (Read/Write)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2
B9 - B8
Address
42
Bit1
43
B7 - B0
1FF
Reset Value
Set descramble starting sector unit number.
The unit number is automatically incremented when all applicable start signals are enabled and completed in
units of sector.
Unit number definition
B9 - 8: Bank 0 - 3
B7 - 4: Block 0 - 12
B3 - 0: Sector 0 - 15
USERREG
Address
A8
Bit7
Bit6
Bit5
TSTWRD
0
Bit4
ectest
0
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
-
-
-
-
Reset Value
•
•
TSTWRD: For chip testing.
Ectest: For ECC block simulation (let it be in default state)
USRREG: ECC Operation Control/Memory Point Reset
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
AA
MONITO
R3
MONITO
R2
MONITO MONITO MPRSTZ TSTEND TSTPOR TSTPIRE
R1
R0
MUX
END
ND
Reset Value
0
0
0
0
1
0
0
0
•
•
MONITOR 3 - 0: For internal signal monitoring in chip test mode.
MPRSTZ: BUNP, DUNP, EUNP, and TUNP's initial value select register
1: TUNP = "1FF"
0: BUNP, DUNP, EUNP = "3FF"
Used for stopping a mode by force during ECC's operation (PI read or PO read). When the operation is
stopped, the next operation is carried out according to the specified ECC mode. In other words, if you stop the
first PI process by force in PI+PO+PI mode, the PO mode is initiated, and if the PO mode is stopped by force,
the next PI is initiated. If you stop during the last PI process, the next ECC block's first PI process is initiated.
•
Stop operation:
① Tstendmux bit set to “1”.
② Tstpirend if PI. tstporend if PO, set the bit to “1”. ® Stop the operation at this time.
③ Tstpirend or tstporend bit is set to”0”.
④Set tstendmux bit to “0”
- ③ and ④can be carried out simultaneously.
41
KS1453
DVDP DATA PROCESSOR IC
USRREG: Data Transfer/Test Mode Register
Bit6 Bit5 Bit4 Bit3
REQEG ACKEG STREG TOSEG DTEREG
Address
Bit7
Bit2
Bit1
TSTID
0
Bit0
TSTIDSY
0
AE
-
-
Reset Value
0
0
0
0
0
•
REQEG, ACKEG, STREG, TOSEG, DTEREG
Selects the active mode of the transfer-related signals (DATREQ, DATACK, STROBE, TOS, DTER).
VALUE
REQEG
Active High
Active Low
ACKEG
Active High
Active Low
STREG
TOSEG
DTEREG
Active High
Active Low
1
0
Falling Edge
Rising Edge
Active High
Active Low
•
TSTID, TSTIDSY
For chip testing
USERREG: PWM Register
Bit6 Bit5 Bit4
Address
Bit7
Bit3
Bit2
Bit1
Bit0
C0
PWM07 PWM06 PWM05 PWM04 PWM03 PWM02 PWM01 PWM00
PWM17 PWM16 PWM15 PWM14 PWM13 PWM12 PWM11 PWM10
PWM27 PWM26 PWM25 PWM24 PWM23 PWM22 PWM21 PWM20
PWM37 PWM36 PWM35 PWM34 PWM33 PWM32 PWM31 PWM30
PWM47 PWM46 PWM45 PWM44 PWM43 PWM42 PWM41 PWM40
PWM57 PWM56 PWM55 PWM54 PWM53 PWM52 PWM51 PWM50
PWM67 PWM66 PWM65 PWM64 PWM63 PWM62 PWM61 PWM60
PWM77 PWM76 PWM75 PWM74 PWM73 PWM72 PWM71 PWM70
C1
C2
C3
C4
C5
C6
C7
Reset Value
1
0
0
0
0
0
0
0
•
•
•
PWM output's high pulse width is capable of changing in 0 - 255 steps.
Resolution: XTI1 1CLK/STEP
Address: Output pin
Address
C7
C6
C5
C4
C3
C2
C1
C0
Output PIN
PWMO7 PWMO6 PWMO5 PWMO4 PWMO3 PWMO2 PWMO1 PWMO0
42
DVDP DATA PROCESSOR IC
KS1453
Bit0
CAVCONTROL: CAV Control Register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
C8
CKSEL1 CKSEL0
-
-
-
CAVVAL1 CAVVAL9 CAVVAL8
0
C9
CAVVAL7 CAVVAL6 CAVVAL5 CAVVAL4 CAVVAL3 CAVVAL2 CAVVAL1 CAVVAL0
Reset Value
0
0
0
0
0
0
0
0
•
•
CKSEL(1:0): Reference clock select for CAV control
CAVVAL(10:0): Initial value select for CAV control
DISC Rotation Number Selection Range
CAVCK(1)
CAVCK(0)
Nck
DVD
CD
0
0
1
1
0
1
0
1
8
4
2
1
1372.4 - 2746.5
686.2 - 1372.4
343.1 - 686.2
171.5 - 343.1
215.2 - 430.7
107.6 - 215.2
53.8 - 107.6
26.9 - 53.8
In CAV mode, the disc rotating speed is set according to the following formula.
DISC RPM = fsys ´ 10 ´ Nck / 1024 / CAV_REF
Here,
fsys: System clock for DVD (27MHz), for CD (33.8688/8MHz)
Nck: Select clock division ratio using CAVCK[1:0]
In other words, (8 ® 1/128, 4 ® 1/256, 2 ® 1/512, 1 ® 1/1024).
CAV_REF26.16: Value defined by (1537- Ncarv).
Has a range of 1408 £ CAV_REF £ 1537.
XT AL ´ 10 ´ Nc k
F or m ua l : CAV _ RE F = --------------------------------------------------
1024 ´ RP M
Where XTAL: DVD (XTL1), CD (CK33MI/8)
Example) CAVVAL(10:0) value select for 1440 RPM
26.16MHz ´ 10 ´ 8
CAV _ RE F = ------------------------------------------------------ = 1419.27 = 1419
1024 ´ 1440
CAVVAR = 1537 – 1419 = 118 = 7 6 H
The CAV_REF value in the formula above can change depending on the fsys.
43
KS1453
DVDP DATA PROCESSOR IC
MICOM READ REGISTER & READ/WRITE REGISTER (R/W UNMARKED; R)
INTSTAT1: Interrupt Status Register 1
Address
4A
Bit7
DVDSINT
0
Bit6
Bit5
Bit4
Bit3
Bit2
EMPTY
0
Bit1
Bit0
DSINT TOSINT TRSCMPLT ECCMPLT
OVER UNDER
Reset Value
0
0
0
0
0
0
•
•
DVDSINT: DVD Sync interrupt request
Set to '1' each time a sync (ID sync) is output from the DVD decoder.
This interrupt is generated when INTCTL3 ($0C)'s CLRINT bit is “1”. It is cleared to “0” when MICOM reads the
bit of the register
The first ID sync during abnormal PLAY (such as reset, search or jump) is an inserted ID sync, so you shouldn't
use it as an ID interrupt.
DSINT: DSI interrupt request
In the DVD decoder, out of the 2048 main data,
If the system header Start_Code (00, 00, 01, BB) starts at the 15th byte, and
The Packet_Header (00, 00, 01, BF, **, **) starts at the 39th byte and
Sub_Stream_id (00),
the sector is determined to be a DSI pack and sets DSINT to 1. When CLRINT bit is 1, it is cleared to “0” when
MICOM reads the bit of the register.
DT
DT DT DT DT
DT
2047
DT0 DT1 DT2
........
DT0 DT1
14 - - 17 - 38 - 44 45
DSI Section
2048 Main Data Within 1 Sector
- Don't care in CD mode.
•
TOSINT: Top of sector interrupt request
Request that marks the beginning of the sector during data transfer.
Cleared to '0' when CLRINT = “1” and MICOM reads the bit of the register.
•
•
TRSCMPLT: Interrupt request sent when transfer is completed for the predetermined number of bytes.
ECCMPLT: ECC complete interrupt request.
Interrupt request sent when error correction is completed. Cleared to “0” when CLRINT = “1” and MICOM
reads the bit of the register.
44
DVDP DATA PROCESSOR IC
KS1453
Steps EMPTY, OVER, UNDER are the same as those of DVD Sync
•
•
EMPTY: When there aren't any data (sector) to be transferred to memory.
OVER: Memory overflow flag. If the section filled with memory when DVD sync is being generated is above the
OTS (Over Threshold Size) value, the Z-decoder sends the over interrupt. It is cleared to “0” when CLRINT =
“1” and MICOM reads the bit of the register.
•
UNDER: Memory underflow flag
When the section filled with memory is under the UTS (Under Threshold Size) value, the Z-decoder sends the
under interrupt.It is cleared to “0” when CLRINT = “1” and MICOM reads the bit of the register.
- OVER, UNDER interrupt
The new over interrupt only occurs if there is an over after an over interrupt and under interrupt have already
occurred. Likewise, a new under interrupt only occurs if there is an under after an under interrupt has already
occurred.
Over
Over
Under
No Under
Under
Under
45
KS1453
DVDP DATA PROCESSOR IC
INTSTAT2: Interrupt Status Register 2
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
4B
SBQINT MCPINT
-
-
-
-
-
-
-
-
-
-
-
-
Reset Value
0
0
•
•
SBQINT: Subcode Q sync interrupt
Detects subcode sync S0, S1 and generates an interrupt.
MCPINT: MICOM block copy complete interrupt.
ERRSTAT: ERROR Status Register
Address
4C
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
EIDERR DSIERR IDCONERR
-
-
ECCERR EDCFLG
-
-
SBQERR
0
Reset Value
0
0
0
0
0
Various error status information can be found using the interrupt status register.
•
EIDERR: You can see if there are any errors in the ID address data in the EFM demodulated data sector being
input into the current buffer according to the DVDSINT (DVD ID sync interrupt) state.
1: Errors detected (ID ECC error)
0: No Errors
•
•
DSIERR: You can see if there are any errors in the currently generated DSINT ($4A) according to the
DVDSINT (DVD ID sync interrupt) state
1: Error possible (EDC error)
0: No errors
•
IDCONERR: Continuity error presence in sector ID address of EFM data being writed into the buffer (checks
the continuity of two consecutive ID numbers)
1: Discontinuous
0: Continuous
•
•
ECCERR: Error presence in current error corrected data, shown by ECCMPLT (ECC complete interrupt) state.
1: Error present (1 block's ECC results)
0: No errors
EDCFLG: Error presence in 2064 bytes of sector data output to the A/V decoder, shown by TOSINT (top of
sector interrupt) state.
1: Error present
0: No errors
•
SBQERR: Error presence in subcode data output to the A/V decoder, shown by SBQINT (subcode Q interrupt)
state.
1: Error present
0: No errors
46
DVDP DATA PROCESSOR IC
KS1453
DVDSTATUS: DVD Decoder Status Register
Address
4D
Bit7
Bit6
Bit5
Bit4
Bit3
SYOK
0
Bit2
NOSY
0
Bit1
ILSY
0
Bit0
-
-
-
-
-
-
-
-
-
-
Reset Value
The Sync status of the sector with the interrupt can be found by the INTSTAT1 register ($4A)'s DVDSINT interrupt.
•
•
•
SYOK: “1” is read when ID sync is detected in the same timing as the inserted timing.
NOSY: “1” is read when ID sync is not detected within window.
ILSY: “1” is read when ID sync is detected outside window.
DVDSVSTAT: DVD Decoder Servo Status Register
Address
4E
Bit7
Bit6
LOCK
0/X
Bit5
GFS
0/X
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
-
-
-
-
Reset Value
•
•
LOCK: “1” when the spindle servo is locked.
GFS: “1” when the 16-8 frame sync (17.58kHz) from playback is found by accurate timing.
CDSUBQ: CD-DA Subcode Q Register
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
50
SBQ79 - SBQ72
¯
¯
¯
¯
¯
¯
59
SBQ07 - SBQ00
Reset Value
X
X
X
X
X
X
X
X
CD-DA Subcode Q data storage.
When S0S1 (serve code block sync) is low, this data is valid.
47
KS1453
DVDP DATA PROCESSOR IC
SEEKIDADR: ID Data During EFM Demodulation
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
60
SID31 - SID24
SID23 - SID16
SID15 - SID08
SID07 - SID00
61
62
63
Reset Value
X
X
X
X
X
X
X
X
This data is used for the ID address of the data being currently EFM demodulated, seamless buffering control, and
disc search. it is valid until next DVDSINT interrupt.
IDSYZ
Demodulated Data
SID (7:0)
N's Demodulated Data
N-1's ID Output
N+1's Demodulated Data
N's ID Output
N+2's Demodulated Data
N+1's ID Output
EIDERRO
N-1's ID Error Output
N's ID Error Output
N+1's ID Error Output
48
DVDP DATA PROCESSOR IC
KS1453
Bit0
TRANSIDADR: ID Data During Data Transfers to A/V Decoder
Address
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
64
TID31 - TID24
TID23 - TID16
TID15 - TID08
TID07 - TID00
65
66
67
Reset Value
X
X
X
X
X
X
X
X
ID address of the data being output to the A/V decoder or ROM decoder after decoding. This data is valid until the
next TOSINT interrupt.
ZIRQZD (pin)
DVDSINT ($4A)
N's Data Descramble
X
N+1's Data Descramble
X
Output DSIFG ($4A) & Store DSIID
Address ($90 ~ 93)
DSIFG ($4A)
Internal Detection (DSIFG)
N's EDCERR ($4C) Operation
N+1's EDCERR ($4C) Operation
Address N's Sector EDC Result
DSIERR ($4C)
(EDC result)
49
KS1453
DVDP DATA PROCESSOR IC
RADR, RDATA: MDAB Register for Direct Access on DRAM (MDAB = 1)
(Read/Write Register)
Address
Bit7
-
Bit6
-
Bit5
-
Bit4
Bit3
Bit2
Bit1
ADR17
ADR9
ADR1
Bit0
ADR16
ADR8
ADR0
70
71
72
ADR20
ADR12
ADR4
ADR19
ADR11
ADR3
ADR18
ADR10
ADR2
ADR15
ADR7
ADR14
ADR6
ADR13
ADR5
RDATA: Data read from buffer (When MDAB = 1)
RDT6 RDT5 RDT4 RDT3 RDT2
All Zero
73
RDT7
RDT1
RDT0
Reset Value
READ ACCESS
Buffer Read Address Setting
ZCS
MRZA
MWR
MRD
MDAT (7:0)
$70
RADRH
RADRM
Register ADR.
$70 select
ADR20 ~ ADR16
value stored in $70
- Register pointer automatically
changed to $71.
- ADR15 ~ ADR8 value stored
in $71 register.
70's register address doesn't automatically increase, so it must always be set by MICOM.
50
DVDP DATA PROCESSOR IC
Buffer Reading
KS1453
ZCS
MRZA
MWR
MRD
MDAT (7:0)
ZWAIT
$73
X
RDATA1
X
RDATA2
Register ADR.
$73 select.
- Store the buffer data
selected by RADR
($70~$72)'s buffer
pointer into the
register $73
- If MICOM read RDATA1, the
$73 register pointer stays the
same, while the RDAT ($70~72)'s buffer
pointer automatically increases to move
RDATA2 to register $73.
(RDATA1:
RDT7~RDT0).
- Enable ZWAIT (low) after MRD
falling, then disable ZWAIT when
RDATA2 is completely stored in register
$73.
- Enable ZWAIT
(low) after MRD
falling, and when
RDATA1 storage in
register $73 is
- When ZWAIT signal is disabled
(high), read RDARA1 and MRD rising
after RDATA2 read.
completed, disable
ZWAIT signal.
- When ZWAIT signal
is disabled
(high), MICOM read
RDATA1 and
MRD rising.
51
KS1453
DVDP DATA PROCESSOR IC
Last Read out Address Reading
Read the value 'Buffer Pointer+1' from the last read out.
ZCS
MRZA
MWR
MRD
MDAT (7:0)
$70
RADRH
RADRM
Register ADR.
$70 select
Read register $70's
value
- Register pointer automatic change to
$71
- Read register $71's value
52
DVDP DATA PROCESSOR IC
KS1453
Bit0
Buffering End Sector Unit Number
Bit Bit5 Bit4 Bit3
B9 - B8
B7 - B0
B (9:0) = 3FF
Address
80
Bit7
Bit2
Bit1
81
Reset Value
Sector unit Number of the current buffer after EFM data write completion. Valid until the next DVDSINT interrupt. 1
sector carried out while WRST low is stored. When WRST ® 'L', the completed sector no.value is output (valid
from first DVDSINT after WRST low).
ECC End Sector Unit Number
Address
82
Bit7
Bit
Bit5
Bit4
B9 - B8
B7 - B0
B (9:0) = 3FF
Bit3
Bit2
Bit1
Bit0
83
Reset Value
Sector unit number of the current buffer after error correction is completed. Valid until the next ECCMPT interrupt.
When ECCST ® 'L', immediately stopped. When ECCST ® 'L', (ECC completed < or ended > block no.) is read.
Transfering End Sector Unit Number
Address
84
Bit7
Bit
Bit5
Bit4
B9 - B8
B7 - B0
B (9:0) = 1FF
Bit3
Bit2
Bit1
Bit0
85
Reset Value
Buffer unit number of the data continuing to be output to the A/V decoder or ROM decoder after the decoding. Valid
until the next TOSINT interrupt. When TRST ® 'L' outputs the transfer completed unit number.
DSI Unit Number
Address
86
Bit7
Bit
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
B9 - B8
87
B7 - B0
Reset Value
B (9:0) = 000
Unit number of the buffer that stores the DSI sector after DSIFG ($4A) generation. Valid until the next DVDSINT
interrupt.
53
KS1453
DVDP DATA PROCESSOR IC
BUFFER WRITE
During Re-search or Jump Control
- Set WRST out of write to “0”, reassign the memory address to WBA, and write.
WBA ($30, $31)
WBA
SID
WBA + X
SEEKIDADR
($60-$63)
XXX
SID
SID + 1
SID + 2
SID + X
Actua ID of the
data being stored
SID + 1
WBA
SID + X
SID + X + 1
WBA + X
WBA
+ 2
RWA ($80, $81)
XXX
WBA + 1
WRST ($12)
DVDSINT ($4A)
54
DVDP DATA PROCESSOR IC
KS1453
Write Control According to Over or Under Interrupt
- Stopping and starting write is accomplished by controlling WRST. The write location isn't reloaded.
WBA ($30, $31)
WBA
SID
WBA
SEEKIDADR
($60-$63)
XXX
SID
SID + 1
SID + 2
WBA + 1
SID + 3
Actua ID of the
data being stored
SID + 1
WBA
SID + 3
SID + 4
WBA
+ 2
RWA ($80, $81)
XXX
WBA + 3
WRST ($12)
DVDSINT ($4A)
55
KS1453
DVDP DATA PROCESSOR IC
ECC CONTROL
- If ECCST is “0” while must be carrying out ECC, always must be set the next ECC address to WEA.
- If ECCST is “0”, stop the current ECC operation in execution.
WEA ($32, $31)
WEA
WEA + N
CID + N
EEIDA
($94-$97)
XXX
CID
XXX
CID
CID + 16
CID + 32
WEA + 16
XXX
CID + N
XXX
CID + N + 16
ID of data being
corrected
CID + 16
WEA
CID + N + 16 SID + N + 32
REA ($82, $83)
ECCST ($12)
WEA + N
WEA + N + 16
ECCMPLT ($4A)
ECCERR
DVDSINT ($4A)
56
DVDP DATA PROCESSOR IC
KS1453
CONTROL DURING TRANSFER
Transfer After Reassigning The Memory Address During Transferring:
- Set TRST to “0”, reassign a new address to WTA, and start re-transferring by setting TRST to “1”.
(Even if TRST is “0”, reassignment must come after transferring the specified sector amount.)
WTA ($34, $35)
WTA
WTA + X
TRANSIDADR
($64-$67)
TID
TID
TID + 1
TID + 1
WTA
TID + 2
TID + 2
WTA + 1
TID + X
TID + X +1
Actua ID of data
being transferred
TID + X
XXX
TID + X +1
WTA + X
WTA
+ 2
RTA ($84, $85)
XXX
Transfer
complete even
when TRST = 0
TRST ($12)
TOSINT ($4A)
57
KS1453
DVDP DATA PROCESSOR IC
Stopping and Starting Transfer by Controlling Only TRST
WTA ($34, $35)
WTA
WTA
TRANSIDADR
($64-$67)
TID
TID
TID + 1
TID + 1
WTA
TID + 2
TID + 2
WTA + 1
TID + 3
TID + 3
TID + 4
TID + 4
Actua ID of data
being transferred
WTA
+ 2
RTA ($84, $85)
XXX
WTA + 3
TRST ($12)
TOSINT ($4A)
58
DVDP DATA PROCESSOR IC
KS1453
Bit0
Descramble end Sector Unit Number
Bit Bit5 Bit4 Bit3
B9 - B8
Address
88
Bit7
Bit2
Bit1
89
B7 - B0
Reset Value
B (9:0) = 3FF
Sector unit number of the completely descrambled buffer
ECC end ID Address
Address
Bit7
Bit
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
94
B31 - B24
95
B23 - B16
B15 - B8
B7 - B0
96
97
Reset Value
X
X
X
X
X
X
X
X
The ID address corresponding to the end sector unit number of the buffer that has just finished error correction.
This data is valid until the next ECCMPT interrupt.
DSI ID Address
Address
Bit7
Bit
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
9C
B31 - B24
9D
9E
B23 - B16
B15 - B8
B7 - B0
9F
Reset Value
X
X
X
X
X
X
X
X
DSI sector's ID address stored in the buffer after DSIFG ($4A) generation. This data is valid until the next
DVDSINT interrupt.
Remaining Data Size (SECTOR Unit)
Address
F0
Bit7
Bit
Bit5
Bit4
B9 - B8
B7 - B0
Bit3
Bit2
Bit1
Bit0
F1
Reset Value
X
X
X
X
X
X
X
X
The difference between the sector unit number of a descrambled buffer and the unit number after transfer to the A/
V decoder or ROM decoder. You can find out how much extra data you have to transfer.
59
KS1453
DVDP DATA PROCESSOR IC
OVER, UNDER INTERRUPT ($4A) APPLICATION
60
DVDP DATA PROCESSOR IC
KS1453
5
INTERFACE
MICOM I/F
MICOM I/F TIMING
Read Cycle
ZCS
MRZA
MWR
MRD
MDAT (7:0)
Address
Data
Write Cycle
ZCS
MRZA
MWR
MRD
Address
Data
MDAT (7:0)
61
KS1453
Read Cycle Timing
MRZA
DVDP DATA PROCESSOR IC
T
MRZA-SETUP
TMRZA-HOLD
ZCS
T
ZCS-SETUP
TZCS-HOLD
MWR
T
MWR-INACTIVE
T
MRD-ACTIVE
MRD
T
MRD-INACTIVE
T
H2
T
READ-VALID
T
RDAT-HOLD
T
H1
MDAT [7:0]
Write Cycle Timing
MRZA
ZCS
T
MRZA-SETUP
TMRZA-HOLD
T
ZCS-SETUP
TZCS-HOLD
MRD
T
MRD-INACTIVE
T
MWR-ACTIVE
MWR
T
MWR-INACTIVE
T
WDAT-SETUP TWDAT-HOLD
VALID
MDAT [7:0]
62
DVDP DATA PROCESSOR IC
Time
KS1453
Description
Min
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TMRZA-SETUP
MRZA setup
T
MRZA hold
ZCS setup
ZCS hold
10
10
10
30
30
30
120
MRZA-HOLD
T
ZCS-SETUP
T
ZCS-HOLD
T
T
MWR inactive
MWR-INACTIVE
T
MWR active pulse width
MWR-ACTIVE
MRD inactive
MRD-INACTIVE
T
MRD active pulse width
MRD-ACTIVE
T
MRD active to read data valid
MRD active to MDAT(7:0) OW-impedance
MRD inactive to MDAT(7:0) IGH-impedance
Read data hold after MRD inactive
Write data setup
60
-
READ-VALID
T
T
-
H1
H2
-
T
10
20
10
RDAT-HOLD
T
WDAT-SETUP
T
Write data hold
WDAT-HOLD
There should be no glitches in signals MRZA, ZCS, MWR, and MRD.
63
KS1453
DVDP DATA PROCESSOR IC
AV DECODER I/F
Equal spacing timing transfer method (DVD-P I/F)
TW-TOS
TOS
TCSPULSE-HIGH
TCSPULSE-LOW
CSTROBE/
DATACLK
TCSPULSE-CYCLK
TDATA-SETUP-STR TDATA-HOLD-STR
SDATA (7:0)
DATREQ
DATACK
DTER
INVALID
TDATA-ACCESS
ACK-HOLD
TACK-SETUP
MODE1: 2048 bytes main data only ® compared to MODE2, Tdata-access has a delay longer by 16bytes at the
beginning of data transfer, but the overall data rate is the same.
MODE2: 2064 bytes data in a sector
(4bytes ID + 2bytes IEC + 6bytes RSV + 2048bytes main data + 4bytes EDC)
•
•
•
•
•
•
The DTER signal is output in units of sectors.
Data is taken at CSTROBE/DATACLK'S falling edge (rising edge in reverse mode).
CSTROBE/DATACLK'S duty cycle is not regular
Tcspulse-high/low: 4T
Tcspulse-cycle: 8T (240 ns)
CSTROBE, DATREQ, DATACK'S edge is programmable (reversible).
64
DVDP DATA PROCESSOR IC
KS1453
Timing Spec
Time
Description
Min
5
Max
4T
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDATA-SETUP-STR
TDATA-HOLD-STR
TD
SDATA(7:0) setup to cstrobe asserted (synchronous)
SDATA(7:0) hold from cstrobe asserted (synchronous)
Delay from datreq asserted to datack (asynchronous)
Datack low time (asynchronous)
5
4T
0
TACK-LOW
50
236
12
TCSPULSE-CYCLE
TACK-HOLD
TSDATA-D
Datack period
Datack disabled time
4T
10
SDATA(7:0) delay from datack falling
Datack setup to cstrobe (synchronous)
Datack hold from cstrobe (synchronous)
TACK-SETUP
TACK-HOLD
5
5
65
KS1453
DVDP DATA PROCESSOR IC
CD-DA/ CD-ROM/ V-CD DATA OUTPUT TIMING (FORMAT 1, FORMAT 2)
66
DVDP DATA PROCESSOR IC
KS1453
SUBCODE OUTPUT I/F (FOR CD-G)
SOS1
WFSY
1
2
3
4
5
6
7
8
I
SQCK
SQDT
II
Q
R
S
T
U
V
W
III
I: After WFSY becomes falling edge, SQCK becomes “L” at about 10 m sec.
II: If S0S1 is “L”, subcode P is output, and if “H”, subcode sync S0 and S1 are output.
III: If pulses are input to the SQCK terminal over seven, subcode data (P, Q, R, S, T, U, V, W) are repeated.
SOS1
0
1
2
3
4
5
6
95
96
97
WFSY
SQCK
SQDT
P
Q
R
S
T
U
V
W
1 subcode sync = 98 EFM FRAMEs (1 EFM FRAME = 7.35kHz, 1 subcode sync = 75Hz)
98 EFM FRAMEs = 2bytes for subcode sync (S0, S1) + 96bytes for subcode data
96bytes subcode data = 1(P) bit ´ 96 + 1(Q) bit ´ 80 + 16bits (CRC for EDC) for CDP + 6(R - W) bits ´ 96 for CDG
67
KS1453
DVDP DATA PROCESSOR IC
WFSY
T
D
T
SQCKHW
T
SQCKLW
SQCK
SQDT
S0S1
T
HOLD
P
Q
R
Byte
0
Byte
Byte
2
Byte
3
Byte
4
Byte 97 Byte
Byte
1
1
0
T
S0S1HW
TBP
WFSY
SQCK
T
FP
TWFSYLM
Time
Description
Min
Typ
Max
Unit
T
Delay time from WFSY low to SQCK high edge
for "P" subcode bit (SQCK input)
1
-
-
us
D
T
SQCK (input) high pulse width
SQCK (input) low pulse width
SQDT hold time from SQCK high
S0S1 high pulse width
Block period
1
1
0
-
-
-
3
3
-
us
us
ns
us
ms
us
us
SQCKHW
T
SQCKLW
T
-
HOLD
T
136
13
136
68
-
S0S1HW
T
T
-
-
BP
Frame period
-
-
FP
T
WFSY low pulse width
-
-
WFSYLW
SQDT read should be completed when WFSY is low (TWFSYLW).
68
DVDP DATA PROCESSOR IC
KS1453
6
MISCELLANEOUS
EXTERNAL DRAM MEMORY MAP
ECC 13 block can be stored using 4M DRAM, and can carry out the following: EFM+demodulation 1 block, ECC 1
block, descramble 1 block, and TRANS 1 block.
: Memory mapping (512 x 512 x 16) for DVDP.
1 sector standard: ID(4), IEC(2), RSV(6), DPDATA(2048), EDC(4), PI(120), PO(182)
0 0000 0000 (0)
DPDATA (208 x 2048 Byte)
13 ECC Block
-> 208 Sector
1 1010 0000 (416)
1 1100 0000 (448)
1 1001 1111 (415)
1 1011 1001 (441)
PI (208 x 120 Byte)
PO (208 x 182 Byte)
1 1111 0100 (500)
1 1111 1000 (504)
1 1110 0011 (499)
1 1111 0111 (503)
1 1111 1111 (511)
Un - Used
ID + IEC + RSV + EDC (208 x 16 Byte)
Figure 7. External DRAM Memory Map
MEMORY MAPPING DEFINITION BY SECTOR
PI: 128byte per sector.
- 1 row address increases per 8 sectors.
PO: 256byte per sector.
- 1 row address increases per 4 sectors.
ID, IEC, RSV, EDC: 32bytes per sector.
- 1 row address increases per 32 sectors.
69
KS1453
DVDP DATA PROCESSOR IC
ADDRESS MAPPING
Data Mapping
ECC Block
Number
ID Sector
Number
Row Address
Column Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
x
. . .
. . .
. . .
15
0
0
0
0
0
0
0
0
1
0
1
0
1
x
1
x
x
1
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0 - 15
2
0 - 15
. . .
x
x
. . .
. . .
. . .
12
0
1
1
1
1
0
0
0
0
0
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
. . .
. . .
. . .
15
1
x
PI Mapping
ECC Block
Number
ID Sector
Number
Row Address
Column Address
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
1
0
0
0
0
0
0
1
x
. . .
. . .
. . .
15
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
x
x
1
x
x
1
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0 - 15
2
0 - 15
. . .
0
x
. . .
. . .
. . .
12
0
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
. . .
. . .
. . .
15
1
x
70
DVDP DATA PROCESSOR IC
PO Mapping
KS1453
ECC Block
Number
ID Sector
Number
Row Address
Column Address
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
x
. . .
. . .
. . .
15
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
x
x
1
x
x
1
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0 - 15
2
0 - 15
. . .
0
x
. . .
. . .
. . .
12
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
. . .
. . .
. . .
15
1
x
ID(4) + IEC(2) + RSV(6) + EDC(4)
ECC Block
Number
ID Sector
Number
Row Address
Column Address
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
1
1
1
. . .
. . .
. . .
15
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
0
1
x
x
1
x
x
1
x
x
1
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0 - 15
2
0 - 15
. . .
1
x
. . .
. . .
. . .
12
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
0
1
0
1
0
x
x
x
x
x
x
x
x
. . .
. . .
. . .
15
1
1
Lower 4bits is mapped by sectors
® ID: “0000” - “0001”, IEC: “0010”, RSV: “0011” - “0110”, EDC: “1000” - “1001”
71
KS1453
DVDP DATA PROCESSOR IC
CIRCUIT APPLICATION
4M Bit DRAM
P17-P20, P22-P25, P27-P30, P32-35: DD[15:0]_OUT/
P45-P46, P48- P54: DADR[8:0]_OUT/
P39, P40: ZWE[1:0]_OUT/ P41, P43: ZOE[1:0]_OUT/
P37: ZLCAS_OUT/ P38: ZUCAS_OUT/
P44: ZRAS_OUT
P60-
P66: SDATA[0:6]_OUT
P67: SDATA[7]_BI
(DVD MODE)
MPEG
Decoder
P57: TOS_OUT
P58: DATACK_OUT
P69: CSTROBE_OUT
P70: DATREQ_IN
P71: DTER_OUT
P73-P76, P78-P81:
PWMO[7:0]_OUT
RF
(KS1461)
P60: CDATA
P61: LRCK
P62: BLCK
P63: C2PO
P64: SQDT
P65: WFSY
P66: SOS1
P67: SQCK
(CD MODE)
KS1453
P104: PLCK_IN
P114: FG_IN
P116: EFMI_IN
P106: PLLLOCK_OUT
P107: CLVLOCK_OUT
P108: SERLOCK_OUT
CDG
SERVO
(KS1452)
P98: TEST0_IN
P99: TEST1_IN
P100: TEST2_IN
P122: TEST3_IN
P109: MDP_OUT
P110: MDS_OUT
P113: MON_OUT
P115: FSW_OUT
P5-P12: MDAT[7:0]_BI/
P124: ZRST_IN
P2: ZCS_IN/ P3: MRZA_IN
P125: ZWAIT_OUT/
P126: ZIRQZD_OUT
P127: MRD_IN/
P128: MWR_IN
MICOM
Figure 8. Circuit Application
72
DVDP DATA PROCESSOR IC
KS1453
PACKAGE DIMENSIONS
22.00
20.00
±
±
0.30
0.20
0-8
+ 0.10
0.15 - 0.05
0.10 MAX
128-QFP-1420
#128
+ 0.10
0.20 - 0.05
#1
0.05 MIN
2.10
2.40 MAX
0.50
(0.75)
±
0.10
Figure 9. Package Dimensions
73
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