KS24L161CT [SAMSUNG]
EEPROM, 16KX1, Serial, CMOS, PDSO8, TSSOP-8;
| 型号： | KS24L161CT |
| 厂家： | 
SAMSUNG |
| 描述： | EEPROM, 16KX1, Serial, CMOS, PDSO8, TSSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总20页 (文件大小：144K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS24L161
16K-bit
Serial EEPROM
Data Sheet
OVERVIEW
The KS24L161 serial EEPROM has a 16 Kbits (2,048 bytes) capacity, supporting the standard I2C™-bus serial
interface. It is fabricated using Samsungs’ most advanced CMOS technology. One of its major features is a
hardware-based write protection circuit for the entire memory area. Hardware-based write protection is controlled
by the state of the write-protect (WP) pin. Using one-page write mode, you can load up to 16 bytes of data into
the EEPROM in a single write operation. Another significant feature of the KS24L161 is its support for fast mode
and standard mode.
FEATURES
I2C-Bus Interface
Operating Characteristics
·
·
Two-wire serial interface
·
·
Operating voltage: 2.0 V to 5.5 V
Operating current
Automatic word address increment
— Maximum write current: < 3 mA at 5.5 V
— Maximum read current: < 200 mA at 5.5 V
— Maximum stand-by current: < 2 mA at 2.0 V
Operating temperature range
— – 25°C to + 70°C (commercial)
— – 40°C to + 85°C (i ndustrial)
Operating clock frequencies
EEPROM
·
·
·
16 Kbits (2,048 bytes) storage area
16-byte page buffer
·
·
·
Typical 3 ms write cycle time with
auto-erase function
·
·
Hardware-based write protection for the entire
EEPROM (using the WP pin)
— 100 kHz at standard mode
— 400 kHz at fast mode
EEPROM programming voltage generated
on chip
·
·
1,000,000 erase/write cycles
100 years data retention
Electrostatic discharge (ESD)
— 5,000 V (HBM)
— 400 V (MM)
Packages
8-pin DIP, SOP, and TSSOP
·
5-1
KS24L161 SERIAL EEPROM
DATA SHEET
SDA
HV Generation
Start/Stop
Timing Control
Logic
Control Logic
WP
EEPROM
Cell Array
2,048 x 8 Bits
SCL
Slave Address
Comparator
Word Address
Pointer
Row
Decoder
Column Decoder
Data Register
D
and ACK
OUT
Figure 5-1. KS24L161 Block Diagram
5-2
DATA SHEET
KS24L161 SERIAL EEPROM
VCC WP SCL SDA
KS24L161
A0
A1
A2
VSS
NOTE: The KS24L161 is available in 8-pin DIP, SOP,
and TSSOP package.
Figure 5-2. Pin Assignment Diagram
Table 5-1. KS24L161 Pin Descriptions
Description
Name
Type
Circuit
Type
A0, A1, A2
VSS
–
–
No internal connection
Ground pin.
–
–
SDA
I/O
Bi-directional data pin for the I2C-bus serial data interface. Schmitt
trigger input and open-drain output. An external pull-up resistor
must be connected to VDD.
3
SCL
WP
Input
Input
Schmitt trigger input pin for serial clock input.
2
1
Input pin for hardware write protection control. If you tie this pin to
VCC, the write function is disabled to protect previously written data
in the entire memory; if you tie it to VSS, the write function is
enabled. This pin is internally pulled down to VSS.
VCC
–
Single power supply.
–
NOTE: See the following page for diagrams of pin circuit types 1, 2, and 3.
5-3
KS24L161 SERIAL EEPROM
DATA SHEET
Noise
Filter
SCL
WP
Figure 5-4. Pin Circuit Type 2
Figure 5-3. Pin Circuit Type 1
SDA
Data Out
V
SS
Noise
Filter
Data In
Figure 5-5. Pin Circuit Type 3
5-4
DATA SHEET
KS24L161 SERIAL EEPROM
FUNCTION DESCRIPTION
I2C-BUS INTERFACE
The KS24L161 supports the I2C-bus serial interface data transmission protocol. The two-wire bus consists of a
serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to VCC by a
pull-up resistor that is located somewhere on the bus.
Any device that puts data onto the bus is defined as a “transmitter” and any device that get s data from the bus is
a “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop conditions,
controlling bus access. Only one KS24L161 devices can be connected to the I2C-bus as slaves (see Figure 5-6).
Both the master and slaves can operate as a transmitter or a receiver, but the master device determines which
bus operating mode would be active.
V
CC
V
CC
R
R
SDA
SCL
Master
Slave
MCU
(Transmitter/
Receiver)
KS24L161
Tx/Rx
Figure 5-6. Typical Configuration
5-5
KS24L161 SERIAL EEPROM
DATA SHEET
I2C-BUS PROTOCOLS
Here are several rules for I2C-bus transfers:
— A new data transfer can be initiated only when the bus is currently not busy.
— MSB is always transferred first in transmitting data.
— During a data transfer, the data line (SDA) must remains stable whenever the clock line (SCL) is High.
The I2C-bus interface supports the following communication protocols:
·
·
Bus not busy: The SDA and the SCL lines remain in High level when the bus is not active.
Start condition: A start condition is initiated by a High-to-Low transition of the SDA line while SCL remains in
High level. All bus commands must be preceded by a start condition.
·
Stop condition: A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains in
High level. All bus operations must be completed by a stop condition (see Figure 5-7).
SCL
SDA
Start
Data or
Data
Stop
Condition
ACK Valid
Change
Condition
Figure 5-7. Data Transmission Sequence
·
·
Data valid: Following a start condition, the data becomes valid if the data line remains stable for the duration
of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock
pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total
number of bytes that can be transferred in one operation is theoretically unlimited.
ACK (Acknowledge): An ACK signal indicates that a data transfer is completed successfully. The transmitter
(the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master
generates, the receiver pulls the SDA line low to acknowledge that it has successfully received the eight bits
of data (see Figure 5-8). But the slave does not send an ACK if an internal write cycle is still in progress.
In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors
the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to
transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition
to be issued by the master before returning to its stand-by mode.
5-6
DATA SHEET
KS24L161 SERIAL EEPROM
Master
SCL Line
Bit 1
Bit 9
Data from
Transmitter
ACK from
Receiver
ACK
Figure 5-8. Acknowledge Response From Receiver
·
·
Slave Address: After the master initiates a start condition, it must output the address of the device to be
accessed. The most significant four bits of the slave address are called the “device identifier.” The identifier
for the KS24L161 is “1010B”. The next three bits (B2, B1, B0) are for block selection. They are used by the
master to select which of the blocks of internal memory (1 block=256 words) are to be accessed. (see Table
5-2 below.) These bits are in effect the three most significant bits of the word address.
Read/Write: The final (eighth) bit of the slave address defines the type of operation to be performed. If the
R/W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed.
Table 5-2. Slave Address Byte
Function
Device Identifier
Block Select
R/W Bit
b7 b6 b5 b4
b3
B2
B2
b2
B1
B1
b1
B0
B0
b0
1
Read
Write
1
1
0
0
1
1
0
0
0
5-7
KS24L161 SERIAL EEPROM
BYTE WRITE OPERATION
DATA SHEET
In a complete byte write operation, the master transmits the slave address, word address, and one data byte to
the KS24L161 slave device (see Figure 5-9).
Start
Slave Address
Word Address
Data
Stop
A
C
K
A
C
K
A
C
K
Figure 5-9. Byte Write Operation
Following a start condition, the master sends the device identifier (4 bits), three “dont’ care” bits, and an R /W bit
set to “0” onto the bus. Then the addressed KS24L161 generates an ACK, and waits for the next byte. The next
byte to be transmitted by the master is the word address. This 8-bit address is written into the word address
pointer of the KS24L161.
When the KS24L161 receives the word address, it responds by issuing an ACK and then waits for the next 8-bit
data. When it receives the data byte, the KS24L161 again responds with an ACK. The master terminates the
transfer by generating a Stop condition, at which time the KS24L161 begins the internal write cycle.
While the internal write cycle is in progress, all KS24L161 inputs are disabled and the KS24L161 does not
respond to any additional request from the master.
5-8
DATA SHEET
KS24L161 SERIAL EEPROM
PAGE WRITE OPERATION
The KS24L161 can also perform 16-byte page write operation. A page write operation is initiated in the same way
as a byte write operation. However, instead of finishing the write operation after the first data byte is transferred,
the master can transmit up to 15 additional bytes. The KS24L161 responds with an ACK each time it receives a
complete byte of data (see Figure 5-10).
Start
Slave Address
Word Address n
Data n
Data (<= n + 15)
Stop
...
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 5-10. Page Write Operation
The KS24L161 automatically increments the word address pointer each time it receives a complete data byte.
When one byte is received, the internal word address pointer increments to the next address so that the next data
byte can be received.
If the master transmits more than 16 bytes before it generates a stop condition to end the page write operation,
the KS24L161 word address pointer value “rolls over” and the previously received data is overwritten. If the
master transmits less than 16 bytes and generates a stop condition, the KS24L161 writes the received data to the
corresponding EEPROM address.
During a page write operation, all inputs are disabled and there would be no response to additional requests from
the master until the internal write cycle is completed.
5-9
KS24L161 SERIAL EEPROM
DATA SHEET
POLLING FOR AN ACK SIGNAL
When the master issues a stop condition to initiate a write cycle, the KS24L161 starts an internal write cycle. The
master can then immediately begin polling for an ACK from the slave device to determine whether the write cycle
is completed.
To poll for an ACK signal in a write operation, the master issues a start condition followed by the slave address.
As long as the KS24L161 remains busy with the write operation, no ACK is returned. When the KS24L161
completes the write operation, it returns an ACK and the master can then proceed with the next read or write
operation (see Figure 5-11).
Send write
command
Send Stop condition to
initiate write cycle
Send Start
condition
Send slave address
W
“0
with R/
bit =
”
No
“0”
ACK =
?
Yes
Start next
operation
Figure 5-11. Master Polling for an ACK Signal from a Slave Device
5-10
DATA SHEET
KS24L161 SERIAL EEPROM
HARDWARE-BASED WRITE PROTECTION
You can also write-protect the entire memory area of the KS24L161. This method of write protection is controlled
by the state of the Write Protect (WP) pin.
When the WP pin is connected to VCC, any attempt to write a value to the memory is ignored.
The KS24L161 will acknowledge slave and word address, but it will not generate an acknowledge after receiving
first byte of data. In this situation the write cycle will not be started when a stop condition is generated. By
connecting the WP pin to VSS, the write function is allowed for the entire memory.
These write protection features effectively change the EEPROM to a ROM in order to protect data from being
overwritten. Whenever the write function is disabled, a slave address and a word address are acknowledged on
the bus, but data bytes are not acknowledged.
The WP pin is internally pulled down to VSS.
CURRENT ADDRESS BYTE READ OPERATION
The internal word address pointer maintains the address of the last word accessed, incremented by one.
Therefore, if the last access (either read or write) was to the address “n”, the next read operation would access
data at address “n+1”.
When the KS24L161 receives a slave address with the R/W bit set to “1”, it issues an ACK and sends eight bits of
data. In a current address byte read operation the master does not acknowledge the data, and it generates a
Stop condition, forcing the KS24L161 to stop the transmission (see Figure 5-12).
Start
Slave Address
Data
Stop
A
C
K
N
O
A
C
K
Figure 5-12. Current Address Byte Read Operation
5-11
KS24L161 SERIAL EEPROM
DATA SHEET
RANDOM ADDRESS BYTE READ OPERATION
Using random read operations, the master can access any memory location at any time. Before it issues the
slave address with the R/W bit set to “1”, the mas ter must first perform a “dummy” write operation. This operation
is performed in the following steps:
1. The master first issues a start condition, the slave address, and the word address to be read. (This step sets
the internal word address pointer of the KS24L161 to the desired address.)
2. When the master receives an ACK for the word address, it immediately re-issues a start condition followed
by another slave address, with the R/W bit set to “1”.
3. The KS24L161 then sends an ACK and the 8-bit data stored at the pointed address.
4. At this point, the master does not acknowledge the transmission, generating a stop condition.
5. The KS24L161 stops transmitting data and reverts to stand-by mode (see Figure 5-13).
Slave
Word
Slave
Start
Address
Address
Start
Address
Data (n)
Stop
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 5-13. Random Address Byte Read Operation
5-12
DATA SHEET
KS24L161 SERIAL EEPROM
SEQUENTIAL READ OPERATION
Sequential read operations can be performed in two ways: current address sequential read operation, and
random address sequential read operation. The first data is sent in either of the two ways, current address byte
read operation or random address byte read operation described earlier. If the master responds with an ACK, the
KS24L161 continues transmitting data. If the master does not issue an ACK, generating a stop condition, the
slave stops transmission, ending the sequential read operation.
Using this method, data is output sequentially from address “n” followed by address “n+1”. The word address
pointer for read operations increments to all word addresses, allowing the entire EEPROM to be read sequentially
in a single operation. After the entire EEPROM is read, the word address pointer “rolls over” and the KS24L161
continues to transmit data for each ACK it receives from the master (see Figure 5-14).
Start
Slave Address
Data (n)
Data (n+x)
Stop
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 5-14. Sequential Read Operation
5-13
KS24L161 SERIAL EEPROM
DATA SHEET
ELECTRICAL DATA
Table 5-3. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Unit
VCC
VIN
–
– 0.3 to + 7.0
V
Supply voltage
–
–
– 0.3 to + 7.0
– 0.3 to + 7.0
– 40 to + 85
– 65 to + 150
5000
V
V
Input voltage
VO
Output voltage
°
C
TA
–
Operating temperature
Storage temperature
Electrostatic discharge
°
C
TSTG
VESD
–
HBM
MM
V
400
Table 5-4. D.C. Electrical Characteristics
°
°
°
°
(TA = – 25 C to + 70 C (Commercial), – 40 C to + 85 C (Industrial), VCC = 2.0 V to 5.5 V)
Parameter
Input low voltage
Symbol
Conditions
SCL, SDA
Min
–
Typ
Max
Unit
VIL
0.3 VCC
–
V
V
VIH
ILI
0.7 VCC
–
–
–
–
–
–
–
–
–
–
10
10
0.4
3
Input high voltage
Input leakage current
–
–
–
–
–
–
–
–
VIN = 0 to VCC
µA
µA
V
ILO
VO = 0 to VCC
Output leakage current
Output Low voltage
VOL
ICC1
ICC2
ICC3
ICC4
ICC5
IOL = 3 mA, VCC = 2.0 V
VCC = 5.5 V, 400 kHz
VCC = 2.0 V, 100 kHz
VCC = 5.5 V, 400 kHz
VCC = 2.0 V, 100 kHz
mA
Supply current
Write
1
0.2
60
5
Read
µA
µA
VCC = SDA = SCL = 5.5 V,
all other inputs = 0 V
Stand-by current
ICC6
–
–
2
VCC = SDA = SCL = 2.0 V,
all other inputs = 0 V
5-14
DATA SHEET
KS24L161 SERIAL EEPROM
Table 5-4. D.C. Electrical Characteristics (Continued)
°
°
°
°
(TA = – 25 C to + 70 C (Commercial), – 40 C to + 85 C (Industrial), VCC = 2.0 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CIN
–
–
10
pF
°
Input capacitance
25 C, 1MHz,
VCC = 5 V, VIN = 0 V,
A0, A1, A2, SCL and WP pin
CI/O
–
–
10
°
Input/Output capacitance
25 C, 1MHz,
VCC = 5 V, VI/O = 0 V,
SDA pin
Table 5-5. A.C. Electrical Characteristics
°
°
°
°
(TA = – 25 C to + 70 C (Commercial), – 40 C to + 85 C (Industrial), VCC = 2.0 V to 5.5 V)
Parameter
Symbol Conditions
VCC = 2.0 to 5.5 V
(Standard Mode)
VCC = 4.5 to 5.5 V
(Fast Mode)
Unit
Min
Max
Min
Max
100 (1)
400 (1)
Fclk
tHIGH
tLOW
External clock frequency
Clock High time
–
0
0
kHz
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
–
4
4.7
–
–
–
0.6
1.3
–
–
–
Clock Low time
–
tR
Rising time
SDA, SCL
1
0.3
0.3
–
tF
Falling time
SDA, SCL
–
0.3
–
–
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tSU:STO
tBUF
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Bus free time
–
–
–
–
–
4
0.6
0.6
0
4.7
0
–
–
–
–
0.25
4
–
0.1
0.6
1.3
–
–
–
Before new
4.7
–
–
transmission
tAA
Data output valid from
clock low (2)
–
0.3
3.5
–
0.9
ms
tSP
Noise spike width
Write cycle time
–
–
–
–
100
5
–
–
50
5
ns
tWR
ms
NOTES:
1. Upon customers request, up to 400 kHz (Max.) in standard mode and 1 MHz in fast mode are available.
2. When acting as a transmitter, the KS24L161 must provide an internal minimum delay time to bridge the undefined
period (minimum 300 ns) of the falling edge of SCL. This is required to avoid unintended generation of a start or stop
condition.
5-15
KS24L161 SERIAL EEPROM
DATA SHEET
t
HIGH
t
t
R
F
t
LOW
SCL
t
SU:STO
t
t
t
t
SU:DAT
SU:STA
HD:STA
HD:DAT
SDA IN
t
BUF
t
AA
SDA OUT
Figure 5-15. Timing Diagram for Bus Operations
SCL
SDA
8th Bit
ACK
WORDn
tWR
Stop
Condition
Start
Condition
Figure 5-16. Write Cycle Timing Diagram
5-16
DATA SHEET
KS24L161 SERIAL EEPROM
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements. They do
not, however, represent guaranteed operating values.
(Frequency = 100 kHz)
2.0
1.6
Temp = -40 C
Temp = -25 C
1.2
I
(mA)
Temp = 25 C
Temp = 70 C
Temp = 85 C
CC
0.8
0.4
0
1.5
2.5
3.5
V
4.5
5.5
(V)
CC
Figure 5-17. Write Current
5-17
KS24L161 SERIAL EEPROM
DATA SHEET
(Frequency = 100 kHz)
140
120
100
80
Temp = -40 C
Temp = -25 C
Temp = 25 C
Temp = 70 C
Temp = 85 C
I
(uA)
CC
60
40
20
0
1.5
2.5
3.5
4.5
5.5
V
(V)
CC
Figure 5-18. Read Current
(Frequency = 100 kHz)
1.5
1.2
0.9
0.6
0.3
0
I
(uA)
CC
Temp = -40 C
Temp = -25 C
Temp = 25 C
Temp = 70 C
Temp = 85 C
1.5
2.5
3.5
4.5
5.5
V
(V)
CC
Figure 5-19. Stand-by Current
5-18
DATA SHEET
KS24L161 SERIAL EEPROM
(T = 25 C)
A
70
60
50
40
30
20
10
0
V
V
= 6 V
= 5 V
DD
DD
V
V
= 4 V
= 3 V
DD
DD
I
(mA)
OL
V
= 2 V
DD
0
1
2
3
4
5
6
V
(V)
OL
Figure 5-20. Output Low Voltage
5-19
KS24L161 SERIAL EEPROM
DATA SHEET
NOTES
5-20
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