KS57C0002IS [SAMSUNG]
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SAMSUNG 
KS57C0002/0004
S MSUNG
4-BIT CMOS Microcontroller
Product Specification
OVERVIEW
The KS57C0002/0004 single-chip CMOS microcontroller is designed for high-performance using Samsung's
newest 4-bit CPU core. With a four-channel comparator, eight LED direct drive pins, serial I/O interface, and a
versatile
8-bit timer/countkxcellent design solution for a variety of general-purpose applications.
Up to 24 pins of the 30-pin SDIP package can be dedicated to I/O. Five vectored interrupts provide fast response
to internal and external events. In addition, the KS57C0002/0004's advanced CMOS technology ensures low
power consumption and a wide operating voltage range.
FEATURES
Memory
•
Stop mode (system clock
stops)
Watch Timer
•
256 × 4-bit data memory
(KS57C0002)
•
Interval generation: 0.5 s,
3.9ms at 32768 Hz
Oscillation Sources
512 × 4-bit data memory
(KS57C0004)
•
Four frequency outputs to the
BUZ pin
•
Crystal, ceramic, or RC for
system clock (RC is only for
the KS57C0002)
•
2048 × 8-bit program memory
(KS57C0002)
8-Bit Serial I/O Interface
4096 × 8-bit program memory
(KS57C0004)
•
Crystal, ceramic: 4.19 MHz
(typical)
•
•
•
8-bit transmit/receive mode
8-bit receive-only mode
•
•
RC: 1 MHz
24 I/O Pins
LSB-first or MSB-first
transmission selectable
CPU clock divider circuit
(by 4, 8, or 64)
•
I/O: 18 pins, including 8 high-
current pins
•
Internal or external clock
source
•
Input only: 6 pins
Instruction Execution Times
•
0.95, 1.91, 15.3 µs at 4.19
MHz
Comparator
Bit Sequential Carrier
•
4-channel mode with internal
•
Support for 16-bit serial data
transfer in arbitrary format
reference (4-bit resolution)
and 16-step variable
reference voltage
Operating Temperature
°
°
•
– 40 C to 85 C
Operating Voltage Range
2.7 V to 6.0 V
Package Type
30 SDIP, 32 SOP
Interrupts
•
•
3-channel mode with external
reference
•
•
Two external interrupt vectors
•
Three internal interrupt
vectors
150 mV resolution (minimum)
8-Bit Basic Timer
Programmable interval timer
8-Bit Timer/Counter
•
Two quasi-interrupts
•
•
Memory-Mapped I/O Structure
Data memory bank 15
Power-Down Modes
•
•
•
Programmable interval timer
External event counter
function
•
Idle mode (only CPU clock
stops)
•
Timer/counter clock output to
TCLO0 pin
2–1
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
BASIC
TIMER
WATCH
TIMER
RESET
Xin
Xout
8-BIT
TIMER/
P0.0 / SCK
I/O PORT 0
COUNTER
P0.1 / SO
P0.2 / SI
INTERRUPT
CONTROL
BLOCK
STACK
POINTER
CLOCK
P3.0 / TCL0
P3.1 / TCLO0
P3.2 / CLO
SERIAL
I/O
PORT
I/O PORT 3
PROGRAM
COUNTER
INTERNAL
INTERRUPTS
INPUT
PORT 1
P1.0 / INT0
P1.1 / INT1
PROGRAM
STATUS
WORD
I/O PORT 4
I/O PORT 5
P4.0–P4.3
P5.0–P5.3
INSTRUCTION
DECODER
P2.0 / CIN0
P2.1 / CIN1
P2.2 / CIN2
P2.3 / CIN3
INPUT
PORT 2
ARITHMETIC
LOGIC UNIT
P6.0 / KS0
P6.1 / KS1
P6.2 / KS2
P6.3 / BUZ
FLAGS
I/O PORT 6
COMPARATOR
2 K/ 4 K
BYTE
256 / 512
x 4-BIT
PROGRAM
MEMORY
DATA
MEMORY
a
Figure 1. KS57C0002/0004 Block Diagram
P0.0 / SCK
1
30
29
28
27
26
25
24
P0.0/SCK
P0.1/SO
P0.2/SI
1
32
31
30
29
28
27
VDD
VDD
A
P0.1 / SO
P0.2 / SI
2
2
P6.3/BUZ
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P6.3 / BUZ
P6.2 / KS2
P6.1 / KS1
P6.0 / KS0
P5.3
3
3
P1.0 / INT0
P1.1 / INT1
P2.0 / CIN0
P2.1 / CIN1
P2.2 / CIN2
P2.3 / CIN3
P3.0 / TCL0
4
P1.0/INT0
NC
4
5
5
6
P1.1/INT1
P2.0/CIN0
P2.1/CIN1
P2.2/CIN2
P2.3/CIN3
P3.0/TCL0
P3.1/TCLO0
P3.2/CLO
RESET
6
7
KS57C0002/04 26
7
P5.2
KS57C0002/04
P5.2
8
(Top View) 23
8
25
P5.1
P5.1
(Top View)
9
22
21
20
19
18
17
16
9
24
23
22
21
20
19
18
17
P5.0
P5.0
10
11
12
13
14
15
10
11
12
13
14
15
16
P4.3
P4.3
P3.1 / TCLO0
P3.2 / CLO
RESET
P4.2
P4.2
NC
P4.1
P4.1
P4.0
TEST
P4.0
Xout
VSS
TEST
Xout
Xin
VSS
Xin
30 SDIP
32 SOP
Figure 2. KS57C0002/0004 Pin Assignments (32 SOP, 30 SDIP)
S MSUNG
ELECTRONICS
September 1996
2–2
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 1. KS57C0002/0004 Pin Descriptions
Pin Name
P0.0
P0.1
P0.2
Pin Type
Description
Number
Share Pin
I/O
3-bit I/O port. 1-bit or 3-bit read/write and test is
possible. Pull-up resistors are assignable to input pins
by software and are automatically disabled for output
pins. Pins are individually configurable as input or
output.
1
2
3
SCK
SO
SI
P1.0
P1.1
I
2-bit input port. 1-bit or 2-bit read and test is possible.
Pull-up resistors are assignable by software.
4
5
INT0
INT1
P2.0–P2.3
I
4-bit input port. 1-bit or 4-bit read and test is possible.
Same as port 0
6–9
CIN0–CIN3
P3.0
P3.1
P3.2
I/O
10
11
12
TCL0
TCLO0
CLO
P4.0–P4.3
P5.0–P5.3
I/O
I/O
4-bit I/O ports.
18–21
22–25
—
1-, 4-, or 8-bit read/write and test is possible.
Pins are individually configurable as input or output.
Ports can be configurable as n-channel open-drain by
mask option (maximum 9V).
P6.0
P6.1
P6.2
P6.3
4-bit I/O port.
26
27
28
29
KS0
KS1
KS2
BUZ
1-bit or 4-bit read/write and test is possible.
Pull-up resistors are assignable to input pins by
software and are automatically disabled for output
pins. Pins individually configurable as input or output.
INT0
I
I
I
External interrupts with rising/falling edge detection
External interrupts with rising/falling edge detection
4
5
P1.0
P1.1
INT1
CIN0–CIN3
4-channel comparator input.
6–9
P2.0–P2.3
CIN0–CIN2: comparator input only.
CIN3: comparator input or external reference input
SCK
SO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Serial interface clock signal
Serial data output
1
2
P0.0
P0.1
P0.2
P3.0
P3.1
P3.2
P6.3
SI
Serial data input
3
TCL0
TCLO0
CLO
BUZ
External clock input for timer/counter
Timer/counter clock output
CPU clock output
10
11
12
29
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at
4.19 MHz for buzzer sound
KS0–KS2
I/O
—
—
I
Quasi-interrupt input with falling edge detection
26–28
30
P6.0–P6.2
V
V
Main power supply
Ground
—
—
—
—
—
DD
SS
15
RESET
TEST
Reset signal
13
I
Test signal input (must be connected to V
)
14
SS
X , X
in out
—
Crystal, ceramic, or RC oscillator signal for system
clock
16, 17
S MSUNG
ELECTRONICS
2–3
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 2. Supplemental KS57C0002/0004 Pin Data
Pin Numbers
1, 2, 3
Pin Names
P0.0–P0.2
Share Pins
I/O Type
Reset Value
Input
Input
Input
Input
—
Circuit Type
SCK, SO, SI
I/O
I
5
3
4, 5
P1.0, P1.1
P2.0–P2.3
P3.0–P3.2
RESET
INT0, INT1
6–9
CIN0–CIN3
I
6, 8 *
5
10–12
13
TCL0, TCLO0, CLO
I/O
I
—
—
—
—
—
—
9
14
TEST
I
—
—
—
—
7
15
V
—
—
I/O
I/O
I/O
—
SS
16, 17
18–21
22–25
26–29
Xin, Xout
—
P4.0–P4.3
P5.0–P5.3
P6.0–P6.3
Input
Input
Input
7
KS0, KS1, KS2,
BUZ
5
30
V
—
—
—
—
DD
*
I/O circuit type 8 is for P2.3 only.
S MSUNG
ELECTRONICS
September 1996
2–4
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
VDD
VDD
P-CHANNEL
OUT
P-CHANNEL
N-CHANNEL
DATA
IN
N-CHANNEL
OUTPUT
DISABLE
Figure 6. Pin Circuit Type 4
Figure 3. Pin Circuit Type 1
VDD
PULL-UP
RESISTOR
RESISTOR
ENABLE
P-CHANNEL
I/O
IN
DATA
CIRCUIT
TYPE 4
SCHMITT TRIGGER
OUTPUT
DISABLE
CIRCUIT TYPE 2
Figure 7. Pin Circuit Type 5
Figure 4. Pin Circuit Type 2
VDD
PULL-UP
RESISTOR
DIGITAL INPUT
RESISTOR
ENABLE
P-CHANNEL
IN
ANALOG INPUT
SCHMITT TRIGGER
Figure 5. Pin Circuit Type 3
Figure 8. Pin Circuit Type 6
S MSUNG
ELECTRONICS
2–5
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
VDD
DIGITAL INPUT
ANALOG INPUT
EXTERNAL VREF
P-CHANNEL
DATA
(MASK
OPTION)
N-CHANNEL
OUTPUT
DISABLE
MAXIMUM INPUT VOLTAGE: 9 V
Figure 10. Pin Circuit Type 8
Figure 9. Pin Circuit Type 7
VDD
IN
Schmitt Trigger Input
Figure 11. Pin Circuit Type 9
S MSUNG
ELECTRONICS
September 1996
2–6
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PROGRAM MEMORY (ROM)
— 16-byte general-purpose area
— 16-byte area for vector addresses
— 96-byte instruction reference area
ROM maps for KS57C0002/0004 devices are mask
programmable at the factory. In their standard
configuration, the device's 2048 × 8-bit (KS57C0002),
or 4096 × 8-bit (KS57C0004) program memory has
four areas that are directly addressable by the
program counter ( PC):
— 1920-byte (KS57C0002), 3968-byte (KS57C0004)
general-purpose area
0000H
VECTOR
ADDRESS AREA
7
6
5
4
3
2
1
0
000FH
0010H
RESET
INTB
INT0
0000H
0002H
0004H
0006H
0008H
000AH
GENERAL-PURPOSE
AREA
001FH
0020H
INSTRUCTION
REFERENCE AREA
007FH
0080H
INT1
GENERAL-PURPOSE
INTS
INTT0
KS57C0002
07FFH
AREA 1
0800H
0FFFH
KS57C0004
GENERAL-PURPOSE
AREA 2
Figure 12. ROM Map
Figure 13. Vector Address Map
— 256×4 -bit general-purpose area in bank1
DATA MEMORY (RAM)
(KS57C0004 only)
In its standard configuration, the 256× 4 -bit
(KS57C0002), or the 512 ×4-bit (KS57C0004) data
memory has four areas:
— 128× 4-bit area in bank 15 for memory-mapped
I/O addresses
I/O MAP FOR HARDWARE REGISTERS
— 32 ×4-bit working registers
Table 3 contains detailed information about I/O
mapping for peripheral hardware in bank 15 (register
locations F80H–FFFH).
— 224× 4-bit general-purpose area in bank0 which
is also used as the stack area
S MSUNG
ELECTRONICS
2–7
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
DA
DA.b
ADDRESSING
MODE
@HL
@H + DA.b
@WX
@WL
mema.b memb.@L
RAM
AREAS
EMB = 0 EMB = 1
EMB = 0
EMB = 1
X
X
X
000H
WORKING
REGISTERS
01FH
020H
SMB = 0
SMB = 0
BANK 0
(GENERAL
REGISTERS
AND STACK)
07FH
080H
0FFH
100H
BANK 1
KS57C0004
ONLY
SMB = 1
SMB = 1
(GENERAL
REGISTERS)
1FFH
F80H
FB0H
BANK 15
FBFH
FC0H
(PERIPHERAL
HARDWARE
REGISTERS)
SMB = 15
SMB = 15
FF0H
FFFH
NOTES: 1. 'X' means don't care.
2. Blank columns indicate RAM areas that are not addressable, given the addressing method
and enable memory bank (EMB) flag setting shown in the column headers.
Figure 14. Data Memory (RAM) Address Structure
S MSUNG
ELECTRONICS
September 1996
2–8
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Addressing Mode
Table 3. I/O Map for Memory Bank 15
Memory Bank 15
Register
Address
F81H–F80H
F85H
Name
R/W
R/W
W
1-Bit
No
4-Bit
No
8-Bit
Yes
No
SP
Stack Pointer
BMOD
BCNT
WMOD
TMOD0
TCNT0
TREF0
PSW
Basic Timer Mode Register
Basic Timer Counter Register
Watch Timer Mode Register
Timer/Counter 0 Mode Register
Timer/Counter 0 Counter Register
Timer/Counter 0 Reference Reg
.3
Yes
No
F87H–F86H
F89H–F88H
F91H–F90H
F95H–F94H
F97H–F96H
FB0H
R
No
Yes
Yes
Yes
Yes
Yes
Yes
W
No
No
W
.3
No
R
No
No
W
No
No
IS1
IS0
EMB
SC1
ERB
SC0
R/W
R
Yes
No
Yes
No
(2)
FB1H
SC2
C
FB2H
IPR
SIO Mode Register
W
IME
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
FB3H
PCON
IMOD0
IMOD1
IMODK
Power Control Register
W
FB4H
External Interrupt 0 Mode Register
External Interrupt 1 Mode Register
External Key Interrupt Mode Reg
W
No
FB5H
W
No
FB6H
W
No
FB8H
"0"
"0"
"0"
"0"
IE1
"0"
"0"
"0"
IEB
IEW
IET0
IES
IE0
IRQB
R/W
R/W
Yes
Yes
Yes
FBAH
IRQW
FBCH
"0"
IRQT0 R/W
IRQS
FBDH
"0"
FBEH
IRQ1
"0"
IRQ0
FBFH
IEK
IRQK
FC0H
BSC0
BSC1
Bit Sequential Carrier 0
Bit Sequential Carrier 1
Bit Sequential Carrier 2
Bit Sequential Carrier 3
Clock Mode Register
R/W
Yes
Yes
Yes
FC1H
FC2H
BSC2
FC3H
BSC3
FD0H
CLMOD
CMPREG
CMOD
PUMOD
SMOD
P2MOD
SBUF
W
R
No
No
No
No
.3
Yes
Yes
No
No
No
FD4H
Comparison Result Register
Comparator Mode Register
Pull-up Mode Register
SIO Mode Register
FD7H–FD6H
FDDH–FDCH
FE1H–FE0H
FE2H
R/W
W
Yes
Yes
Yes
No
No
W
No
Port 2 Mode Register
SIO Buffer Register
W
No
No
No
Yes
No
FE5H–FE4H
FE9H–FE8H
FEBH–FEAH
R/W
W
Yes
Yes
PMG1
Port Mode Group 1
No
PMG2
Port Mode Group 2
S MSUNG
ELECTRONICS
2–9
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Addressing Mode
Table 3. I/O Map for Memory Bank 15 (Concluded)
Memory Bank 15
Address
FEDH–FECH
FF0H
Register
PMG3
P0
Name
Port Mode Group 3
Port 0
R/W
W
1-Bit
No
4-Bit
No
8-Bit
Yes
No
R/W
R
Yes
Yes
FF1H
P1
Port 1
No
FF2H
P2
Port 2
R
No
FF3H
P3
Port 3
R/W
R/W
R/W
R/W
No
FF4H
P4
Port 4
Yes
FF5H
P5
Port 5
FF6H
P6
Port 6
No
NOTES:
1. Bit 0 in the WMOD register must be set to "0".
2. The carry flag can be read or written by specific bit manipulation instructions only.
S MSUNG
ELECTRONICS
September 1996
2–10
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
incrementing or decrementing the value of the L
register.
BIT SEQUENTIAL CARRIER (BSC)
The bit sequential carrier (BSC) is a 16-bit general
register that is mapped in data memory bank 15.
Using the BSC, you can specify sequential addresses
and bit locations using 1-bit indirect addressing
(memb.@L).
For 8-bit manipulations, the 4-bit register names
BSC0 and BSC2 must be specified and the upper and
lower 8 bits manipulated separately. If the values of
the L register are 0H at BSC0.@L, the address and bit
location assignment is FC0H.0. If the L register
content is FH at BSC0.@L, the address and bit
location assignment is FC3H.3.
BSC bit addressing is independent of the current EMB
value. In this way, programs can process 16-bit data
by moving the bit location sequentially and then
Table 4. BSC Register Organization
Name
BSC0
BSC1
BSC2
BSC3
Address
FC0H
Bit 3
Bit 2
Bit 1
Bit 0
BSC0.3
BSC1.3
BSC2.3
BSC3.3
BSC0.2
BSC1.2
BSC2.2
BSC3.2
BSC0.1
BSC1.1
BSC2.1
BSC3.1
BSC0.0
BSC1.0
BSC2.0
BSC3.0
FC1H
FC2H
FC3H
☞
PROGRAMMING TIP — Using the BSC Register to Output 16-Bit Data
To use the bit sequential carrier (BSC) register to output 16-bit data (5937H) to the P3.0 pin:
BITS
SMB
LD
LD
LD
LD
SMB
LD
EMB
15
EA,#37H
BSC0,EA
EA,#59H
BSC2,EA
0
;
;
;
;
BSC0 ← A, BSC1 ← E
BSC2 ← A, BSC3 ← E
L,#0H
;
;
;
AGN LDB
C,BSC0.@L
LDB
INCS
JR
P3.0,C
L
AGN
P3.0 ← C
RET
S MSUNG
ELECTRONICS
2–11
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
INTERRUPTS
The KS57C0002/0004 microcontroller has two external interrupts, three internal interrupts, and two quasi-
interrupts. Table 5 shows the conditions for each interrupt generation. The request flags that actually generate
these interrupts are cleared by hardware when the service routine is vectored. However, the quasi-interrupt's
request flags must be cleared by software.
IMOD1
IMOD0
IEW
IET0
IES
IE1
IE0
IEK
IEB
INTB
IRQB
IRQ0
IRQ1
IRQS
IRQT0
IRQW
IRQK
INT0
INT1
#
@
@
INTS
INTT0
INTW
INTK (KS0–KS2)
IMODK
POWER-DOWN
MODE
RELEASE SIGNAL
IME
IPR
INTERRUPT CONTROL UNIT
IS1 IS0
VECTOR INTERRUPT
GENERATOR
# = Noise filtering circuit
@ = Edge detection circuit
Figure 15. Interrupt Control Circuit Diagram
S MSUNG
ELECTRONICS
September 1996
2–12
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 5. Interrupt Request Flag Conditions and Priorities
Interrupt
Source
Internal /
External
Condition for IRQx Flag Setting
Interrupt
Priority
Request Flag
Name
INTB
INT0
INT1
INTS
I
E
E
I
Reference time interval signal from basic timer
Rising or falling edge detected at INT0 pin
Rising or falling edge detected at INT1 pin
1
2
3
4
IRQB
IRQ0
IRQ1
IRQS
Completion signal for serial transmit-and-receive
or receive-only operation
INTT0
I
Signals for TCNT0 and TREF0 registers match
5
IRQT0
IRQK
INTK *
E
Falling edge is detected at any of the KS0–KS2
pins
—
INTW *
I
Time interval of 0.5 s or 3.19 ms
—
IRQW
*
The INTK and INTW are quasi-interrupts and INTK are used only for testing incoming signals.
INTERRUPT ENABLE FLAGS (IEx)
INTERRUPT PRIORITY
IEx flags, when set to "1", enable specific interrupt
requests to be serviced. When the interrupt request
flag is set to "1", an interrupt will not be serviced until
its corresponding IEx flag is also enabled. The IPR
register contains a global disable bit, IME, which
disables all interrupt at once.
Each interrupt source can also be individually
programmed to high levels by modifying the IPR
register. When IS1 = 0 and IS0 = 1, a low-priority
interrupt can itself be interrupted by a high-priority
interrupt, but not by another low-priority interrupt.
If you clear the interrupt status flags (IS1 and IS0) to
"0" in a interrupt service routine, a high-priority
interrupt can be interrupted by low-priority interrupt
(multi-level interrupt). Before the IPR can be modified
by 4-bit write instructions, all interrupts must first be
disabled by a DI instruction.
Table 6. Interrupt Enable and Request Flag
Address
FB8H
Bit 3
Bit 2
Bit 1
IEB
IEW
0
Bit 0
IRQB
IRQW
0
0
0
0
FBAH
FBBH
FBCH
FBDH
FBEH
FBFH
0
When all interrupts are low priority (the lower three
bits of the IPR register are "0"), the interrupt
requested first will have high priority. Therefore, the
first-requested interrupt cannot be superseded by any
other interrupt.
0
0
0
0
0
IET0
IES
IE0
IEK
IRQT0
IRQS
IRQ0
IRQK
0
IE1
0
IRQ1
0
If two or more interrupt requests are received
simultaneously, the priority level is determined
according to the standard interrupt priorities, where
the default priority is assigned by hardware when the
lower three IPR bits = "0".
NOTES:
1. IEx refers to all interrupt enable flags.
2. IRQx refers to all interrupt request flags.
3. IEx = "0" is interrupt disable mode.
4. IEx = "1" is interrupt enable mode.
S MSUNG
ELECTRONICS
2–13
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
In this case, the higher-priority interrupt request is
serviced and the other interrupt is inhibited. Then,
when the high-priority interrupt is returned from its
service routine by an IRET instruction, the inhibited
service routine is started.
EXTERNAL INTERRUPTS
The external interrupt mode registers (IMOD0 and
IMOD1) are used to control the triggering edge of the
input signal at the INT0 and INT1 pins, respectively.
When a sampling clock rate of fx/64 is used for INT0,
an interrupt request flag must be cleared before 16
machine cycles have elapsed. Since the INT0 pin has
a clock-driven noise filtering circuit built into it, please
take the following precautions when you use it:
Table 7. Interrupt Priority Register Settings
IPR.2 IPR.1 IPR.0 Result of IPR Bit Setting
0
0
0
Process all interrupt
requests at low priority.
— To trigger an interrupt, the input signal width at
INT0 must be at least two times wider than the
pulse width of the clock selected by IMOD0. This
is true even when the INT0 pin is used for
general-purpose input.
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
INTB
INT0
INT1
INTS
INTT0
— Since the INT0 input sampling clock does not
operate during Stop or Idle mode, you cannot use
INT0 to release power-down mode.
When modifying the IMOD0 and IMOD1 registers, it is
possible to accidentally set an interrupt request flag.
Table 8. Default Priorities
Source
INTB
Default Priority
To avoid unwanted interrupts, take these precautions
when writing your programs:
1
2
3
4
5
INT0
1. Disable all interrupts with a DI instruction.
2. Modify the IMOD0 or IMOD1 register.
3. Clear all relevant interrupt request flags.
INT1
INTS
INTT0
4. Enable the interrupt by setting the appropriate IEx
flag.
5. Enable all interrupts with an EI instructions.
Table 9. IMOD0 and IMOD1 Register Organization (4-Bit W)
IMOD0.3
0
IMOD0.1
IMOD0.0
Effect of IMOD0 Settings
Select CPU clock for sampling
0
1
Select fx/64 sampling clock
Rising edge detection
0
0
0
0
0
0
1
1
0
1
0
1
Falling edge detection
Both rising and falling edge detection
IRQ0 flag cannot be set to "1"
0
0
0
0
0
0
0
0
0
IMOD1.0
Effect of IMOD1 Settings
Rising edge detection
0
1
Falling edge detection
S MSUNG
ELECTRONICS
September 1996
2–14
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
EXTERNAL KEY INTERRUPT MODE REGISTER
The external key interrupt (INTK) mode register, IMODK, is used to select KS pins as interrupt input pins. When a
falling edge is detected at one of the KS0–KS2 pins, the IRQK flag is set to "1". This generates an interrupt
request and a release signal for power-down mode. To generate a key interrupt on a falling signal edge at KS0–
KS2, all of the KS0–KS2 pins must be configured to input mode.
If one or more of the pins which are configured as key Interrupt (KS0–KS2) are in Low input or Low output state,
the key Interrupt can not be occurred.
Table 10. IMODK Register Bit Settings (4-Bit W)
0
0
0
0
0
0
0
0
0
IMODK.2
IMODK.1
IMODK.0
Effect of IMODK Settings
Disable key interrupt
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Select falling edge at KS0
Select falling edge at KS1
Select falling edge at KS0–KS1
Select falling edge at KS2
Select falling edge at KS0, KS2
Select falling edge at KS1–KS2
Select falling edge at KS0–KS2
KS2
KS1
KS0
FALLING
EDGE
DETECTION
CIRCUIT
IMODK
IRQK
NOTE: To generate a key interrupt on a falling edge at KS0–KS2, all KS0–KS2 pins must be
configured to input mode.
Figure 15-1. Circuit diagram for KS0-KS2 Pins
S MSUNG
ELECTRONICS
2–15
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
OSCILLATOR CIRCUITS
The KS57C0002/0004 system clock circuit is shown in Figure 16 below. By manipulating bits 1 and 0 of the
PCON register, the system clock frequency can be divided by 4, 8, or 64.
SYSTEM
OSCILLATOR
CIRCUIT
fx
Xin
Xout
WATCH TIMER
BASIC TIMER
TIMER/COUNTER 0
CLOCK OUTPUT CIRCIT
COMPARATOR
FREQUENCY
DIVIDING
CIRCUIT
OSCILLATOR
STOP
1/2
1/16
CPU
CLOCK
SELECTOR
1/4
CPU STOP SIGNAL
( IDLE MODE)
PCON.0
PCON.1
PCON.2
PCON.3
IDLE
WAIT RELEASE SIGNAL
OSCILLATOR
CONTROL
CIRCUIT
INTERNAL RESET SIGNAL
STOP
POWER-DOWN RELEASE SIGNAL
PCON.3,2 CLEAR
Figure 16. Clock Circuit Diagram
S MSUNG
ELECTRONICS
September 1996
2–16
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Xin
Xin
Xin
R
Xout
Xout
Xout
Figure 17. Crystal/Ceramic
Oscillator
Figure 18. External Clock
Figure 19. RC Oscillator (only
for the KS57C0002)
POWER CONTROL REGISTER (PCON)
The power control register, PCON, is used to select the CPU clock frequency and to control CPU operating and
power-down modes. PCON bits 3 and 2 are controlled by the STOP and IDLE instructions, which engage the
Stop and Idle power-down modes, respectively. Using these instructions, you can initiate a power-down mode at
any time, regardless of the current value of the enable memory bank flag (EMB).
Table 11. Power Control Register (PCON) Organization (4-Bit W)
PCON Bit Settings
Resulting CPU Operating Mode
PCON.3
PCON.2
0
0
1
0
1
0
Normal CPU operating mode
Idle power-down mode
Stop power-down mode
PCON Bit Settings
Resulting CPU Clock Frequency
PCON.1
PCON.0
0
1
1
0
0
1
fx/64
fx/8
fx/4
☞
PROGRAMMING TIP — Setting the CPU Clock
To set the CPU clock to 0.95 µs at 4.19 MHz:
BITS
SMB
LD
EMB
15
A,#3H
PCON,A
LD
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ELECTRONICS
2–17
September 1996
KS57C0002 /0004 MICROCONTROLLER
INSTRUCTION CYCLE TIMES
PRODUCT SPECIFICATION
The unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided.
Table 12. Instruction Cycle Times for CPU Clock Rates
Selected
CPU Clock
Resulting Frequency
Oscillation
Source
Cycle Time (µs)
fx/64
fx/8
65.5 kHz
524.0 kHz
1.05 MHz
15.3
1.91
0.95
fx = 4.19 MHz
fx/4
CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulses to the CLO pin. The clock output mode register, CLMOD, is used to
enable or disable clock output to the CLO pin and to select the CPU clock source and frequency. To output a
frequency, the clock output pin CLO/P3.2 must be set to output mode and the pin's latch must be cleared to "0".
Bit 2 in the CLMOD register must always be "0".
Table 13. Clock Output Mode Register (CLMOD) Organization
CLMOD Bit Settings
Resulting Clock Output
CLMOD.1
CLMOD.0
Clock Source
Frequency
1.05 MHz, 524 kHz, 65.5 kHz
524 kHz
0
0
1
1
0
1
0
1
CPU clock (fx/4, fx/8, fx/64)
fx/8
fx/16
fx/64
262 kHz
65.5 kHz
CLMOD.3
Result of CLMOD.3 Setting
0
1
Clock output is disabled
Clock output is enabled
NOTE: Frequencies assume that fx = 4.19 MHz.
CLMOD.3
CLO
CLMOD.2
4
CLMOD.1
CLOCK
P3.2 OUTPUT LATCH
PM3.2
SELECTOR
CLMOD.0
CLOCKS
(fx/8, fx/16, fx/64, CPU clock)
Figure 20. CLO Output Pin Circuit Diagram
S MSUNG
ELECTRONICS
September 1996
2–18
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞
PROGRAMMING TIP — CPU Clock Output to the CLO Pin
To output the CPU clock to the CLO pin:
BITS
SMB
LD
LD
BITR
LD
EMB
15
EA,#40H
PMG1,EA
P3.2
A,#9H
CLMOD,A
;
Or BITR EMB
;
;
P3.2 ← Output mode
Clear P3.2 output latch
LD
POWER-DOWN
In Stop mode, system clock oscillation is halted
(assuming it is currently operating), and peripheral
hardware components are powered-down. The effect
of Stop mode on specific peripheral hardware
components — CPU, basic timer, serial I/O, timer/
counters 0, and watch timer — and on external
interrupt requests, is detailed in Table 14.
The KS57C0002/0004 microcontroller has two power-
down modes to reduce power consumption: Idle and
Stop. In Idle mode, the CPU clock stops while
peripherals and the oscillator continue to operate
normally.
Table 14. Hardware Operation During Power-Down Modes
Operation
Clock oscillator
Stop Mode (STOP)
Idle Mode (IDLE)
System clock oscillation stops
CPU clock oscillation stops (system clock
oscillation continues)
Basic timer
Basic timer stops
Basic timer operates (with IRQB set at
each reference interval)
Serial interface
Timer/counter 0
Operates only if external SCK input is
selected as the serial I/O clock
Operates if a clock other than the CPU
clock is selected as the serial I/O clock
Operates only if TCL0 is selected as the Timer/counter 0 operates
counter clock
Comparator
Comparator operation is stopped
Watch timer operation is stopped
Comparator operates
Watch timer operates
Watch timer
External interrupts
INT1 and INTK are acknowledged; INT0 INT1 and INTK are acknowledged;
is not serviced
INT0 is not serviced
CPU
All CPU operations are disabled
All CPU operations are disabled
Power-down mode
release signal
Interrupt request signals (except INT0)
are enabled by an interrupt enable flag or are enabled by an interrupt enable flag or
by RESET input by RESET input
Interrupt request signals (except INT0)
S MSUNG
ELECTRONICS
2–19
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
RECOMMENDED CONNECTIONS FOR UNUSED PINS
To reduce overall power consumption, please configure unused pins according to the guidelines described in
Table 15.
Table 15. Unused Pin Connections for Reduced Power Consumption
Pin/Share Pin Names
P0.0 / SCK
Recommended Connection
Input mode: Connect to V
DD
P0.1 / SO
P0.2 / SI
Output mode: Do not connect
P1.0 / INT0 – P1.1 / INT1
Connect to V
Connect to V
DD
DD
P2.0 / CIN0
P2.1 / CIN1
P2.2 / CIN2
P2.3 / CIN3
P3.0 / TCLO0
P3.1 / TCLO1
P3.2 / CLO
Input mode: Connect to V
DD
Output mode: Do not connect
P3.3 / BUZ
P4.0–P4.3, P5.0–P5.3
P6.0 / KS0 – P6.3 / BUZ
TEST
Connect to V
SS
RESET
Table 16 provides detailed information about hardware register values after a RESET occurs during power-down
mode or during normal operation.
RESET
Table 16. Hardware Register Values After
RESET
Power-Down Mode
RESET
Occurs During
Normal Operation
Hardware Component
or Subcomponent
If
Occurs During
If
Program counter (PC)
Lower three bits of address 0000H Lower three bits of address 0000H
are transferred to PC10–8, and the are transferred to PC10–8, and the
contents of 0001H to PC7–0.
contents of 0001H to PC7–0.
Program Status Word (PSW):
Carry flag (C)
Retained
Undefined
Skip flag (SC0–SC2)
0
0
0
0
Interrupt status flags (IS0, IS1)
Bank enable flags (EMB, ERB)
Bit 6 of address 0000H in program Bit 6 of address 0000H in program
memory is transferred to the ERB memory is transferred to the ERB
flag, and bit 7 of the address to the flag, and bit 7 of the address to the
EMB flag.
EMB flag.
Stack pointer (SP)
Undefined
Undefined
S MSUNG
ELECTRONICS
September 1996
2–20
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
RESET
Table 16. Hardware Register Values After
(Continued)
RESET
Power-Down Mode
RESET
Occurs During
Normal Operation
Hardware Component
or Subcomponent
If
Occurs During
If
Data Memory (RAM):
General registers E, A, L, H, X, W, Z,
Y
Values retained
Undefined
(Note 1)
General-purpose registers
Undefined
Values retained
Bank selection registers (SMB, SRB)
BSC register (BSC0–BSC3)
0, 0
0
0, 0
0
Clocks:
Power control register (PCON)
0
0
0
0
Clock output mode register (CLMOD)
Interrupts:
Interrupt request flags (IRQx)
Interrupt enable flags (IEx)
Interrupt priority flag (IPR)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Interrupt master enable flag (IME)
INT0 mode register (IMOD0)
INT1 mode register (IMOD1)
INTK mode register (IMODK)
I/O Ports:
Output buffers
Off
0
Off
0
Output latches
Port mode flags (PM)
0
0
Pull-up resistor mode reg (PUMOD)
Port 2 mode register (PWMOD)
0
0
0
0
Basic Timer:
Count register (BCNT)
Mode register (BMOD)
Undefined
0
Undefined
0
Timer/Counter 0:
Count registers (TCNT0)
Reference registers (TREF0)
Mode registers (TMOD0)
Output enable flags (TOE0)
0
0
FFH, FFFFH
FFH, FFFFH
0
0
0
0
Note1: The values of the 0F8H-0FDH are not retained when a RESET signal is input.
S MSUNG
ELECTRONICS
2–21
September 1996
KS57C0002 /0004 MICROCONTROLLER
Table 16. Hardware Register Values After
PRODUCT SPECIFICATION
RESET
(Continued)
RESET
Power-Down Mode
RESET
Occurs During
Normal Operation
Hardware Component
or Subcomponent
If
Occurs During
If
Watch Timer:
Watch timer mode register (WMOD)
Comparator
0
0
Comparator mode register (CMOD)
Comparison result register
0
0
Undefined
Undefined
Serial I/O Interface:
SIO mode register (SMOD)
SIO interface buffer (SBUF)
0
0
Values retained
Undefined
PORT MODE FLAGS (PM FLAGS)
I/O PORTS
Port mode flags (PM) are used to configure I/O ports
0 and 3–6 to input or output mode. It does this by
setting or clearing the corresponding I/O buffer. If a
PM bit is "0", the corresponding I/O pin is set to input
mode. If the PM bit is "1", the corresponding pin is set
to output mode.
The KS57C0002/0004 has two input ports and five I/O
ports. There are total of 6 input pins and 18
configurable I/O pins, including 8 high-current I/O
pins. This gives a total number of 24 I/O pins.
Table 17. Port Mode Flag Map
PM Group ID
Address
FE8H
Bit 3
"0"
Bit 2
PM0.2
PM3.2
PM4.2
"0"
Bit 1
PM0.1
PM3.1
PM4.1
"0"
Bit 0
PM0.0
PM3.0
PM4.0
"0"
PMG1
FE9H
"0"
PMG2
PMG3
FEAH
FEBH
FECH
FEDH
PM4.3
"0"
PM5.3
PM6.3
PM5.2
PM6.2
PM5.1
PM6.1
PM5.0
PM6.0
S MSUNG
ELECTRONICS
September 1996
2–22
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞
PROGRAMMING TIP — Configuring I/O Ports as Input or Output
Configure P0.0 and P3.0 as an output port and the other ports as input ports:
BITS
SMB
LD
LD
LD
LD
LD
LD
EMB
15
EA,#11H
PMG1,EA
EA,#00H
PMG2,EA
EA,#00H
PMG3,EA
;
;
;
P0.0 and P3.0 ← Output
P4 ← Input
P5, P6 ← Input
PORT 2 MODE REGISTER (P2MOD)
PULL-UP RESISTOR MODE REGISTER (PUMOD)
P2MOD register settings determine if port 2 is used
either for analog input or for digital input.
The pull-up resistor mode register, PUMOD, is used
to assign internal pull-up resistors to specific I/O ports.
When a configurable I/O port pin is used as an output
pin, its assigned pull-up resistor is automatically
disabled, even though the pin's pull-up is enabled by a
corresponding PUMOD bit setting.
FE2H
4-Bit W
P2MOD.3
P2MOD.2
P2MOD.1
P2MOD.0
When bit = "1", a pull-up resistor is assigned to the
corresponding I/O port: PUMOD.3 for port 3,
PUMOD.6 for port 6, and so on.
When a P2MOD bit is set to "1", the corresponding pin
is configured as a digital input pin. When set to "0",
configured as an analog input pin: P2MOD.0 for P2.0,
P2MOD.1 for P2.1, P2MOD.2 for P2.2, and P2MOD.3
for P2.3.
Table 18. Pull-Up Resistor Mode Register (PUMOD) Organization (8-Bit W)
Address
FDCH
Bit 3
PUMOD.3
"0"
Bit 2
"0"
Bit 1
PUMOD.1
"0"
Bit 0
PUMOD.0
"0"
FDDH
PUMOD.6
☞
PROGRAMMING TIP — Enabling and Disabling I/O Port Pull-Up Resistors
P6 enable pull-up resistors, P0, P1, and P3 disable pull-up resistors.
BITS
SMB
LD
EMB
15
EA,#40H
PUMOD,EA
LD
;
P6 enable
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ELECTRONICS
2–23
September 1996
KS57C0002 /0004 MICROCONTROLLER
PORT 0 CIRCUIT DIAGRAM
PRODUCT SPECIFICATION
SCK
SMOD.1
SO
P0.0
LATCH
P0.1
LATCH
P0.2
LATCH
SMOD.7
SMOD.6
SMOD.5
V
DD
SCK
SI
PUMOD.0
PM0.2
PM0.1
PM0.0
P0.0 / SCK
P0.1 / SO
P0.2 / SI
When a port pin acts as an output, its pull-up resistor is automatically disabled, even
though the port's pull-up resistor is enabled by bit settings to the pull-up resistor
mode register (PUMOD).
NOTE:
Figure 21. I/O Port 0 Circuit Diagram
S MSUNG
ELECTRONICS
September 1996
2–24
PRODUCT SPECIFICATION
PORT 1 CIRCUIT DIAGRAM
KS57C0002 /0004 MICROCONTROLLER
VDD
VDD
INT0
INT1
PUMOD.1
IMOD0
N/R
Circuit
P1.0 / INT0
P1.1 / INT1
N/R = Noise reduction
Figure 22. Input Port 1 Circuit Diagram
PORT 2 CIRCUIT DIAGRAM
P2.0 / CIN0
DIGITAL INPUT
ANALOG INPUT
DIGITAL INPUT
P2.1 / CIN1
P2.2 / CIN2
P2.3 / CIN3
ANALOG INPUT
DIGITAL INPUT
ANALOG INPUT
DIGITAL INPUT
ANALOG INPUT
EXTERNAL REFERENCE
Figure 23. Port 2 Circuit Diagram
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ELECTRONICS
2–25
September 1996
KS57C0002 /0004 MICROCONTROLLER
PORT 3 CIRCUIT DIAGRAM
PRODUCT SPECIFICATION
V
DD
PUMOD.3
TC0 CLOCK OUTPUT
CLOCK OUTPUT
PM3.2
PM3.1
PM3.0
P3.0 / TCL0
P3.1 / TCLO0
P3.2 / CLO
OUTPUT
LATCH
1, 4
M
U
X
1, 4
TCL0
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even
though the port's pull-up resistor is enabled by bit settings to the pull-up resistor
mode register (PUMOD).
Figure 24. Port 3 Circuit Diagram
S MSUNG
ELECTRONICS
September 1996
2–26
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
PORTS 4 AND 5 CIRCUIT DIAGRAM
x = 4, 5
b = 0, 1, 2, 3
V
DD
PMx.b
8
P-CH
MASK OPTION
OUTPUT
LATCH
Px.b
1, 4, 8
N-CH
M
U
X
VSS
Figure 25. Circuit Diagram for Ports 4 and 5
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ELECTRONICS
2–27
September 1996
KS57C0002 /0004 MICROCONTROLLER
PORT 6 CIRCUIT DIAGRAM
PRODUCT SPECIFICATION
V
DD
PUMOD.6
PM6.3
PM6.2
PM6.1
PM6.0
P6.0 / KS0
P6.1 / KS1
P6.2 / KS2
P6.3 / BUZ
OUTPUT
LATCH
1, 4
M
U
X
1, 4
NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, eve
though the port's pull-up resistor is enabled by bit settings to the pull-up resistor
mode register (PUMOD).
Figure 26. Port 6 Circuit Diagram
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ELECTRONICS
September 1996
2–28
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
incrementing as it counts BT clocks until an overflow
occurs. An overflow causes the BT interrupt request
flag (IRQB) to be set to "1" to signal that the
designated time interval has elapsed. An interrupt
request is then generated, BCNT is cleared to "0", and
counting continues from 00H.
BASIC TIMER (BT)
The basic timer generates interrupt requests atprecise
intervals. You can use the basic timer as a "watchdog"
timer for monitoring system events or use BT output
to stabilize clock oscillation when Stop mode is
released by an interrupt and following RESET.
Oscillation Stabilization Interval Control
Interval Timer Function
Setting bits 2–0 of the BMOD register determines the
time interval (also referred to as 'wait time') required to
stabilize clock signal oscillation when power-down
mode is released by an interrupt. When a RESET
signal is generated, the standard stabilization interval
for system clock oscillation following a RESET is
31.3ms at 4.19 MHz.
The measurement of elapsed time intervals is the
basic timer's primary function. The standard interval is
256 BT clock pulses. To restart the basic timer, set
bit 3 of the mode register BMOD to "1". The 8-bit
counter register, BCNT, is incremented each time a
clock signal is detected that corresponds to the
frequency selected by BMOD. BCNT continues
"CLEAR" SIGNAL
CLEAR
IRQB
CLEAR
BCNT
BITS
INSTRUCTION
BMOD.3
INTERRUPT
REQUEST
OVERFLOW
CLOCK
BMOD.2
BMOD.1
BMOD.0
BCNT
IRQB
4
SELECTOR
1-BIT R/W
8
CPU CLOCK
START SIGNAL
(POWER-DOWN RELEASE)
CLOCK INPUT
Figure 27. Basic Timer Circuit Diagram
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ELECTRONICS
2–29
September 1996
KS57C0002 /0004 MICROCONTROLLER
BASIC TIMER MODE REGISTER (BMOD)
PRODUCT SPECIFICATION
BMOD.3, is used to restart the basic timer. When
BMOD.3 is set to "1", the contents of the BT counter
register (BCNT) and the BT interrupt request flag
(IRQB) are both cleared to "0", and timer operation is
restarted.
The basic timer mode register, BMOD, is used to
select input frequency and oscillation stabilization
time. The most significant bit of the BMOD register,
Table 19. Basic Timer Mode Register (BMOD) Organization (4-Bit W)
BMOD.3
Basic Timer Enable/Disable Control Bit
Start basic timer; clear IRQB, BCNT, and BMOD.3 to "0".
1
BMOD.2
BMOD.1
BMOD.0
Basic Timer Input Clock
Oscillation Stabilization
12
20
0
0
1
1
0
1
0
1
0
1
1
1
fx/2 (1.02 kHz)
2
/fx (250 ms)
/fx (31.3 ms)
/fx (7.82 ms)
/fx (1.95 ms)
9
17
15
13
fx/2 (8.18 kHz)
2
2
2
7
fx/2 (32.7 kHz)
5
fx/2 (131 kHz)
NOTES:
1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fx) of 4.19 MHz.
2. fx = system clock frequency.
3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after Stop mode is released.
4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.
5. BMOD.3 is bit addressable.
BASIC TIMER COUNTER (BCNT)
NOTE
Always execute a BCNT read operation
twice to eliminate the possibility of
reading unstable data while the counter
is incrementing. If, after two consecutive
reads, the BCNT values match, you can
select the latter value as valid data. Until
the results of the consecutive reads
match, however, the read operation
must be repeated until the validation
condition is met.
BCNT is an 8-bit counter register for the basic timer.
When BCNT has incremented to hexadecimal 'FFH', it
is cleared to '00H' and an overflow is generated. The
overflow causes the interrupt request flag, IRQB, to
be set to "1". When the interrupt request is generated,
BCNT immediately resumes counting incoming clock
signals.
S MSUNG
ELECTRONICS
September 1996
2–30
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞
PROGRAMMING TIP — Using the Basic Timer
1. To read the basic timer count register (BCNT):
BITS
SMB
LD
LD
LD
CPSE
JR
EMB
15
EA,BCNT
YZ,EA
EA,BCNT
EA,YZ
BCNTR
BCNTR
2. When Stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms:
BITS
SMB
LD
EMB
15
A,#0BH
BMOD,A
LD
;
;
Wait time is 31.3 ms
Set stop power-down mode
STOP
NOP
NOP
NOP
NORMAL
OPERATING MODE
NORMAL
OPERATING MODE
STOP MODE
IDLE MODE
(31.3 ms)
CPU
OPERATION
STOP
INSTRUCTION
STOP MODE IS
RELEASED BY
INTERRUPT
3. To set the basic timer interrupt interval time to 1.95 ms (at 4.19 MHz):
BITS
SMB
LD
EMB
15
A,#0FH
BMOD,A
LD
EI
BITS
IEB
;
Basic timer interrupt enable flag is set to "1"
4. Clear BCNT and the IRQB flag and restart the basic timer:
BITS
SMB
BITS
EMB
15
BMOD.3
S MSUNG
ELECTRONICS
2–31
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Timer/counter 0 can supply a clock signal to the clock
selector circuit of the serial I/O interface for data
shifter and clock counter operations. (These internal
SIO operations are controlled in turn by the SIO mode
register, SMOD). This clock generation function lets
you adjust data transmission rates across the serial
interface.
8-BIT TIMER/COUNTER 0 (TC0)
Timer/counter 0 (TC0) is used to count system
'events' by identifying the transition (high-to-low or
low-to-high) of incoming square wave signals.
To indicate that an event has occurred, or that a
specified time interval has elapsed, TC0 generates an
interrupt request. By counting signal transitions and
comparing the current counter value with the
reference register value, TC0 can be used to measure
specific time intervals.
CLOCKS
(fx/2 , fx/2 , fx/2 , fx)
P3.0
10
6
4
TCL0
8
TCNT0
8
TMOD0.7
TMOD0.6
TMOD0.5
TMOD0.4
TMOD0.3
TMOD0.2
TMOD0.1
TMOD0.0
8-BIT
COMPARATOR
TREF0
CLOCK
SELECTOR
8
CLEAR
CLEAR
SET
INVERTED
CLEAR
TOL0
IRQT0
SERIAL
I/O
TCLO0
PM3.1
P3.1 LATCH
TOE0
Figure 28. TC0 Circuit Diagram
PROGRAMMABLE TIMER/COUNTER FUNCTION
The content of TCNT0 is then cleared to 00H, and
TC0 continues counting.
Timer/counter 0 can generate interrupt requests at
various intervals, based on the selected system clock
frequency. The reference register, TREF0, stores the
value for the number of clock pulses to be generated
between interrupt requests. The counter register,
TCNT0, counts the incoming clock pulses, which are
compared to the TREF0 value as TCNT0 is
incremented. When TREF0 = TCNT0, the TC0
interrupt request flag (IRQT0) is set to "1", the status
of TOL0 is inverted, and the interrupt is generated.
EVENT COUNTER FUNCTION
Timer/counter 0 can be used to monitor or detect
system 'events' by using the external clock input at
the TCL0 pin (I/O port 3.0) as the counter source. To
activate the TC0 event counter function, P3.0/TCL0
must be set to input mode. With the exception of the
different TMOD0.4–TMOD0.6 settings, the operation
sequence for TC's event counter function is identical
to its programmable timer/counter function.
S MSUNG
ELECTRONICS
September 1996
2–32
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
TC0 CLOCK FREQUENCY OUTPUT
Using timer/counter, you can output a modifiable clock frequency to the TC0 clock output pin, TCLO0. To enable
the output to the TCLO0/P3.1, the pin must be set to output mode when the timer output enable flag (TOE0) has
been enabled.
☞
PROGRAMMING TIP — TC0 Signal Output to the TCLO0 Pin
Output a 30 ms pulse width signal to the TCLO0 pin:
BITS
SMB
LD
LD
LD
LD
LD
LD
BITR
BITS
EMB
15
EA,#79H
TREF0,EA
EA,#4CH
TMOD0,EA
EA,#20H
PMG1,EA
P3.1
;
;
P3.1 ← Output mode
P3.1 clear
TOE0
By selecting an external clock source, you can divide the incoming clock signal by the TREF0 value and then
output this modified clock frequency to the TCLO0 pin.
☞
PROGRAMMING TIP — External TCL0 Clock Output to the TCLO0 Pin
Output external TCL0 clock pulse to the TCLO0 pin (divide by four):
EXTERNAL (TCL0)
CLOCK PULSE
TCLO0
OUTPUT
PULSE
BITS
SMB
LD
LD
LD
LD
LD
LD
BITR
BITS
EMB
15
EA,#01H
TREF0,EA
EA,#0CH
TMOD0,EA
EA,#20H
PMG1,EA
P3.1
;
;
P3.1 ← Output mode
P3.1 clear
TOE0
S MSUNG
ELECTRONICS
2–33
September 1996
KS57C0002 /0004 MICROCONTROLLER
TC0 MODE REGISTER (TMOD0)
PRODUCT SPECIFICATION
TMOD0 is the 8-bit mode control register for timer/counter 0. When TMOD0.3 is set to "1", the contents of TCNT0,
IRQT0, and TOL0 are cleared, counting starts from 00H, and TMOD0.3 is automatically reset to "0" for normal
TC0 operation. When TC0 operation stops (TMOD0.2 = "0"), the contents of the TC0 counter register, TCNT0, are
retained until TC0 is re-enabled.
Table 20. TC0 Mode Register (TMOD0) Organization (8-Bit W)
Bit Name
TMOD0.7
TMOD0.6
TMOD0.5
TMOD0.4
TMOD0.3
Setting
Resulting TC0 Function
MSB value always logic zero
Address
0
F91H
0,1
1
Specify input clock edge and internal frequency
Clear TCNT0, IRQT0, and TOL0. Then immediately resume
counting. (This bit is automatically cleared to "0" when counting
resumes.)
TMOD0.2
0
1
0
0
Disable timer/counter; retain TCNT0 contents
Enable timer/counter
F90H
TMOD0.1
TMOD0.0
Value always "0"
LSB value always "0"
Table 21. TMOD0.6, TMO0.5, and TMOD0.4 Bit Settings
TMOD0.6
TMOD0.5
TMOD0.4
Resulting Counter Source and Clock Frequency
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
External clock input (TCL0) on rising edges
External clock input (TCL0) on falling edges
10
fx/2
= 4.09 kHz
6
fx /2 = 65.5 kHz
4
fx/2 = 262 kHz
fx = 4.19 MHz
NOTE: 'fx' = system clock
S MSUNG
ELECTRONICS
September 1996
2–34
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞
PROGRAMMING TIP — Restarting TC0 Counting Operation
1. Set TC0 timer interval to 4.09 kHz:
BITS
SMB
LD
EMB
15
EA,#4CH
TMOD0,EA
LD
EI
BITS
IET0
2. Clear TCNT0, IRQT0, and TOL0. Then, restart the TC0 counting operation:
BITS
SMB
BITS
EMB
15
TMOD0.3
TC0 REFERENCE REGISTER (TREF0)
☞
PROGRAMMING TIP — Setting a TC0 Timer
Interval
TREF0 is used to store a reference value to be
compared to the incrementing TCNT0 register in order
to identify an elapsed time interval.
To set a 30 ms timer interval for TC0, given fx =
4.19MHz, follow these steps.
Use the following formula to calculate the correct
value to load to the TREF0 reference register:
1. Select the timer/counter mode register with a
maximum setup time of 62.5 ms (assume that the
TC0 timer interval =
10
TC0 counter clock = fx/2 , and TREF0 is FFH):
1
(TREF0 value + 1) ×
2. Calculate the TREF0 value:
TMOD0frequencysetting
TREF0value+1
30 ms =
(assuming a TREF0 value ≠ 0)
4.09kHz
30ms
244µs
TC0 OUTPUT ENABLE FLAG (TOE0)
TREF0 + 1 =
= 122.9 = 7AH
The 1-bit timer/counter 0 output enable flag TOE0
controls output from TC0 to the TCLO0 pin.
TREF0 value = 7AH – 1 = 79H
3. Load the value 79H to the TREF0 register:
F92H
0
1-Bit R/W
0
BITS
SMB
LD
EMB
15
EA,#79H
TREF0,EA
EA,#4CH
TMOD0,EA
TOE0
0
When you set the TOE0 flag to "1", the contents of
TOL0 can be output to the TCLO0 pin.
LD
LD
LD
S MSUNG
ELECTRONICS
2–35
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
software as soon as a requested interrupt service
routine has been executed.
WATCH TIMER
Watch timer functions include real-time and watch-
time measurement and interval timing for the system
clock. It is also used as a clock source for generating
buzzer output.
The watch timer can generate a steady 2 kHz, 4 kHz,
8 kHz, or 16 kHz signal to the BUZ pin. To generate a
BUZ signal, clear the output latch for I/O port 6.3 to
"0" and set the port 6.3 output mode flag (PM6.3) to
output mode.
To start the watch timer, set bit 2 of the watch timer
mode register, WMOD.2, to "1". The watch timer
starts, the interrupt request flag IRQW is automatically
set to "1", and interrupt requests commence in 0.5-
second intervals. Because the watch timer functions
as a quasi-interrupt instead of a vectored interrupt, the
IRQW flag should be cleared to "0" by program
By setting WMOD.1 to "1", the watch timer functions
in high-speed mode, generating an interrupt every
3.91 ms. High-speed mode is useful for timing events
during program debugging sequences.
P6.3 LATCH
PM6.3
WMOD.7
0
BUZ
WMOD.5
fx = SYSTEM CLOCK
fw = WATCH TIMER FREQUENCY
MUX
8
WMOD.4
fw/16 (2 KHz)
fw/2 (16 kHz)
0
fw/8
(4 kHz)
ENABLE / DISABLE
fw/4
(8 kHz)
WMOD.2
WMOD.1
0
SELECTOR
CIRCUIT
IRQW
7
14
fw/2
fw/2 (2 Hz)
FREQUENCY
DIVIDING
fw
CLOCK
32.768 kHz
SELECTOR
CIRCUIT
fx/128
GND
Figure 29. Watch Timer Circuit Diagram
S MSUNG
ELECTRONICS
September 1996
2–36
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
WATCH TIMER MODE REGISTER (WMOD)
The watch timer mode register WMOD is used to select specific watch timer operations.
Table 22. Watch Timer Mode Register (WMOD) Organization (8-Bit W)
Bit Name
Values
Function
Disable buzzer (BUZ) signal output
Enable buzzer (BUZ) signal output
Address
WMOD.7
0
1
WMOD.6
"0"
Always "0"
WMOD.5 – .4
0
0
1
0
1
2 kHz buzzer (BUZ) signal output
4 kHz buzzer (BUZ) signal output
8 kHz buzzer (BUZ) signal output
16 kHz buzzer (BUZ) signal output
Always "0"
F89H
0
1
1
WMOD.3
WMOD.2
"0"
0
Disable watch timer; clear frequency dividing circuits
Enable watch timer
1
F88H
WMOD.1
0
Normal mode; sets IRQW to 0.5 s
High-speed mode; sets IRQW to 3.91 ms
Always "0"
1
WMOD.0
0
NOTE: System clock frequency (fx) is assumed to be 4.19 MHz.
☞
PROGRAMMING TIP — Using the Watch Timer
1. Select a 0.5 second interrupt, and 2 kHz buzzer enable:
BITS
SMB
LD
LD
BITR
LD
EMB
15
EA,#80H
PMG3,EA
P6.3
EA,#84H
WMOD,EA
IEW
;
;
P6.3 ← Output mode
Clear P6.3 output latch
LD
BITS
2. Sample real-time clock processing method:
CLOCK
BTSTZ
RET
•
•
•
IRQW
;
;
;
0.5 second check
No, return
Yes, 0.5 second interrupt generation
;
Increment HOUR, MINUTE, SECOND
S MSUNG
ELECTRONICS
2–37
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
an external reference voltage is input at P2.3, the
other three pins (P2.0–P2.2) in port 2 are used for
analog input. Unused port 2 pins must be connected
COMPARATOR
Port 2 can be used as a analog input port for the 4-
channel comparator block. The reference voltage for
the comparator can be supplied either internally or
externally at P2.3.
to V
.
DD
When a conversion is completed, the result is saved
in the comparison result register CMPREG. The initial
values of the CMPREG are undefined and the
comparator operation is disabled by a RESET.
When internal reference voltage is used, four
channels (P2.0–P2.3) are used for analog inputs and
the internal reference voltage is varies at 16 levels. If
P2.0 / CIN0
P2.1 / CIN1
P2.2 / CIN2
M
U
X
COMPARISON
+
RESULT
4
REGISTER
–
(CMPREG)
P2.3 / CIN3
VREF
(EXTERNAL)
M
U
X
VDD
CMOD.7
CMOD.6
CMOD.5
1/2R
VREF
(INTERNAL)
M
U
X
R
R
0
8
CMOD.3
CMOD.2
CMOD.1
CMOD.0
1/2R
Figure 30 Comparator Circuit Diagram
S MSUNG
ELECTRONICS
September 1996
2–38
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
COMPARATOR MODE REGISTER (CMOD)
When CMOD.5 is set to "1":
— External reference voltage is supplied from
P2.3/CIN3.
The comparator mode register (CMOD) is used to set
the operation mode of the comparator. Based on the
CMOD.5 bit setting, an internal or an external
reference voltage is input for the comparator, as
follows:
— P2.0 to P2.2 are used as the analog input pins.
— The comparator can detect a 150 mV difference
between the reference voltage and analog input
voltages.
When CMOD.5 is "0":
— A reference voltage is selected by the CMOD.0 to
CMOD.3 bit settings.
— Bits 0–2 in the CMPREG register contain the
results (the content of bit 3 is not used).
— P2.0 to P2.3 are used as analog input pins.
Bit 6 in the CMOD register controls conversion time
while bit 7 enables or disables comparator operation
to reduce power consumption.
— The internal digital-to-analog converter generates
16 reference voltages.
— The comparator can detect a 150 mV difference
between the reference voltage and analog input
voltages.
— Comparator results are written into 4-bit
comparison result register (CMPREG).
CMOD.7 CMOD.6 CMOD.5
0
CMOD.3 CMOD.2 CMOD.1 CMOD.0 FD6H–FD7H
Reference voltage (VREF) selection:
VDD x (n + 0.5)/16, n = 0 to 15
1: CIN3; external reference, CIN0–2; analog input
0: Internal reference, CIN0–3; analog input
1: Conversion time (4 x 24 /fx, 15.2 µs @4.19MHz)
0: Conversion time (4 x 27 /fx, 121.6 µs @4.19MHz)
1: Comparator operation enable
0: Comparator operation disable
Figure 31. Comparator Mode Register Organization
PORT 2 MODE REGISTER (P2MOD)
When a P2MOD bit is set to "1", the corresponding pin
is configured as a digital input pin. When it is "0", the
corresponding pin is configured as an analog input:
P2MOD.0 for P2.0, P2MOD.1 for P2.1, P2MOD.2 for
P2.2, and P2MOD.3 for P2.3.
P2MOD register settings determine if port 2 is used
for analog or digital input.
FE2H
4-Bit W
P2MOD.3 P2MOD.2 P2MOD.1
P2MOD.0
S MSUNG
ELECTRONICS
2–39
September 1996
KS57C0002 /0004 MICROCONTROLLER
COMPARATOR OPERATION
PRODUCT SPECIFICATION
The comparison result is calculated as follows:
If "1"
If "0"
Analog input voltage ≥ V
Analog input voltage ≤ V
+ 150 mV
– 150 mV
REF
REF
The comparator compares analog voltage input at
CIN0–CIN3 with an external or internal reference
voltage (V
) that is selected by CMOD register.
REF
The result is written to the comparison result register
CMPREG at address FD4H.
To obtain a comparison result, the data must be read
out from the CMPREG register after V is updated
REF
by changing the CMOD value after a conversion time
has elapsed.
ANALOG INPUT
VOLTAGE (CIN0–3)
REFERENCE
VOLTAGE (VREF)
COMPARISON TIME
(CMPCLK x 4)
COMPARATOR CLOCK
(CMPCLK, fx/16, fx/128)
COMPARISON
START
COMPARISON
END
COMPARISON
RESULT (CMPREG)
1
1
0
UNKNOWN
Figure 32. Conversion Characteristics
☞
PROGRAMMING TIP — Programming the Comparator
The following program example converts the analog voltage input at CIN0–CIN2 pins into 4-bit digital code.
BITR
LD
LD
EMB
A,#0H
P2MOD,A
EA,#8XH
;
;
;
Analog input selection (CIN0–CIN3)
x = 0–F, comparator enable
Internal reference, conversion time (121.6 µs)
LD
LD
CMOD,EA
WAIT LD
A,#0H
INCS
JR
LD
LD
A
WAIT
A,CMPREG
P4,A
;
;
Read the result
Output the result from port 4
S MSUNG
ELECTRONICS
September 1996
2–40
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
SERIAL I/O INTERFACE
Using the serial I/O interface, you can exchange 8-bit data with an external device. The serial interface can run off
an internal or an external clock source, or the TOL0 signal that is generated by the 8-bit timer/counter 0, TC0. If
you use the TOL0 clock signal, you can modify its frequency to adjust the serial data transmission rate.
INTERNAL BUS
8
LSB or MSB first
SO
SBUF (8-BIT)
SI
CLK
R
Q
D
SCK
IRQS
R
CLK
TOL0
CLOCK
SELECTOR
Q0 Q1 Q2
10
fx/2
Q
3-BIT COUNTER
CLK
S
fx/2
CLEAR
SMOD.7 SMOD.6 SMOD.5
SMOD.3 SMOD.2 SMOD.1 SMOD.0
–
8
Figure 33. Serial I/O Interface Circuit Diagram
S MSUNG
ELECTRONICS
2–41
September 1996
KS57C0002 /0004 MICROCONTROLLER
SERIAL I/O MODE REGISTER (SMOD)
PRODUCT SPECIFICATION
SERIAL I/O BUFFER REGISTER (SBUF)
The serial I/O mode register (SMOD) specifies the
operation mode of the serial interface. SMOD register
settings enable you to select either MSB-first or LSB-
first serial transmission, and to operate in transmit-
and-receive mode or receive-only mode. When
SMOD.3 is set to "1", the contents of the serial
interface interrupt request flag, IRQS, and the 3-bit
serial clock counter are cleared, and SIO operations
are initiated. When the SIO transmission starts,
SMOD.3 is cleared to "0".
When the serial interface operates in transmit-and-
receive mode (SMOD.1 = "1"), transmit data in the
SIO buffer register are output to the SO pin at the rate
of one bit for each falling edge of the SIO clock.
Receive data is simultaneously input from the SI pin
to SBUF at the rate of one bit for each rising edge of
the SIO clock.
When receive-only mode is used, incoming data is
input to the SIO buffer at the rate of one bit for each
rising edge of the SIO clock. SBUF can be read or
written using 8-bit RAM control instructions.
Table 23. SIO Mode Register (SMOD) Organization (8-Bit W)
SMOD.0
SMOD.1
SMOD.2
0
1
0
1
0
Most significant bit (MSB) is transmitted first
Least significant bit (LSB) is transmitted first
Receive-only mode; output buffer is off
Transmit-and-receive mode
Disable the data shifter and clock counter; retain contents of IRQS flag when serial
transmission is halted
1
1
0
Enable the data shifter and clock counter; set IRQS flag to "1" when serial
transmission is halted
SMOD.3
SMOD.4
Clear IRQS flag and 3-bit clock counter to "0"; initiate transmission and then reset
this bit to "0"; this bit is also bit-addressable.
Bit not used; value is always "0"
SMOD.7
SMOD.6
SMOD.5
Clock Selection
R/W Status of SBUF
0
0
0
External clock at SCK pin
SBUF is enabled when SIO
operation is halted or when SCK
goes high.
0
0
1
0
1
0
1
x
0
Use TOL0 clock from TC0
CPU clock: fx/4, fx/8, fx/64
Enable SBUF read/write
10
SBUF is enabled when SIO
operation is halted or when SCK
goes high.
4.09 kHz clock: fx/2
4
1
1
1
262 kHz clock: fx/2
NOTES:
1. 'fx' = system clock; 'x' means 'don't care.'
2. kHz frequency ratings assume a system clock (fx) running at 4.19 MHz.
3. The SIO clock selector circuit cannot select a fx/24 clock if the CPU clock is fx/64.
S MSUNG
ELECTRONICS
September 1996
2–42
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
SCK
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SI
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SO
IRQS
TRANSMIT
COMPLETE
SET SMOD.3
Figure 34. SIO Timing in Transmit/Receive Mode
SCK
SI
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
HIGH IMPEDANCE
SO
IRQS
TRANSMIT
COMPLETE
SET SMOD.3
Figure 35. SIO Timing in Receive-Only Mode
S MSUNG
ELECTRONICS
2–43
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
☞
PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O
4
1. Transmit the data value 48H through the serial I/O interface using an internal clock frequency of fx/2 and in
MSB-first mode:
BITS
SMB
LD
LD
LD
LD
LD
LD
EMB
15
EA,#03H
PMG1,EA
EA,#48H
SBUF,EA
EA,#0EEH
SMOD,EA
; P0.0 / SCK and P0.1 / SO ← Output
;
;
; SIO data transfer
☞
PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
SCK / P0.0
SO / P0.1
EXTERNAL
DEVICE
KS57C0002
2. Use CPU clock to transfer and receive serial data at high speed:
BITR
LD
LD
LD
LD
LD
LD
BITR
BTSTZ
JR
EMB
EA,#03H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#4FH
SMOD,EA
IES
; P0.0 / SCK and P0.1 / SO ← Output, P0.2 / SI ← Input
; TDATA address = Bank0(20H–7FH)
; SIO start
; SIO Interrupt Enable
STEST
IRQS
STEST
LD
LD
EA,SBUF
RDATA,EA
; RDATA address = Bank0 (20H–7FH)
S MSUNG
ELECTRONICS
September 1996
2–44
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
☞
PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
3. Transmit and receive an internal clock frequency of 4.09 kHz (at 4.19 MHz) in LSB-first mode:
BITR
LD
LD
LD
LD
LD
LD
EMB
EA,#03H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#8FH
SMOD,EA
; P0.0 / SCK and P0.1 / SO ← Output, P0.2 / SI ← Input
; TDATA address = Bank0 (20H–7FH)
; SIO start
EI
BITS
•
IES
; SIO Interrupt Enable
•
•
INTS
PUSH
PUSH
BITR
LD
SB
EA
EMB
EA,TDATA
; Store SMB, SRB
; Store EA
; EA ← Transmit data
; TDATA address = Bank0 (20H–7FH)
; Transmit data ↔ Receive data
; RDATA address = Bank0 (20H–7FH)
; SIO start
XCH
LD
BITS
POP
POP
IRET
EA,SBUF
RDATA,EA
SMOD.3
EA
SB
SCK / P0.0
EXTERNAL
DEVICE
SO / P0.1
SI / P0.2
KS57C0002
S MSUNG
ELECTRONICS
2–45
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
☞
PROGRAMMING TIP — Setting Transmit/Receive Modes for Serial I/O (Continued)
4. Transmit and receive an external clock in LSB-first mode:
BITR
LD
LD
LD
LD
LD
LD
EMB
EA,#02H
PMG1,EA
EA,TDATA
SBUF,EA
EA,#0FH
SMOD,EA
; P0.1 / SO ← Output, P0.0 / SCK and P0.2/SI← Input
; TDATA address = Bank0 (20H–7FH)
; SIO start
EI
BITS
•
IES
; SIO Interrupt Enable
•
•
INTS
PUSH
PUSH
BITR
LD
SB
EA
EMB
EA,TDATA
; Store SMB, SRB
; Store EA
; EA ← Transmit data
; TDATA address = Bank0 (20H–7FH)
; Transmit data ↔ Receive data
; RDATA address = Bank0 (20H–7FH)
; SIO start
XCH
LD
BITS
POP
POP
IRET
EA,SBUF
RDATA,EA
SMOD.3
EA
SB
SCK / P0.0
EXTERNAL
DEVICE
SO / P0.1
SI / P0.2
KS57C0002
S MSUNG
ELECTRONICS
September 1996
2–46
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
ELECTRICAL DATA
Table 24. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
—
Rating
Units
Supply Voltage
Input Voltage
V
– 0.3 to + 7.0
V
V
DD
V
Ports 4, 5
CMOS push-pull
Open-drain
– 0.3 to V
+ 0.3
DD
I1
– 0.3 to + 9
V
All I/O ports except 4 and 5
—
– 0.3 to V
+ 0.3
I2
O
DD
Output Voltage
V
– 0.3 to V
+ 0.3
V
DD
Output Current High
I
One I/O port active
All I/O ports active
Ports 0, 3, and 6
Ports 4 and 5
All ports, total
—
– 5
– 15
5
mA
OH
OL
Output Current Low
I
mA
30
+ 100
Operating Temperature
Storage Temperature
T
– 40 to + 85
– 65 to + 150
°
°
A
C
C
T
—
stg
Table 25. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 2.7 V to 6.0 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Input High
Voltage
V
Ports 4 and 5
0.7V
—
V
V
IH1
DD
DD
V
V
Ports 0, 1, 2, 3, 6, and RESET
0.8V
—
—
—
V
V
IH2
IH3
DD
DD
DD
X
and X
V
– 0.5
DD
in
out
Input Low
Voltage
V
Ports 4 and 5
—
0.3V
V
V
IL1
DD
V
V
V
Ports 0, 1, 2, 3, 6, and RESET
0.2V
*
IL2
IL3
OH
DD
X
V
and X
out
in
Output High
Voltage
= 4.5 V to 6.0 V
V
V
– 1.0
– 2.0
—
—
DD
DD
DD
I
= – 1 mA
OH
Ports 0, 3, 4, 5, 6
V
= 4.5 V to 6.0 V
DD
I
= – 3.0 mA
OH
Ports 0, 3, 4, 5, 6
*
The value is 0.2V at KS57C0002 or 0.4V at KS57C0004.
S MSUNG
ELECTRONICS
2–47
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 25. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 2.7 V to 6.0 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Output Low
Voltage
V
V
= 4.5 V to 6.0 V
DD
—
0.4
2
V
OL
I
= 15 mA
OL
Ports 4 and 5 only
V
= 4.5 V to 6.0 V
= 1.6 mA
—
—
0.4
2
DD
I
OL
Ports 0, 3, 6 only
V
= 4.5 V to 6.0 V
= 4.0 mA
DD
I
OL
Ports 0, 3, 6 only
Input High
Leakage
Current
I
V
= V
—
—
3
µA
LIH1
IN
DD
All input pins except X and X
in
out
I
I
V
X
= V
DD
20
10
LIH2
LIH3
IN
in
and X
out
V
= 9 V
IN
Ports 4 and 5 are open-drain
Input Low
Leakage
Current
I
V
= 0 V
—
—
– 3
µA
µA
LIL1
LIL2
IN
All input pins except X , X
in out and
RESET
I
V
X
= 0 V
– 20
3
IN
in
and X
out
Output High
Leakage
Current
I
I
V
= V
DD
—
—
LOH1
LOH2
O
All output pins except for port 4
and port 5
V
= 9 V
10
O
Ports 4 and 5 are open-drain
Output Low
Leakage
Current
I
V
= 0 V
—
– 3
µA
LOL
O
R
V
= 0 V; V
DD
= 5 V ± 10%
= 3 V ± 10%
= 5 V ± 10%
= 3 V ± 10%
15
30
40
80
KΩ
Pull-Up
Resistor
L1
L2
IN
Port 0, 1, 3, 6
V
= 0 V; V
200
400
800
IN
DD
Port 0, 1, 3, 6
R
V
= 0 V; V
100
200
230
490
KΩ
IN
DD
RESET
V
= 0 V; V
IN
DD
RESET
S MSUNG
ELECTRONICS
September 1996
2–48
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 25. D.C. Electrical Characteristics (Concluded)
°
°
(T = – 40 C to + 85 C, V
= 2.7 V to 6.0 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
(2)
Supply
Current
I
—
2.5
8
mA
V
= 5 V ± 10%
DD1
DD
(1)
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
(3)
0.62
1.2
1.2
1.8
1.0
V
= 3 V ± 10%
DD
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
I
I
Idle mode; V
= 5 V ± 10%
DD
4.19 MHz crystal oscillator
—
mA
DD2
DD3
C1 = C2 = 22 pF
Idle mode; V
= 3 V ± 10%
0.58
DD
4.19 MHz crystal oscillator
C1 = C2 = 22 pF
Stop mode
0.5
0.3
5
3
µA
V
= 5 V ± 10%
DD
Stop mode
= 3 V ± 10%
V
DD
NOTES:
1. The currents in the following circuits are not included; on-chip pull-up resistors, output port drive currents and comparator.
2. For high-speed controller operation, set the PCON register to 0011B.
3. For low-speed controller operation, set the PCON register to 0000B.
CPU CLOCK
1.0475 MHz
1.00 MHz
750 kHz
500 kHz
250 kHz
15.6 kHz
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 36. Standard Operating Voltage Range
S MSUNG
ELECTRONICS
2–49
September 1996
KS57C0002 /0004 MICROCONTROLLER
Table 26. Oscillator Characteristics
PRODUCT SPECIFICATION
°
°
(T = – 40 C to + 85 C, V
= 5 V)
A
DD
Oscillator
Clock
Configuration
Parameter
Test Condition
Min
Typ
Max Units
(1)
Ceramic
Oscillator
—
0.4
—
4.5
MHz
Xin
Xout
Oscillation frequency
C1
C2
(2)
After V
reaches
—
—
4
ms
Stabilization time
DD
the minimum level of
its variable range
(1)
Crystal
Oscillator
—
0.4
4.19
4.5
MHz
Xin
Xout
Oscillation frequency
C1
C2
(2)
V
V
= 2.7 V to 4.5 V
= 4.5 V to 6.0 V
—
—
—
—
—
—
30
10
ms
ms
Stabilization time
DD
DD
(1)
External
Clock
0.4
4.5
MHz
Xin
Xout
Xin input frequency
Xin input high and low
level width (t , t
—
100
0.4
—
—
150
2
ns
)
XH XL
RC
Oscillator
(3)
Oscillation frequency
limitation
V
= 5 V
MHz
Xin
Xout
DD
R
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillator stabilization after a reset or termination of Stop mode.
3. RC is only for the KS57C0002.
S MSUNG
ELECTRONICS
September 1996
2–50
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 27. Input/Output Capacitance
°
(T = 25 C, V
= 0 V )
A
DD
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
C
f = 1 MHz; Unmeasured pins
—
—
15
pF
IN
are returned to V
SS
Output
Capacitance
C
—
—
—
—
15
15
pF
pF
OUT
I/O Capacitance
C
IO
Table 28. Comparator Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
A
= 4.0 V to 6.0 V, V
= 0 V)
SS
DD
Parameter
Symbol
Condition
Min
0
Typ
—
Max
Units
Input Voltage Range
—
—
—
V
V
V
V
DD
DD
Reference Voltage
Range
V
0
—
REF
Input Voltage Accuracy
V
—
—
—
—
—
±150
mV
CIN
Input Leakage Current
I
I
– 3
3
µA
CIN, REF
Table 29. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 2.7 V to 6.0 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Instruction Cycle
Time
t
V
= 4.5 V to 6.0 V
0.95
—
64
µs
CY
DD
V
V
= 2.7 V to 4.5 V
= 4.5 V to 6.0 V
3.8
0
DD
DD
TCL0 Input
Frequency
f
—
—
—
1
MHz
TI
V
V
= 2.7 V to 4.5 V
= 4.5 V to 6.0 V
275
—
kHz
DD
DD
TCL0 Input High,
Low Width
t
, t
0.48
µs
TIH TIL
V
V
V
V
V
= 2.7 V to 4.5 V
1.8
DD
DD
DD
DD
DD
SCK Cycle Time
t
= 4.5 V to 6.0 V; Input
= 4.5 V to 6.0 V; Output
= 2.7 V to 4.5 V; Input
= 2.7 V to 4.5 V; Output
800
—
ns
KCY
1600
3200
3800
S MSUNG
ELECTRONICS
2–51
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
Table 29. A.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 2.7 V to 6.0 V)
A
DD
Parameter
Symbol
, t
Conditions
Min
Typ
Max
Units
SCK High, Low
Width
t
V
V
= 4.5 V to 6.0 V; Input
400
—
—
ns
KH KL
DD
DD
= 4.5 V to 6.0 V; Output
t
/2 –
KCY
50
V
V
= 2.7 V to 4.5 V; Input
= 2.7 V to 4.5 V; Output
1600
DD
DD
t
KCY/2 –
150
SI Setup Time to
SCK High
t
t
Input
100
—
—
—
—
—
ns
ns
ns
SIK
KSI
Output
Input
150
400
SI Hold Time to
SCK High
Output
400
—
Output Delay for
SCK to SO
t
V
= 4.5 V to 6.0 V; Input
300
KSO
DD
V
V
V
= 4.5 V to 6.0 V; Output
= 2.7 V to 4.5 V; Input
= 2.7 V to 4.5 V; Output
250
1000
1000
—
DD
DD
DD
*
Interrupt Input
High, Low Width
t
, t
INT0
—
—
µs
µs
INTH INTL
INT0, INT1, KS0–KS2
Input
10
10
RESET Input Low
Width
t
—
RSL
*
The minimum value for INT0 is based on a clock of 2t
or 128/fx as assigned by the IMOD0 register setting.
CY
0.8 VDD
0.8 VDD
MEASUREMENT
POINTS
0.2 VDD
0.2 VDD
Figure 37. A.C. Timing Measurement Points (Except for X )
in
S MSUNG
ELECTRONICS
September 1996
2–52
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
Table 30. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Condition
Min
Typ
Max
Units
Data Retention
Supply Voltage
V
—
2.0
—
6.0
V
DDDR
Data Retention
Supply Current
I
—
—
0
0.1
10
—
—
—
µA
ms
ms
ms
DDDR
Release Signal Set
Time
t
—
—
17
SREL
WAIT
Oscillation
Stabilization Time
t
When released by RESET
When released by interrupt
—
—
2
/fx
(1)
(2)
NOTES:
1. During oscillation stabilization time, CPU operation must be stopped to avoid instability during oscillator startup.
2. The basic timer causes a delay of 217/fx after a reset.
INTERNAL RESET
OPERATION
IDLE MODE
OPERATING
STOP MODE
DATA RETENTION MODE
MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
RESET
Figure 38. Stop Mode Release Timing When Initiated By
IDLE MODE
NORMAL
OPERATING
MODE
STOP MODE
DATA RETENTION MODE
VDD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING SIGNAL
(INTERRUPT REQUEST)
Figure 39. Stop Mode Release Timing When Initiated By Interrupt Request
S MSUNG
ELECTRONICS
2–53
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
1 / fx
tXL
tXH
Xin
VDD – 0.5 V
0.4 V
Figure 40 Clock Timing Measurement at X
in
1 / fTI
tTIL
tTIH
0.8 VDD
0.2 VDD
TCL0
Figure 41. TCL0 Timing
tRSL
RESET
0.2 VDD
RESET
Figure 42. Input Timing for
Signal
tINTL
tINTH
INT0, 1
KS0 to KS2
0.8 VDD
0.2 VDD
Figure 43. Input Timing for External Interrupts
S MSUNG
ELECTRONICS
September 1996
2–54
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
tCKY
tKL
tKH
0.8 VDD
0.2 VDD
SCK
tSIK
tKSI
0.8 VDD
0.2 VDD
SI
INPUT DATA
tKSO
SO
OUTPUT DATA
Figure 44. Serial Data Transfer Timing
S MSUNG
ELECTRONICS
2–55
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
CHARACTERISTIC CURVES
NOTE
The characteristic values shown in the following graphs are based on actual test measurements.
They do not, however, represent guaranteed operating values.
IDD1 vs. FREQUENCY (CPU CLOCK = fx/4, fx = 1, 2, 4.2 MHz)
4
3.5
VDD = 5.5 V
3
2.5
2
1.5
1
VDD = 3.3 V
0.5
0
0.0
1.0
2.0
3.0
4.0
5.0
FREQUENCY (MHz)
Figure 45. Frequency VS. I
DD1
IDD2 vs. FREQUENCY (CPU CLOCK = fx/4, fx/64, fx = 4.2 MHz)
1.5
VDD = 5.5 V
1
0.5
VDD = 3.3 V
0
0.0
1.0
2.0
3.0
4.0
5.0
FREQUENCY (MHz)
Figure 46. Frequency VS. I
DD2
S MSUNG
ELECTRONICS
September 1996
2–56
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
IDD1 vs. VDD (CPU CLOCK = fx/4, fx/64, fx = 4.2 MHz)
4
3.5
3
fx/4
2.5
2
fx/64
1.5
1
0.5
0
3.0
4.0
5.0
6.0
7.0
POWER SUPPLY VOLTAGE VDD (V)
Figure 47. V
VS. I
DD1
DD
S MSUNG
ELECTRONICS
2–57
September 1996
KS57C0002 /0004 MICROCONTROLLER
PRODUCT SPECIFICATION
NOTES
S MSUNG
ELECTRONICS
September 1996
2–58
PRODUCT SPECIFICATION
KS57C0002 /0004 MICROCONTROLLER
NOTES
S MSUNG
ELECTRONICS
2–59
September 1996
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