KS57C0616Q [SAMSUNG]
Microcontroller, 4-Bit, MROM, SAM47 CPU, 6MHz, CMOS, PQFP44;
| 型号： | KS57C0616Q |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, MROM, SAM47 CPU, 6MHz, CMOS, PQFP44 微控制器 |
| 文件： | 总32页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS57C0616/P0616
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The KS57C0616 single-chip CMOS microcontroller has been designed for high-performance using SAM 47
(Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable for its low energy
consumption and low operating voltage.
Up to 36 pins of the available 42-SDIP and 44-QFP packages can be dedicated to I/O, and six vectored interrupts
provide fast response to internal and external events.
In addition, the advanced CMOS technology of KS57C0616 provides for low power consumption and a wide
operating voltage range.
OTP
The KS57C0616 microcontroller is also available in OTP (One Time Programmable) version, KS57P0616. The
KS57P0616 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM.
The main features of KS57P0616 and KS57C0616 is same except ROM type.
1-1
PRODUCT OVERVIEW
KS57C0616/P0616
FEATURES SUMMARY
Memory
Interrupts
·
·
1 K ´ 4-bit RAM
16 K ´ 8-bit ROM
·
·
·
3 external interrupt vectors
3 internal interrupt vectors
2 quasi-interrupts
36 I/O Pins
·
·
·
Input only: 4 pins
Power-Down Modes
I/O: 24 pins
·
·
Idle: Only CPU clock stops
Stop: System clock stops
N-channel open-drain I/O: 8 pins
Memory-Mapped I/O Structure
Data memory bank 15
Oscillation Sources
·
·
·
·
Crystal, or ceramic for main system clock
Main system clock frequency: 0.4–6.0 MHz
CPU clock divider circuit (by 4, 8, or 64)
8-Bit Basic Timer
·
·
Programmable interval timer
Watchdog timer
Instruction Execution Times
·
·
·
0.95, 1.91, and 15.3 ms at 4.19 MHz
1.12, 2.23, 17.88 ms at 3.58 MHz
0.67, 1.33, 10.7 ms at 6.0 MHz
Two 8-Bit Timer/Counters
·
·
·
Programmable 8-bit timer
External event counter function
Arbitrary clock frequency output
Operating Temperature
°
– 40 C to 85 °C
·
Watch Timer
·
·
Real-time and interval time measurement
Four frequency outputs to the BUZ pin
Operating Voltage Range
1.8 V to 5.5 V
·
Bit Sequential Carrier
Package Types
42 SDIP, 44 QFP
·
Supports 8-bit serial data transfer in arbitrary
format
·
1-2
KS57C0616/P0616
OVERVIEW
BLOCK DIAGRAM
BASIC
(WATCH-
DOG) TIMER
INT0, INT1, INT2, INT4
X
IN
X
OUT
RESET
WATCH
TIMER
8-BIT TIMER
COUNTER
0/1
INTERRUPT
CONTROL
BLOCK
STACK
POINTER
CLOCK
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
INPUT
PORT 1
PROGRAM
COUNTER
P6.0–P6.3 /
KS0–KS3
I/O PORT 6
I/O PORT 7
INTERNAL
INTERRUPTS
P2.0/TCLO0
P2.1/TCLO1
P2.2/CLO
P7.0–P7.3 /
KS4–KS7
I/O PORT 2
I/O PORT 3
P2.3/BUZ
PROGRAM
STATUS
WORD
INSTRUCTION DECODER
P3.0/TCL0
P3.1/TCL1
P3.2
P8.0–P8.3
P9.0–P9.3
I/O PORT 8
I/O PORT 9
ARITHMETIC
AND
LOGIC UNIT
P3.3
P4.0/BTCO
P4.1–P4.3
FLAGS
I/O PORT 4
I/O PORT 5
P5.0–P5.3
1-K x 4-BIT
DATA
MEMORY
16-KBYTE
PROGRAM
MEMORY
Figure 1-1. KS57C0616 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
KS57C0616/P0616
PIN ASSIGNMENTS
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/TCLO0
P2.1/TCLO1
P2.2/CLO
P2.3/BUZ
P3.0/TCL0
P3.1/TCL1
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P9.2
P9.1
P9.0
P9.3
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
9
10
11
12
13
14
15
16
17
18
19
20
21
V
DD
V
SS
X
OUT
X
IN
TEST
P4.0/BTCO
P4.1
RESET
P3.2
P3.3
P4.2
Figure 1-2. KS57C0616 Pin Assignment Diagrams (42-SDIP-600)
1-4
KS57C0616/P0616
PRODUCT OVERVIEW
P2.2/CLO
P2.3/BUZ
P3.0/TCL0
P3.1/TCL1
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
V
DD
V
SS
X
OUT
X
IN
TEST
P4.0/BTCO
P4.1
9
10
11
P5.2
P5.1
Figure 1-3. KS57C0616 Pin Assignment Diagrams (44-QFP-1010B)
1-5
PRODUCT OVERVIEW
KS57C0616/P0616
PIN DESCRIPTIONS
Table 1-1. KS57C0616 Pin Descriptions
Description
Pin
Name
Pin
Type
Pin
Number
Share
Pin
Circuit
Type
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test is possible.
Each pull-up resistors are assignable by software.
1 (39)
2 (40)
3 (41)
4 (42)
INT0
INT1
INT2
INT4
A-4
D-2
D-4
E-2
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
5 (43)
6 (44)
7 (1)
TCLO0
TCLO1
CLO
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
8 (2)
BUZ
P3.0
P3.1
P3.2
P3.3
4-bit pull-up resistors are software assignable to
input pins and are automatically disabled for output
pins. Ports 2 and 3 can be paired to enable 8-bit
data transfer.
9 (3)
10 (4)
19 (13)
20 (14)
TCL0
TCL1
P4.0
P4.1
P4.2
P4.3
I/O
4-bit I/O ports.
16 (10)
17 (11)
21 (15)
22 (17)
BTCO
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to
input pins and are automatically disabled for output
pins.
P5.0–P5.3
27–30
(22–25)
N-channel open-drain or push-pull output can be
selected by software (1-bit unit).
Ports 4 and 5 can be paired to enable 8-bit data
transfer.
P6.0–P6.3
P7.0–P7.3
I/O
4-bit I/O ports.
31–34
(26–29),
35–38
KS0–KS3
KS4–KS7
D-4
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
(30–33)
4-bit pull-up resistors are software assignable to
input pins and are automatically disabled for output
pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
P8.0–P8.3
P9.0–P9.3
I/O
4-bit I/O port.
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or 40–42, 39
23–26
(18–21),
–
D-2
output.
(35–37, 34)
4-bit pull-up resistors are software assignable to
input pins and are automatically disabled for output
pins.
Ports 8 and 9 can be paired to enable 8-bit data
transfer.
1-6
KS57C0616/P0616
PRODUCT OVERVIEW
Table 1-1. KS57C0616 Pin Descriptions (Continued)
Pin Name
Pin
Type
Description
Pin
Number
Share Pin Circuit
Type
INT0
INT1
I
External interrupt input. The triggering edge for
INT0 and INT1 is selectable.
1 (39)
2 (40)
P1.0
P1.1
A-3
INT2
INT4
I
I
Quasi-interrupt input with detection of rising edge
3 (41)
4 (42)
P1.2
P1.3
A-3
A-3
External interrupt with detection of rising and falling
edge.
TCLO0
TCLO1
CLO
I/O
I/O
I/O
I/O
Timer/counter 0 clock output
Timer/counter 1 clock output
Clock output
5 (43)
6 (44)
7 (1)
P2.0
P2.1
P2.2
P2.3
D-2
D-2
D-2
D-2
BUZ
2, 4, 8, or 16 kHz frequency output for buzzer sound
with 4.19 MHz system clock
8 (2)
TCL0
TCL1
I/O
I/O
I/O
I/O
External clock input for timer/counter 0
External clock input for timer/counter 1
Basic timer clock output
9 (3)
10 (4)
16 (10)
P3.0
P3.1
D-4
D-4
E-2
D-4
BTCO
P4.0
KS0–KS3
Quasi-interrupt inputs with falling edge detection
31–34
(26–29)
35–38
P6.0–P6.3
KS4–KS7
P7.0–P7.3
(30–33)
VDD
VSS
–
–
Power supply
Ground
11 (5)
12 (6)
–
–
–
–
–
–
RESET signal
18 (12)
–
–
B
–
RESET
XIN
XOUT
Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use XIN and input
14 (8)
13 (7)
XIN's reverse phase to XOUT
)
TEST
NC
–
–
Test signal input
15 (9)
–
–
–
–
No connection
(16, 38)
NOTE: Parentheses indicate pin number for 44 QFP package.
1-7
PRODUCT OVERVIEW
KS57C0616/P0616
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
-
P CHANNEL
IN
IN
-
N CHANNEL
Schmitt Trigger
Figure 1-6. Pin Circuit Type B
Figure 1-4. Pin Circuit Type A
V
V
DD
DD
Pull-up
Resistor
-
P Channel
Pull-up
Resistor
Enable
Data
-
Out
P Channel
-
N Channel
Output
IN
Disable
Schmitt Trigger
Figure 1-7. Pin Circuit Type C
Figure 1-5. Pin Circuit Type A-3
1-8
KS57C0616/P0616
PRODUCT OVERVIEW
V
V
DD
DD
Pull-Up
Resistor
Pull-Up
Resistor
Pull-Up
Enable
Resistor
Pull-Up
Enable
Resistor
P-Channel
I/O
P-Channel
I/O
Data
Data
Circuit
Type C
Circuit
Type C
Output
Output
Disable
Disable
Schmitt Triger
Figure 1-9. Pin Circuit Type D-4
Figure 1-8. Pin Circuit Type D-2
V
DD
Pull-Up
Resistor
PNE
V
DD
Pull-Up Resistor
Enable
P-Channel
I/O
Data
Output
Disable
N-Channel
Figure 1-10. Pin Circuit Type E-2
1-9
PRODUCT OVERVIEW
KS57C0616/P0616
NOTES
1-10
KS57C0616/P0616
ELECTRICAL DATA
12 ELECTRICAL DATA
OVERVIEW
In this chapter, information on KS57C0616 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN and XOUT
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
12-1
ELECTRICAL DATA
KS57C0616/P0616
Table 12-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
VDD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
V
VI1
VO
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 15
All I/O ports
V
V
Output Voltage
Output Current High
–
IOH
One I/O port active
mA
All I/O ports active
One I/O port active
– 35
IOL
Output Current Low
+ 30 (Peak value)
mA
+ 15 (note)
All I/O ports active
+ 100 (Peak value)
+ 60 (note)
°
TA
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
C
°
C
Tstg
– 65 to + 150
NOTE: The values for output current low (IOL) are calculated as peak value ´
Duty .
Table 12-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
0.7 VDD
VDD
Input high
voltage
VIH1
All input pins except those
specified below for VIH2–VIH3
–
V
0.8 VDD
VDD
VDD
VIH2
VIH3
VIL1
Ports 1, 3, 6, 7, and RESET
XIN and XOUT
V
DD – 0.1
0.3 VDD
Input low
voltage
All input pins except those
specified below for VIL2–VIL3
–
–
V
0.2 VDD
0.1
VIL2
VIL3
Ports 1, 3, 6, 7, and RESET
XIN and XOUT
12-2
KS57C0616/P0616
ELECTRICAL DATA
Table 12-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
IOH = – 1 mA
Ports except 1
VDD = 4.5 V to 5.5 V
Min
Typ
Max
Units
VOH
VDD – 1.0
Output high
voltage
–
–
V
VOL1
Output low
voltage
–
–
2
V
V
IOL = 15 mA, Ports 4 and 5 only
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
–
–
–
–
0.4
2
VOL2
VDD = 4.5 V to 5.5 V
IOL= 4 mA, all out ports except 4, 5
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
V = V
–
–
–
–
0.4
3
ILIH1
Input high
µA
I
DD
leakage current
All input pins except those specified
below
ILIH2
VI = VDD
20
XIN and XOUT
ILIL1
ILIL2
VI = 0 V
Input low
leakage current
–
–
– 3
µA
All input pins except below and RESET
VI = 0 V
– 20
XIN and XOUT only
ILOH
ILOL
RL1
VO = VDD
Output high
leakage current
–
–
–
–
3
µA
µA
kW
All out pins
VO = 0 V
Output low
leakage current
– 3
100
200
All out pins
VDD = 5 V; VI = 0 V
except RESET
VDD = 3 V
Pull-up resistor
25
50
50
100
RL2
VDD = 5 V; V = 0 V; RESET
I
100
200
250
500
400
800
VDD = 3 V
12-3
ELECTRICAL DATA
KS57C0616/P0616
Table 12-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Symbol
Conditions
Min
Typ
Max Units
IDD1
6.0 MHz
–
2.6
8.0
4.0
mA
mA
µA
Run mode; VDD = 5 V ± 10%
current (1)
crystal oscillator; C1 = C2 = 22 pF 3.58 MHz
1.7
VDD = 3 V ± 10%
6.0 MHz
1.2
0.7
4.0
2.3
3.58 MHz
IDD2
6.0 MHz
–
–
0.7
0.6
2.5
1.8
Idle mode; VDD = 5 V ± 10%
crystal oscillator; C1 = C2 = 22 pF 3.58 MHz
VDD = 3 V ± 10%
6.0 MHz
0.2
0.2
1.5
1.0
3.58 MHz
IDD3
Stop mode; VDD = 5 V ± 10%
Stop mode; VDD = 3 V ± 10%
0.2
0.1
3.0
2.0
NOTES:
1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers.
2. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
12-4
KS57C0616/P0616
ELECTRICAL DATA
Table 12-3. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 C, VDD = 1.8 V to 5.5 V)
°
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Ceramic
0.4
–
6.0
MHz
Xin
Xout
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
4.2
4
Stabilization time (2)
ms
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Crystal
0.4
6.0
MHz
Xin
Xout
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
4.2
10
Stabilization time (2)
ms
VDD = 2.7 V to 5.5 V
External
Clock
0.4
6.0
MHz
Xin
Xout
XIN input frequency (1)
VDD = 1.8 V to 5.5 V
–
0.4
–
–
4.2
XIN input high and low
83.3
1,250
ns
level width (tXH, tXL
)
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
12-5
ELECTRICAL DATA
KS57C0616/P0616
Table 12-4. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Symbol
Condition
Min
Typ
Max
Units
CIN
COUT
CIO
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
15
15
pF
Capacitance
Output
Capacitance
–
–
–
–
pF
pF
I/O Capacitance
Table 12-5. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 C, VDD = 1.8 V to 5.5 V)
°
Parameter
Symbol
Conditions
Min
Typ
Max
Units
tCY
VDD = 2.7 V to 5.5 V
Instruction Cycle
Time
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
0.95
0
fTI0
f
TI1
TCL0, TCL1 Input
Frequency
–
–
1.5
MHz
µs
,
VDD = 1.8 V to 5.5 V
1
–
tTIH0, tTIL0 VDD = 2.7 V to 5.5 V
tTIH1, tTIL1
TCL0, TCL1 Input
High, Low Width
0.48
VDD = 1.8 V to 5.5 V
1.8
10
tINTH, tINTL
tRSL
Interrupt Input
High, Low Width
INT0, INT1, INT2, INT4,
KS0–KS7
–
–
–
–
µs
µs
RESET Input Low
Width
Input
10
12-6
KS57C0616/P0616
ELECTRICAL DATA
Main Osc. Freq. (Divided by 4)
6 MHz
CPU CLOCK
1.5 MHz
1.05 MHz
4.2 MHz
15.625 kHz
1
2
3
4
5
6
7
1.8
2.7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1 / n x oscillator frequency (n = 4, 8, or 64)
Figure 12-1. Standard Operating Voltage Range
Table 12-6. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
VDDDR
IDDDR
tSREL
Conditions
Min
1.8
–
Typ
–
Max
5.5
10
–
Unit
V
Data retention supply voltage
Data retention supply current
Release signal set time
–
VDDDR = 1.8 V
–
0.1
–
µA
µs
0
217/fx
tWAIT
Oscillator stabilization wait
Released by RESET
–
–
ms
time (1)
(2)
Released by interrupt
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
12-7
ELECTRICAL DATA
KS57C0616/P0616
TIMING WAVEFORMS
INTERNAL RESET
OPERATION
IDLE MODE
STOP MODE
OPERATING
MODE
DATA RETENTION MODE
V
DD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
tSREL
Figure 12-2. Stop Mode Release Timing when Initiated by RESET
IDLE MODE
NORMAL
STOP MODE
OPERATING
MODE
DATA RETENTION
V
DD
VDDDR
tSREL
EXECUTION OF
STOP INSTRUCTION
tWAIT
POWER-DOWN MODE TERMINATING
(INTERRUPT REQUEST)
Figure 12-3. Stop Mode Release Timing when Initiated by Interrupt Request
12-8
KS57C0616/P0616
ELECTRICAL DATA
V
V
V
V
0.8
0.2
0.8
0.2
DD
DD
DD
MEASUREMENT
POINTS
DD
Figure 12-4. A.C. Timing Measurement Points (Except for XIN)
1 / f
x
t
XL
t
XH
X
IN
-0.1 V
V
DD
0.1 V
Figure 12-5. Clock Timing Measurement at XIN
1 / f
TI
t
t
TIH
TIL
TCL
0.8 V
0.2 V
DD
DD
Figure 12-6. TCL Timing
12-9
ELECTRICAL DATA
KS57C0616/P0616
tRSL
RESET
VDD
0.2
Figure 12-7. Input Timing for RESET Signal
tINTL
tINTH
INT0, 1, 2, 4
KS0 to KS7
0.8 V
0.2 V
DD
DD
Figure 12-8. Input Timing for External Interrupts and Quasi-Interrupts
12-10
KS57C0616/P0616
MECHANICAL DATA
13 MECHANICAL DATA
OVERVIEW
The KS57C0616 microcontroller is currently available in 42-pin SDIP and 44-pin QFP package.
#42
#22
°
0 ~ 15
42-SDIP-600
#1
#21
39.10 ± 0.2
(1.77)
1.778
0.50 ± 0.1
1.00 ± 0.1
NOTE: Dimensions are in millimeters.
Figure 13-1. 42-Pin SDIP Package Dunebsuibs
13-1
MECHANICAL DATA
KS57C0616/P0616
°
0~8
13.20 ± 0.30
10.00 ± 0.2
0.1 MAX
44-QFP-1010B
#44
#1
+ 0.10
- 0.05
0.0 MIN
2.05 ± 0.1
2.30 MAX
0.35
0.80
1.00
NOTE: Dimensions are in millimeters.
Figure 13-2. 44-Pin QFP Package Dimensions
13-2
KS57C0616/P0616
KS57P0616 OTP
14 KS57P0616 OTP
OVERVIEW
The KS57P0616 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS57C0616 microcontroller. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by a
serial data format.
The KS57P0616 is fully compatible with the KS57C0616, both in function and in pin configuration. Because of its
simple programming requirements, the KS57P0616 is ideal for use as an evaluation chip for the KS57C0616.
P1.0/INT0
P1.1/INT1
P1.2/INT2
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P9.2
P9.1
P9.0
P9.3
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
P1.3/INT4
P2.0/TCLO0
P2.1/TCLO1
P2.2/CLO
P2.3/BUZ
SDAT/P3.0/TCL0
SCLK/P3.1/TCL1
9
10
11
12
13
14
15
16
17
18
19
20
21
V
/V
DD DD
V
/V
SS SS
X
OUT
X
IN
/TEST
V
PP
P4.0/BTCO
P4.1
RESET /RESET
P3.2
P3.3
P4.2
NOTE: The bolds indicate an OTP pin name.
Figure 14-1. KS57P0616 Pin Assignments (42-SDIP)
14-1
KS57P0616 OTP
KS57C0616/P0616
P2.2/CLO
P2.3/BUZ
SDAT/P3.0/TCL0
SCLK/P3.1/TCL1
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
V
/V
DD DD
V
/V
SS SS
X
OUT
X
IN
/TEST
V
PP
9
10
11
P4.0/BTCO
P4.1
P5.2
P5.1
NOTE: The bolds indicate an OTP pin name.
Figure 14-2. KS57P0616 Pin Assignments (44-QFP)
14-2
KS57C0616/P0616
KS57P0616 OTP
Table 14-1. KS57P0616 Pin Descriptions Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P3.0
Pin Name
Pin No.
I/O
Function
SDAT
9 (3)
I/O
Serial data pin. Output port when reading and input
port when writing. Can be assigned as a
Input/push-pull output port.
P3.1
SCLK
10 (4)
15 (9)
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing (indicates
that OTP enters into the writing mode). When 12.5
V is applied, OTP is in writing mode and when 5 V
is applied, OTP is in reading mode. (Option)
18 (12)
I
I
Chip initialization
RESET
RESET
VDD/VSS
VDD/VSS
Logic power supply pin. VDD should be tied to
+ 5 V during programming.
11/12 (5/6)
NOTE: Parentheses indicate pin numbers of 44-QFP package.
Table 14-2. Comparison of KS57P0616 and KS57C0616 Features
Characteristic
Program Memory
Operating Voltage (VDD
KS57P0616
KS57C0616
16-Kbyte mask ROM
1.8 V to 5.5 V
16-Kbyte EPROM
)
1.8 V to 5.5 V
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
–
Pin Configuration
42 SDIP/44 QFP
42 SDIP/44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of the KS57P0616, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 14-3 below.
Table 14-3. Operating Mode Selection Criteria
VDD
VPP
REG/
MEM
Address
(A15–A0)
R/W
Mode
(TEST)
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
14-3
KS57P0616 OTP
KS57C0616/P0616
Table 14-4. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
VDD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
V
VI1
VO
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 15
All I/O ports
V
V
Output Voltage
Output Current High
–
IOH
One I/O port active
mA
All I/O ports active
One I/O port active
– 35
IOL
Output Current Low
+ 30 (Peak value)
mA
+ 15 (note)
All I/O ports active
+ 100 (Peak value)
+ 60 (note)
°
TA
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
C
°
C
Tstg
– 65 to + 150
NOTE: The values for output current low (IOL) are calculated as peak value ´
Duty .
Table 14-5. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those
specified below for VIH2–VIH3
–
V
VIH2
VIH3
VIL1
0.8 VDD
VDD
VDD
Ports 1, 3, 6, 7, and RESET
XIN and XOUT
V
DD – 0.1
0.3 VDD
Input low
voltage
All input pins except those
specified below for VIL2–VIL3
–
–
V
VIL2
VIL3
0.2 VDD
0.1
Ports 1, 3, 6, 7, and RESET
XIN and XOUT
14-4
KS57C0616/P0616
KS57P0616 OTP
Table 14-5. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
IOH = – 1 mA
Ports except 1
VDD = 4.5 V to 5.5 V
Min
Typ
Max
Units
VOH
VDD – 1.0
Output high
voltage
–
–
V
VOL1
Output low
voltage
–
–
2
V
V
IOL = 15 mA, Ports 4 and 5 only
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
–
–
–
–
0.4
2
VOL2
VDD = 4.5 V to 5.5 V
IOL= 4 mA, all out ports except 4, 5
VDD = 1.8 to 5.5 V, IOL = 1.6 mA
V = V
–
–
–
–
0.4
3
ILIH1
Input high
µA
I
DD
leakage current
All input pins except those specified
below
ILIH2
VI = VDD
20
XIN and XOUT
ILIL1
ILIL2
VI = 0 V
Input low
leakage current
–
–
– 3
µA
All input pins except below and RESET
VI = 0 V
– 20
XIN and XOUT only
ILOH
ILOL
RL1
VO = VDD
Output high
leakage current
–
–
–
–
3
µA
µA
kW
All out pins
VO = 0 V
Output low
leakage current
– 3
100
200
All out pins
VDD = 5 V; VI = 0 V
except RESET
VDD = 3 V
Pull-up resistor
25
50
50
100
RL2
VDD = 5 V; V = 0 V; RESET
I
100
200
250
500
400
800
VDD = 3 V
14-5
KS57P0616 OTP
KS57C0616/P0616
Table 14-5. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Symbol
Conditions
Min
Typ
Max Units
IDD1
6.0 MHz
–
2.6
8.0
4.0
mA
mA
µA
Run mode; VDD = 5 V ± 10%
current (1)
crystal oscillator; C1 = C2 = 22 pF 3.58 MHz
1.7
VDD = 3 V ± 10%
6.0 MHz
1.2
0.7
4.0
2.3
3.58 MHz
IDD2
6.0 MHz
–
–
0.7
0.6
2.5
1.8
Idle mode; VDD = 5 V ± 10%
crystal oscillator; C1 = C2 = 22 pF 3.58 MHz
VDD = 3 V ± 10%
6.0 MHz
0.2
0.2
1.5
1.0
3.58 MHz
IDD3
Stop mode; VDD = 5 V ± 10%
Stop mode; VDD = 3 V ± 10%
0.2
0.1
3.0
2.0
NOTES:
1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers.
2. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
14-6
KS57C0616/P0616
KS57P0616 OTP
Table 14-6. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 C, VDD = 1.8 V to 5.5 V)
°
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Ceramic
0.4
–
6.0
MHz
Xin
Xout
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
3.0
4
Stabilization time (2)
ms
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Crystal
0.4
6.0
MHz
Xin
Xout
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
3.0
10
Stabilization time (2)
ms
VDD = 2.7 V to 5.5 V
External
Clock
0.4
6.0
MHz
Xin
Xout
XIN input frequency (1)
VDD = 1.8 V to 5.5 V
–
0.4
–
–
3.0
XIN input high and low
83.3
1,250
ns
level width (tXH, tXL
)
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
14-7
KS57P0616 OTP
KS57C0616/P0616
Table 14-7. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Symbol
Condition
Min
Typ
Max
Units
CIN
COUT
CIO
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
15
15
pF
Capacitance
Output
Capacitance
–
–
–
–
pF
pF
I/O Capacitance
Main Osc. Freq. (Divided by 4)
6 MHz
CPU CLOCK
1.5 MHz
1.05 MHz
0.75 MHz
4.2 MHz
3 MHz
15.625 kHz
1
2
3
4
5
6
7
1.8
2.7
SUPPLY VOLTAGE (V)
CPU CLOCK = 1 / n x oscillator frequency (n = 4, 8, or 64)
Figure 14-3. Standard Operating Voltage Range
14-8
KS57C0616/P0616
KS57P0616 OTP
START
Address= First Location
V
=5V, V =12.5V
PP
DD
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 14-4. OTP Programming Algorithm
14-9
KS57P0616 OTP
KS57C0616/P0616
NOTES
14-10
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