KS57C5616 [SAMSUNG]
The KS57C5616/P5616 single-chip CMOS microcontroller is designed for high performance in the application for Caller-ID, Telephone using Samsungs newes; 该KS57C5616 / P5616单芯片CMOS微控制器是专为高性能申请来电显示，电话使用三星newes
| 型号： | KS57C5616 |
| 厂家： | 
SAMSUNG |
| 描述： | The KS57C5616/P5616 single-chip CMOS microcontroller is designed for high performance in the application for Caller-ID, Telephone using Samsungs newes |
| 文件： | 总42页 (文件大小：357K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS57C5616/P5616
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The KS57C5616/P5616 single-chip CMOS microcontroller is designed for high performance in the application for
Caller-ID, Telephone using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangable Microcontrollers).
Featuring a DTMF generator, up-to-960-dot LCD direct drive capability, one 8-bit timer/counter and flexible two
8-bit timer/counters, and serial I/O interface, the KS57C5616/P5616 offer an excellent design solution for a wide
variety of applications requiring DTMF, LCD support.
Up to 43 (including COM/SEG) pins in the 100-pin QFP package can be dedicated to I/O. Nine vectored
interrupts provide a fast response to internal and external events. In addition the advanced CMOS technology a of
the KS57C5616/P5616 ensures low power consumption with a wide operating voltage range.
OTP
The KS57C5616 microcontroller is also available in OTP (One Time Programmable) version, KS57P5616.
KS57P5616 microcontroller has an on-chip 16K-byte one-time-programmable EPROM instead of masked ROM.
The KS57P5616 is comparable to KS57C5616, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS57C5616/P5616
FEATURES SUMMARY
Memory
8-bit Serial I/O Interface
•
•
•
8-bit transmit/receive mode
8-bit receive mode
•
•
16K ´ 8-bit ROM
5,120 ´ 4-bit RAM (excluding LCD RAM)
LSB-first or MSB-first transmission selectable
I/O Pins
LCD Controller/Driver
•
Input only:4pins (Not including COM/SEG)
6pins (Including COM/SEG)
•
•
•
•
•
60 SEG x 16 COM terminals
8, 12 and 16 com selectable
COM 8–15: shared with port
SEG40–59: shared with port
Two kinds of LCD bias resistor value
•
I/O: 15pins (Not including COM/SEG)
43pins (Including COM/SEG)
Memory-Mapped I/O Structure
Data memory bank 15
8-bit Basic Timer
•
Bit Sequential Carrier
•
Supports 16-bit serial data transfer in arbitrary
format
•
•
Four interval timer functions
Watchdog timer
Interrupts
•
•
•
Four external interrupt vectors
8-bit Timer/Counter
Five internal interrupt vectors
Two quasi-interrupts
•
•
•
•
Programmable 8-bit timer
External event counter
Power-Down Modes
Arbitrary clock frequency output
External clock signal divider
•
•
•
Idle mode (only CPU clock stops)
Stop mode (main system oscillation stops)
Subsystem clock stop mode
16-Bit Timer/Counter
•
•
•
•
•
•
Programmable 16-bit timer
External event counter
Oscillation Sources
•
•
•
RC, Crystal or Ceramic for system clock
Oscillation frequency: 0.4–6.0 MHz
CPU clock divider circuit (by 4, 8, or 64)
Arbitrary clock frequency output
External clock signal divider
Configurable as two 8-bit Timers
Serial I/O interface clock generator
Instruction Execution Times
•
•
•
1.12, 2.23, 17.88 µs at 3.58 MHz
0.67, 1.33, 10.7 µs at 6.0 MHz
122 µs at 32.768 kHz (subsystem)
Watch Timer
•
Time interval generation: 0.5 s, 3.9 ms
at 32.768 kHz
Operating Temperature
•
4 frequency outputs to BUZ pin (0.5, 1, 2, 4 kHz)
at 32.768 kHz
°
°
•
– 40 C to 85 C
Comparator
Operating Voltage Range
•
4-channel mode: Internal reference (4-bit
resolution); 16-step variable reference voltage
•
•
•
1.8 V to 5.5 V (except DTMF and Comparator)
2 V to 5.5 V (include DTMF)
•
3-channel mode: External reference
4.0 V to 5.5 V (include Comparator)
DTMF Generator
Package Type
100-pin QFP (1420C)
•
16 dual-tone for tone dialing
•
1-2
KS57C5616/P5616
PRODUCT OVERVIEW
BLOCK DIAGRAM
P7.0/SEG55/CIN0
P7.1/SEG54/CIN1
P7.2/SEG53/CIN2
P7.3/SEG52/CIN3
Basic
Timer
Watchdog
Timer
Comparator
Input Port 1
I/O Port 2
XIN
XOUT
RESET
XTIN XTOUT
P1.0-P1.3/
INT0-INT4
Watch
Timer
P2.0/CLO
P2.1/VLC1
P2.2
Interrupt
Control
Block
Instruction
Register
VLC1
Clock
P3.0/TCLO0
P3.1/TCLO1
P3.2/TCL0
P3.3/TCL1
COM0-COM7
LCD
Driver/
Controller
I/O Port 3
P4.0-P5.3/
COM8-COM15
SEG0-SEG39
Program
Counter
Internal
Interrupts
P4.0-P4.3/
COM8-COM11
P10.3-P6.0/
SEG40-SEG59
I/O Port 4
I/O Port 5
P5.0-P5.3/
COM12-COM15
Serial I/O
I/O Port 0
Instruction Dcoder
P6.0-P6.3
SEG59-SEG56/
KS4-KS7
Program
Status Word
I/O Port 6
I/O Port 7
P0.0/SCK/KO
P0.1/SO/K1
P0.2/SI/K2
Arithmetic
and
Logic Unit
P7.0/SEG55/CIN0
P7.1/SEG54/CIN1
P7.2/SEG53/CIN2
P7.3/SEG52/CIN3
P0.3/BUZ/K3
Stack
Pointer
DTMF
Generator
DTMF
P8.0/SEG51/LCDCK
P8.1/SEG50/LCDSY
P8.2/SEG49
I/O Port 8
I/O Port 9
P8.3/SEG48
5K x 4-bit
16-Bit
Timer/Counter
(Two 8Bit
P9.0-P9.3/
SEG47-SEG44
RAM
8-Bit
Timer/
Counter
Timer/Counter)
P10.0-P10.3/
SEG43-SEG40
16KB ROM
I/O Port 10
Figure 1-1. KS57C5616 Block Diagram
1-3
PRODUCT OVERVIEW
KS57C5616/P5616
PIN ASSIGNMENTS
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P10.3/SEG40
P10.2/SEG41
P10.1/SEG42
P10.0/SEG43
P9.3/SEG44
P9.2/SEG45
P9.1/SEG46
P9.0/SEG47
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
1
2
3
4
5
6
7
8
9
DTMF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P0.0/SCK/K0
P0.1/SO/K1
P0.2/SI/K2
P0.3/BUZ/K3
V
DD
SS
OUT
IN
V
X
X
TEST
XTIN
XTOUT
RESET
P8.3/SEG48
P8.2/SEG49
P8.1/SEG50/LCDSY
P8.0/SEG51/LCDCK
P7.3/SEG52/CIN3
P7.2/SEG53/CIN2
P7.1/SEG54/CIN1
P7.0/SEG55/CIN0
P6.3/SEG56/K7
P6.2/SEG57/K6
P6.1/SEG58/K5
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/VLC1
P2.2
P3.0/TCLO0
Figure 1-2. KS57C5616 Pin Assignments (100-QFP Package)
1-4
KS57C5616/P5616
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. KS57C5616 Pin Descriptions
Description
Pin Name
P0.0
P0.1
P0.2
P0.3
Pin Type
I/O
Share Pin
4-bit I/O port.
SCK/K0
SO/K1
SI/K2
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
BUZ/K3
Individual pins are software configurable as open-drain or
push-pull output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P1.0
P1.1
P1.2
P1.3
I
4-bit input port.
1-bit and 4-bit read and test is possible.
4-bit pull-up resistors are software assignable.
INT0
INT1
INT2
INT4
P2.0
P2.1
P2.2
I/O
I/O
Same as port 0 except that port 2 is a 3-bit I/O port.
Same as port 0.
CLO
VLC1
P3.0
P3.1
P3.2
P3.3
TCLO0
TCLO1
TCL0
TCL1
P4.0–P4.3
P5.0–P5.3
I/O
4-bit I/O ports.
COM8–COM11
COM12–COM15
1-, 4-bit or 8-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
P6.0–P6.3
I/O
I/O
Same as P4, P5.
SEG59–
SEG56/K4-K7
P7.0–P7.3
P8.0–P8.1
SEG55/CIN0–
SEG52/CIN3
Input ports.
SEG51/LCDCK
SEG50/LCDSY
1-, 4-bit or 8-bit read and test is possible.
4-bit pull-up resistors are software assignable; pull-up
resistors are automatically disabled for output pins.
These pins can not be used as push-pull output. Refer to
the NOTES of Table 10-3. Port Mode Group Flags.
P8.2–P8.3
I/O
Same as P4, P5.
SEG49
SEG48
P9.0–P9.3
SEG47–SEG44
SEG43–SEG40
P0.0/K0
P10.0–P10.3
I/O
I/O
I/O
Same as P4, P5.
Serial I/O interface clock signal.
Serial data output.
SCK
SO
P0.1/K1
1-5
PRODUCT OVERVIEW
KS57C5616/P5616
Share Pin
Table 1-1. KS57C5616 Pin Descriptions (Continued)
Pin Name
Pin Type
Description
Serial data input.
SI
I/O
I/O
I
P0.2/K2
BUZ
0.5, 1, 2, or 4 kHz frequency output for buzzer sound.
P0.3/K3
INT0, INT1
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
P1.0, P1.1
INT2
INT4
I
I
Quasi-interrupt with detection of rising or falling edges.
P1.2
P1.3
External interrupt with a detection of rising and falling
edge.
CLO
I/O
I/O
I/O
I/O
I/O
I/O
Clock output .
P2.0
P3.0
P3.1
P3.2
P3.3
TCLO0
TCLO1
TCL0
TCL1
Timer/counter 0 clock output.
Timer/counter 1 clock output.
External clock input for timer/counter 0.
External clock input for timer/counter 1.
CIN0
CIN1
CIN2
CIN3
4-Channel comparator input
CIN0–CIN2: comparator input only
CIN3: comparator input or external reference input
P7.0/SEG55
P7.1/SEG54
P7.2/SEG53
P7.3/SEG52
DTMF
O
DTMF output
–
LCDCK
I/O
I/O
O
LCD clock output
P8.0/SEG51
LCDSY
LCD synchronization clock output.
LCD common signal output.
P8.1/SEG50
COM0–COM7
COM8–COM11
COM12–COM15
SEG0–SEG39
SEG40–SEG59
K0–K3
–
I/O
P4.0–P4.3
P5.0–P5.3
O
LCD segment signal output.
–
I/O
I/O
P10.3–P6.0
External interrupt (triggering edge is selectable)
P0.0–P0.3
K4–K7
P6.0–P6.3
V
–
–
I
Main power supply.
Ground.
–
DD
V
SS
–
Reset signal.
–
RESET
VLC1
–
LCD power supply.
P2.1
XIN
X
OUT
–
–
I
Crystal, Ceramic or RC oscillator pins for system clock.
Crystal oscillator pins for subsystem clock.
–
–
–
,
XTIN, XTOUT
TEST
Chip test input pin.
Hold GND when the device is operating.
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-6
KS57C5616/P5616
PRODUCT OVERVIEW
Table 1-2. Supplemental KS57C5616 Pin Data
Pin Names
Share Pins
I/O Type
RESET Value
Circuit Type
P0.0–P0.3
SCK/K0, SO/K1,
SI/K2, BUZ/K3
I/O
Input
E-4
P1.0–P1.3
INT0, INT1 and
INT2, INT4
I
Input
A-4
P2.0
CLO
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
Input
Input
Input
E-4
E-7
E-4
E-2
E-4
H-24
P2.1
VLC1
P2.2
–
P3.0–P3.1
P3.2–P3.3
TCLO0, TCLO1
TCL0, TCL1
P4.0–P4.3
P5.0–P5.3
COM8–COM11
COM12–COM15
I/O
I/O
H-25
H-26
P6.0–P6.3
SEG59/K4–
SEG56/K7
Input
Input
P7.0–P7.2
SEG55/CIN0–
SEG53/CIN2
P7.3
SEG52/CIN3
I/O
I/O
I/O
I/O
I/O
Input
Input
H-27
H-28
H-24
H-24
H-24
P8.0–P8.1
P8.2–P8.3
P9.0–P9.3
P10.0–P10.3
COM0–COM7
SEG0–SEG39
DTMF
SEG51–SEG50
SEG49–SEG48
Input
SEG47–SEG44
Input
SEG43–SEG40
Input
–
–
–
–
O
O
O
–
High
H-3
H-3
G-7
–
High
High impedance
–
VDD
VSS
–
–
–
–
–
–
–
I
–
–
–
B
–
–
RESET
V
LC1
–
–
XIN
X
OUT
,
XTIN XT
,
–
–
–
I
–
–
–
–
OUT
TEST
1-7
KS57C5616/P5616 (Preliminary Spec)
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
N-Channel
In
In
Schmitt Trigger
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type B
DD
V
DD
V
Pull-Up
Resistor
P-CH
Pull-Up
Resistor
Enable
Data
Out
N-CH
Output
DIsable
In
Schmitt Trigger
Figure 1-4. Pin Circuit Type A-4
Figure 1-6. Pin Circuit Type C
1-8
KS57C5616/P5616
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
PNE
VDD
Pull-up
Resistor
Enable
P-CH
N-CH
Data
I/O
Output
DIsable
Figure 1-7. Pin Circuit Type E-2
VDD
Pull-up
Resistor
PNE
V
DD
Pull-up
Resistor
Enable
P-CH
N-CH
I/O
Data
Output
DIsable
Schmitt Trigger
Figure 1-8. Pin Circuit Type E-4
1-9
PRODUCT OVERVIEW
KS57C5616/P5616
VDD
Pull-up
Resistor
PNE
VDD
Pull-up
Resistor
Enable
P-CH
N-CH
I/O
Data
Output
DIsable
Digital
Input
VLCEN
VLC1
Figure 1-9. Pin Circuit Type E-7
1-10
KS57C5616/P5616
PRODUCT OVERVIEW
VLC1
VLC2
VLC3
COM/SEG
VLC4
VLC5
VLC6
Figure 1-10. Pin Circuit Type H-3
1-11
PRODUCT OVERVIEW
KS57C5616/P5616
VLC1
VLC2
VLC3
SEG/COM
Data
Out
Output
DIsable
VLC4
VLC5
VSS
Figure 1-11. Pin Circuit Type H-23
1-12
KS57C5616/P5616
PRODUCT OVERVIEW
DD
V
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Circuit
Type H-23
Data
Circuit
Type C
I/O
Output
DIsable
Figure 1-12. Pin Circuit Type H-24
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Circuit
Type H-23
Data
Circuit
I/O
Type C
Output
DIsable
Figure 1-13. Pin Circuit Type H-25
1-13
PRODUCT OVERVIEW
KS57C5616/P5616
DD
V
Pull-up
Resistor
Pull-up
Resistor
Enable
P-CH
COM/SEG
LCD_ON
Circuit
Type H-23
Data
Circuit
Type C
I/O
Output
DIsable
Analog
Input SEL
Digital In
Analog In
Figure 1-14. Pin Circuit Type H-26
1-14
KS57C5616/P5616
PRODUCT OVERVIEW
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
P-CH
COM/SEG
Circuit
Type H-23
LCD OUT EN
Data
Circuit
Type C
I/O
Output
DIsable
Analog
Input SEL
Digital In
External
REF SEL
Analog In
External
REF In
Figure 1-15. Pin Circuit Type H-27
1-15
PRODUCT OVERVIEW
KS57C5616/P5616
VDD
Pull-up
Resistor
Pull-up
Resistor
Enable
COM/SEG
LCD_ON
Circuit
Type H-23
LCDCK/CLDSY
Circuit
Type C
LCDCK/LCDSY
Enable
I/O
Output
DIsable
Figure 1-16. Pin Circuit Type H-28
-
DTMF Out
+
Disable
Figure 1-17. Pin Circuit Type G-7
1-16
KS57C5616/P5616
ELECTRICAL DATA
16 ELECTRICAL DATA
OVERVIEW
In this section, information on KS57C5616 electrical characteristics is presented as tables and graphics. The
information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— Main system clock oscillator characteristics
— Subsystem clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at X
IN
— Clock timing measurement at XT
IN
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
— Serial data transfer timing
16-1
ELECTRICAL DATA
KS57C5616/P5616
Table 16-1. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Units
V
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
V
DD
V
– 0.3 to V
+ 0.3
Ports 0–10
V
V
I
DD
DD
V
– 0.3 to V
+ 0.3
Output Voltage
Output Current High
–
O
I
One I/O pin active
All I/O pins active
One I/O pin active
– 15
– 35
mA
OH
I
Output Current Low
+ 30 (Peak value)
mA
OL
+ 15 (note)
+ 100 (Peak value)
+ 60 (note)
Total for ports 0, 2–10
T
A
°
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
C
T
stg
°
C
– 65 to + 150
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ´ Duty .
Table 16-2. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
DD
= 1.8 V to 5.5 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
IH1
0.7 V
V
DD
Input High
Voltage
All input pins except those
specified below for V –V
–
V
DD
IH2 IH3
V
IH2
0.8 V
DD
V
DD
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
V
IH3
X , X
IN
, and XT
IN
V
DD
– 0.1
V
DD
OUT
V
0.3V
Input Low
Voltage
All input pins except those
specified below for V –V
–
–
V
IL1
IL2
IL3
DD
IL2 IL3
V
0.2V
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
DD
V
V
X , X
IN
, and XT
IN
0.1
–
OUT
V
= 4.5 V to 5.5 V
= – 1 mA
V
– 1.0
DD
Output High
Voltage
–
–
V
V
OH
DD
I
OH
Ports 0, 2–10
V
V = 4.5 V to 5.5 V
Output Low
Voltage
–
2.0
OL
DD
= 15 mA
I
OL
Ports 0, 2–10
16-2
KS57C5616/P5616
ELECTRICAL DATA
Table 16-2. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
I
V = V
DD
All input pins except those
specified below for I
Input High
Leakage
Current
–
–
3
µA
LIH1
I
LIH2
I
V = V
20
LIH2
I
DD
X , XT
IN IN
I
V = 0 V
I
All input pins except RESET, X
XT
IN
Input Low
Leakage
Current
–
–
– 3
µA
LIL1
,
IN
I
V = 0 V
I
– 20
3
LIL2
X
IN
, XT
IN
I
V
O
= V
Output High
Leakage
Current
–
–
–
–
µA
µA
kW
LOH
DD
All output pins
V = 0 V
O
I
Output Low
Leakage
Current
– 3
LOL
All output pins
R
LI
V = 0 V; V
= 5 V, Port 0–10
Pull-Up
25
47
100
I
DD
Resistor
V
= 3 V
50
100
200
40
95
220
450
55
200
400
800
70
DD
R
L2
V = 0 V; V
I
= 5 V, RESET
–
DD
V
DD
= 3 V
R
LCD1
LCD Voltage
Dividing
kW
Resistor (Note)
R
20
–
28
–
35
LCD2
V
V
V
DD
= 2.7 V to 5.5 V
120
mV
| DD-COMi|
DC
– 15 µA per common pin
Voltage Drop
(i = 0–15)
V
V
DS
V
= 2.7 V to 5.5 V
–
–
120
| DD-SEGx|
DD
– 15 µA per segment pin
Voltage Drop
(x = 0–59)
V
V
LC1
V
= 2.7 V to 5.5 V
V
DD
–0.2
V
DD
V
DD
+0.2
V
LCX Output
DD
LCD clock = 0 Hz
Voltage
V
LC2
V
LC3
V
LC4
V
LC5
0.8V –0.2 0.8V
DD
0.8V +0.2
DD
DD
DD
DD
DD
0.6V –0.2 0.6V
DD
0.6V +0.2
DD
0.4V –0.2 0.4V
DD
0.4V +0.2
DD
0.2V –0.2 0.2V
DD
0.2V +0.2
DD
NOTE:
R
is the LCD Voltage dividing resistor when LCON.1 = “0”, and R when LCON.1 = “1”.
LCD2
LCD1
16-3
ELECTRICAL DATA
KS57C5616/P5616
Table 16-2. D.C. Electrical Characteristics (Concluded)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Supply
Symbol
Conditions
Min
Typ
Max
Units
I
–
3.9
7.0
mA
Run mode; V
DD
= 5 V ± 10%
DD1
(1)
Current
3.58 MHz X-tal oscillator,
C1 = C2 = 22pF
(DTMF on)
–
–
2.0
4.0
V
= 3 V ± 10%
DD
Run mode;
= 5 V ± 10%
I
6.0 MHz
3.58 MHz
4.1
2.7
8.0
5.0
DD2
(DTMF off)
V
DD
Crystal oscillator
C1 = C2 = 22pF
6.0 MHz
3.58 MHz
1.9
1.2
4.0
2.3
V
= 3 V ± 10%
DD
I
Idle mode;
= 5 V ± 10%
6.0 MHz
3.58 MHz
–
1.2
0.9
2.5
1.8
DD3
V
DD
Crystal oscillator
C1 = C2 = 22pF
6.0 MHz
3.58 MHz
0.5
0.4
1.5
1.0
V
= 3 V ± 10%
DD
(2)
(2)
–
–
–
17.5
45
Run mode; V
DD
32 kHz Crystal oscillator
= 3 V ± 10%
mA
mA
mA
I
I
DD4
4.8
15
Idle mode; V = 3 V ± 10%
DD
DD5
I
32 kHz Crystal oscillator
Stop mode;
SCMOD = 0000
DD6
XT = 0 V
2.0
0.6
5
3
V
V
= 5 V ± 10%
= 3 V ± 10%
DD
DD
IN
Stop mode;
SCMOD = 0100
0.2
0.1
3
2
V
= 5 V ± 10%
DD
DD
V
= 3 V ± 10%
Row Tone level
V
V
= 2 to 5. 5 V
– 16.0
– 14.0
– 11.0
dBV
%
DD
ROW
RL = 12 KW; Temp = – 30 to 60 °C
= 2 to 5. 5 V
Ratio of Column
to Row tone
dBCR
THD
V
1
–
2
–
3
5
DD
RL = 12 KW; Temp = – 30 to 60 °C
V = 2 to 5. 5 V
DD
Distortion
(Dual tone)
1 MHz band
RL = 12 KW; Temp = – 30 to 60 °C
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and
output port drive currents.
16-4
KS57C5616/P5616
ELECTRICAL DATA
Table 16-3. Main System Oscillator Characteristics
(TA = – 40 °C + 85 C, VDD = 1.8 V to 5.5 V)
°
Oscillator
Clock
Parameter
Test Condition
Min
Typ Max Units
Configuration
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Ceramic
0.4
–
6.0
MHz
XIN
XOUT
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
0.4
–
–
–
3
4
Stabilization time (2)
Stabilization occurs
when VDD is equal to
ms
the minimum
oscillator voltage
range; VDD = 3.0 V
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Crystal
0.4
–
6.0
MHz
IN
X
OUT
X
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
–
3
Stabilization time (2)
10
30
6.0
ms
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
–
XIN input frequency (1)
External
Clock
0.4
MHz
XIN
XOUT
VDD = 1.8 V to 5.5 V
–
0.4
–
–
3
XIN input high and low
83.3
1,250
ns
level width (tXH, tXL
)
RC
Oscillator
Frequency
–
–
2
–
–
MHz
R = 25 kW, VDD = 5 V
IN
X
OUT
X
R
1
R = 40 kW, VDD = 3 V
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
16-5
ELECTRICAL DATA
KS57C5616/P5616
Table 16-4. Recommended Oscillator Constants
°
°
(T = – 40 C to + 85 C)
A
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
33
(2)
C2
33
(2)
MIN
2.0
MAX
5.5
TDK
3.58 MHz–6.0 MHz
3.58 MHz–6.0 MHz
Leaded Type
FCR” ðÿM5
2.0
5.5
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz–6.0 MHz
2.0
5.5
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
Table 16-5. Subsystem Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
DD
= 1.8 V to 5.5 V)
A
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
V
DD
= 1.8 V to 5.5 V
Crystal
Oscillator
32
32.768
35
kHz
XTIN XTOUT
C1
C2
Stabilization time (2)
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V
= 1.8 V to 5.5 V
= 1.8 V to 5.5 V
–
–
1.0
–
2
s
10
XT input frequency (1)
IN
External
Clock
32
–
100
kHz
XTIN XTOUT
Open
XT input high and low
IN
–
5
–
15
µs
level width (t )
, t
XTL XTH
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
16-6
KS57C5616/P5616
ELECTRICAL DATA
Table 16-6. Input/Output Capacitance
°
(T = 25 C, V
= 0 V )
A
DD
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
C
IN
f = 1 MHz; Unmeasured pins
–
–
15
15
15
pF
are returned to V
SS
C
OUT
Output
Capacitance
–
–
–
–
pF
pF
C
IO
I/O Capacitance
Table 16-7. Comparator Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 4.0 V to 5.5 V, VSS = 0 V)
A
DD
Parameter
Symbol
Condition
Min
Typ
Max
Units
VDD
Input Voltage
Range
–
–
0
–
V
VREF
VCIN
VDD
± 150
3
Reference Voltage
Range
–
–
–
0
–
–
–
–
V
Input Voltage
Accuracy
mV
mA
ICIN, IREF
Input Leakage
Current
– 3
16-7
ELECTRICAL DATA
KS57C5616/P5616
Table 16-8. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
t
V
= 2.7 V to 5.5 V
Instruction Cycle
0.67
–
64
µs
CY
, f
DD
(note)
Time
V
V
= 1.8 V to 5.5 V
= 2.7 V to 5.5 V
1.33
0
64
DD
f
TCL0, TCL1 Input
Frequency
–
–
1.5
MHz
µs
TI0 TI1
DD
V
V
= 1.8 V to 5.5 V
= 2.7 V to 5.5 V
1
–
DD
t
t
, t
TIH0 TIL0
TCL0, TCL1 Input
High, Low Width
0.48
DD
, t
TIH1 TIL1
V
V
= 1.8 V to 5.5 V
= 2.7 V to 5.5 V
1.8
DD
t
SCK Cycle Time
800
–
–
ns
KCY
DD
External SCK source
Internal SCK source
650
V
DD
= 1.8 V to 5.5 V
3200
External SCK source
Internal SCK source; Output
3800
16-8
KS57C5616/P5616
ELECTRICAL DATA
Table 16-8. A.C. Electrical Characteristics (Continued)
= 1.8 V to 5.5 V)
°
°
(T = – 40 C to + 85 C, V
A
DD
Symbol
, t
Parameter
Conditions
= 2.7 V to 5.5 V
Min
Typ
Max
Units
t
V
DD
SCK High, Low
Width
325
–
–
ns
KH KL
External SCK source
T
/
Internal SCK source
kCY
2–50
V
DD
= 1.8 V to 5.5 V
1600
External SCK source
Internal SCK source
t
/
KCY
2–150
tSIK
V
= 2.7 V to 5.5 V; Input
SI Setup Time to
SCK High
100
–
–
–
–
–
ns
ns
ns
DD
V
DD
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V; Output
= 1.8 V to 5.5 V; Input
= 1.8 V to 5.5 V; Output
= 2.7 V to 5.5 V; Input
150
150
500
400
t
SI Hold Time to
SCK High
KSI
V
DD
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V; Output
= 1.8 V to 5.5 V; Input
= 1.8 V to 5.5 V; Output
= 2.7 V to 5.5 V; Input
400
600
500
–
tKSO
Output Delay for
SCK to SO
300
V
V
V
= 2.7 V to 5.5 V; Output
= 1.8 V to 5.5 V; Input
= 2.7 V to 5.5 V; Output
250
1000
1000
–
DD
DD
DD
t
,
Interrupt Input
High, Low Width
INT0–INT2, INT4, KS0–KS7
10
10
–
–
µs
µs
INTH
t
INTL
t
RESET Input Low
Width
Input
–
RSL
NOTE: Unless specified the otherwise, Instruction Cycle Time condition values assume a main system clock (fx) source.
16-9
ELECTRICAL DATA
KS57C5616/P5616
Main Os. Freq. (Divided by 4)
6MHz
CPU Clock
1.5MHz
4.2MHz
3MHz
1.05MHz
0.75kHz
15.625kHz
1
2
3
4
5
6
7
1.8
2.7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64)
Figure 16-1. Standard Operating Voltage Range
Table 16-9. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
Conditions
–
Min
1.8
–
Typ
–
Max
5.5
10
Unit
V
V
DDDR
Data retention supply voltage
Data retention supply current
I
V
= 1.8 V
0.1
µA
DDDR
DDDR
t
Release signal set time
–
0
–
–
–
–
µs
SREL
217 / fx
t
Oscillator stabilization wait
Released by RESET
ms
WAIT
(1)
time
(2)
Released by interrupt
–
–
NOTES:
1. During the oscillator stabilization wait time, all the CPU operations must be stopped to avoid instability that can occur during
the oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay an execution of CPU instructions during the wait time.
16-10
KS57C5616/P5616
ELECTRICAL DATA
TIMING WAVEFORMS
Internal Reset
Operation
Idle Mode
Stop Mode
Operating
Mode
Data Retention Mode
V
DD
VDDDR
Execution of
STOP Instruction
RESET
t
WAIT
t
SREL
Figure 16-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
Normal
Operating
Mode
Stop Mode
Data Retention Mode
DD
V
DDDR
V
SREL
t
Execution of
STOP Instrction
WAIT
t
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 16-3. Stop Mode Release Timing When Initiated by Interrupt Request
16-11
ELECTRICAL DATA
KS57C5616/P5616
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Measurement
Points
Figure 16-4. A.C. Timing Measurement Points (Except for XIN and XTIN)
1/fx
t
XL
tXH
XIN
VDD - 0.1 V
0.1 V
Figure 16-5. Clock Timing Measurement at X
IN
1/fxt
t
XTL
tXTH
XTIN
VDD - 0.1 V
0.1 V
Figure 16-6. Clock Timing Measurement at XT
IN
16-12
KS57C5616/P5616
ELECTRICAL DATA
TI
1/f
TIL
TIH
t
t
TCL0
DD
DD
0.8 V
0.2 V
Figure 16-7. TCL Timing
t
RSL
RESET
0.2 VDD
Figure 16-8. Input Timing for RESET Signal
16-13
ELECTRICAL DATA
KS57C5616/P5616
t
INTL
tINTH
INT0, 1, 2, 4
K0 to K7
0.8 VDD
0.2 VDD
Figure 16-9. Input Timing for External Interrupts and Quasi-Interrupts
t
KCY
t
KL
tKH
SCK
0.8 VDD
0.2 VDD
t
SIK
tKSI
0.8 VDD
0.2 VDD
SI
Input Data
t
KSO
SO
Output Data
Figure 16-10. Serial Data Transfer Timing
16-14
KS57C5616/P5616
MECHANICAL DATA
17 MECHANICAL DATA
This section contains the following information about the device package:
—
—
—
Package dimensions in millimeters
Pad diagram
Pad/pin coordinate data table
23.90 ± 0.3
20.00 ± 0.2
0-8O
+0.10
_0.05
0.15
0.10 MAX
100-QFP-1420C
#100
#1
0.65
(0.58)
0.30 ± 0.1
0.10 MAX
0.05 MIN
2.65 ± 0.10
3.00 MAX
0.80 ± 0.20
Figure 17-1. 100-QFP Package Dimensions
NOTE : Dimensions are in millimeters.
17-1
MECHANICAL DATA
KS57C5616/P5616
NOTES
17-2
KS57C5616/P5616
KS57P5616 OTP
18 KS57P5616 OTP
OVERVIEW
The KS57P5616 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS57C5616 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by
serial data format.
The KS57P5616 is fully compatible with the KS57C5616, both in function and in pin configuration. Because of its
simple programming requirements, the KS57P5616 is ideal for use as an evaluation chip for the KS57C5616.
18-1
KS57P5616 OTP
KS57C5616/P5616
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
DTMF
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
P10.3/SEG40
P10.2/SEG41
P10.1/SEG42
P10.0/SEG43
P9.3/SEG44
P9.2/SEG45
P9.1/SEG46
P9.0/SEG47
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P0.0/
/K0
SCK
P0.1/SO/K1
SDAT /P0.2/SI/K2
SCLK /P0.3/BUZ/K3
V
V
DD/VDD
SS/VSS
OUT
IN
X
X
V
PP/TEST
XTIN
XTOUT
P8.3/SEG48
P8.2/SEG49
RESET/RESET
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/CLO
P2.1/VLC1
P2.2
P8.1/SEG50/LCDSY
P8.0/SEG51/LCDCK
P7.3/SEG52/CIN3
P7.2/SEG53/CIN2
P7.1/SEG54/CIN1
P7.0/SEG55/CIN0
P6.3/SEG56/K7
P6.2/SEG57/K6
P6.1/SEG58/K5
P3.0/TCLO0
Figure 18-1. KS57P5616 Pin Assignments (100-QFP Package)
18-2
KS57C5616/P5616
KS57P5616 OTP
Table 18-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P0.2
Pin Name
Pin No.
I/O
Function
SDAT
13
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input/push-pull output port.
P0.3
SCLK
14
19
I/O
I
Serial clock pin. Input only pin.
V
(TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading
mode. When OTP is operating, hold GND.
(Option)
PP
22
I
I
Chip initialization
RESET
RESET
V
/V
V
/V
15/16
Logic power supply pin. VDD should be tied to
+5 V during programming.
DD SS
DD SS
Table 18-2. Comparison of KS57P5616 and KS57C5616 Features
Characteristic KS57P5616 KS57C5616
16-Kbyte EPROM
1.8 V to 5.5 V
= 5 V, V (TEST) = 12.5V
Program Memory
16-Kbyte mask ROM
1.8 V to 5.5 V
Operating Voltage (V
)
DD
V
OTP Programming Mode
DD
100 QFP
User Program 1 time
PP
Pin Configuration
100 QFP
EPROM Programmability
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the V
PP
(TEST) pin of the KS57P5616, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 18-3 below.
Table 18-3. Operating Mode Selection Criteria
V
Vpp
(TEST)
5 V
REG/
Address
(A15–A0)
0000H
R/W
Mode
DD
MEM
5 V
0
0
0
1
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
0000H
EPROM program
EPROM verify
0000H
0E3FH
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
18-3
KS57P5616 OTP
KS57C5616/P5616
Table 18-4. Absolute Maximum Ratings
°
(T = 25 C)
A
Parameter
Symbol
Conditions
Rating
Units
V
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
V
DD
V
– 0.3 to V
+ 0.3
Ports 0–10
V
V
I
DD
DD
V
– 0.3 to V
+ 0.3
Output Voltage
Output Current High
–
O
I
One I/O pin active
All I/O pins active
One I/O pin active
– 15
– 35
mA
OH
I
Output Current Low
+ 30 (Peak value)
mA
OL
+ 15 (note)
+ 100 (Peak value)
+ 60 (note)
Total for ports 0, 2–10
°
T
A
Operating Temperature
Storage Temperature
–
–
– 40 to + 85
C
°
C
T
stg
– 65 to + 150
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ´ Duty .
18-4
KS57C5616/P5616
KS57P5616 OTP
Table 18-5. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
V
IH1
0.7V
V
DD
Input High
Voltage
All input pins except those
specified below for V –V
–
V
DD
IH2 IH3
V
IH2
0.8V
V
DD
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
DD
V
IH3
X , X
IN
, and XT
IN
V
DD
– 0.1
V
DD
OUT
V
0.3V
Input Low
Voltage
All input pins except those
specified below for V –V
–
–
V
IL1
IL2
IL3
DD
IL2 IL3
V
0.2V
Ports 0, 1, 2, 6, P3.2, P3.3, and
RESET
DD
V
V
X , X
IN
, and XT
IN
0.1
–
OUT
V
= 4.5 V to 5.5 V
= – 1 mA
V
– 1.0
DD
Output High
Voltage
–
–
V
V
OH
DD
I
OH
Ports 0, 2–10
V
V = 4.5 V to 5.5 V
Output Low
Voltage
–
2.0
3
OL
DD
= 15 mA
I
OL
Ports 0, 2–10
V = V
I
I
Input High
Leakage
Current
–
–
–
–
µA
µA
LIH1
LIH2
I
DD
All input pins except those
specified below for I
LIH2
V = V
20
I
DD
X , XT
IN IN
I
V = 0 V
I
All input pins except RESET, X
XT
IN
Input Low
Leakage
Current
– 3
LIL1
,
IN
I
V = 0 V
I
– 20
3
LIL2
X
IN,
XT
IN
I
V
O
= V
Output High
Leakage
Current
–
–
–
–
µA
µA
LOH
DD
All output pins
I
V
O
= 0 V
Output Low
Leakage
Current
– 3
LOL
All output pins
18-5
KS57P5616 OTP
KS57C5616/P5616
Table 18-5. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Units
R
LI
V = 0 V; V
= 5 V, Port 0–10
Pull-Up
25
47
100
kW
I
DD
Resistor
V
= 3 V
50
100
200
40
95
220
450
55
200
400
800
70
DD
R
L2
V = 0 V; V
I
= 5 V, RESET
–
DD
V
DD
= 3 V
R
LCD1
LCD Voltage
Dividing
kW
Resistor (Note)
R
20
–
28
–
35
LCD2
V
V
V
DD
= 2.7 V to 5.5 V
120
mV
| DD-COMi|
DC
– 15 µA per common pin
Voltage Drop
(i = 0–15)
V
V
DS
V
= 2.7 V to 5.5 V
–
–
120
| DD-SEGx|
DD
– 15 µA per segment pin
Voltage Drop
(x = 0–59)
V
V
LC1
V
= 2.7 V to 5.5 V
V
DD
–0.2
V
DD
V
DD
+0.2
V
LCX Output
DD
LCD clock = 0 Hz
Voltage
V
LC2
V
LC3
V
LC4
V
LC5
0.8V –0.2 0.8V
DD
0.8V +0.2
DD
DD
DD
DD
DD
0.6V –0.2 0.6V
DD
0.6V +0.2
DD
0.4V –0.2 0.4V
DD
0.4V +0.2
DD
0.2V –0.2 0.2V
DD
0.2V +0.2
DD
NOTE:
R
is the LCD Voltage dividing resistor when LCON.1 = “0”, and R is the one when LCON.1 = “1”.
LCD2
LCD1
18-6
KS57C5616/P5616
KS57P5616 OTP
Table 18-5. D.C. Electrical Characteristics (Concluded)
= 1.8 V to 5.5 V)
°
°
(T = – 40 C to + 85 C, V
A
DD
Parameter
Supply
Symbol
Conditions
= 5 V ± 10%
Min
Typ
Max
Units
I
Run mode; V
DD
–
3.9
7.0
mA
DD1
(1)
Current
3.58 MHz X-tal oscillator, C1 = C2 = 22pF
(DTMF on)
VDD = 3 V ± 10%
–
2.0
4.0
I
Run mode;
= 5 V ± 10%
6.0 MHz
3.58 MHz
4.1
2.7
8.0
5.0
DD2
V
(DTMF off)
DD
Crystal oscillator
C1 = C2 = 22pF
V
= 3 V ± 10%
6.0 MHz
3.58 MHz
1.9
1.2
4.0
2.3
DD
I
Idle mode;
= 5 V ± 10%
6.0 MHz
3.58 MHz
–
1.2
0.9
2.5
1.8
DD3
V
DD
Crystal oscillator
C1 = C2 = 22pF
V
= 3 V ± 10%
6.0 MHz
3.58 MHz
0.5
0.4
1.5
1.0
DD
(2)
Run mode; V
DD
= 3 V ± 10%
–
–
–
17.5
45
mA
mA
mA
I
I
DD4
32 kHz Crystal oscillator
Idle mode; V = 3 V ± 10%
(2)
4.8
15
DD
DD5
I
32 kHz Crystal oscillator
Stop mode;
SCMOD = 0000
2.0
0.6
5
3
DD6
XT = 0 V
V
V
= 5 V ± 10%
= 3 V ± 10%
DD
DD
IN
Stop mode;
SCMOD = 0100
0.2
0.1
3
2
V
= 5 V ± 10%
DD
DD
V
= 3 V ± 10%
V
V
= 2 to 5.5 V
Row Tone level
– 16.0
– 14.0
– 11.0
dBV
%
DD
ROW
RL = 12 KW; Temp = – 30 to 60 °C
= 2 to 5.5 V
V
Ratio of Column
to Row tone
dBCR
THD
1
–
2
–
3
5
DD
RL = 12 KW; Temp = – 30 to 60 °C
= 2 to 5.5 V
V
Distortion
(Dual tone)
DD
1 MHz band
RL = 12 KW; Temp = – 30 to 60 °C
NOTES:
1. Data includes power consumption for subsystem clock oscillation.
2. When the system clock control register, SCMOD, is set to 1001B, the main system clock oscillation stops and the
subsystem clock is used.
3. Currents in the following circuits are not included: on-chip pull-up resistors, internal LCD voltage dividing resistors, and
output port drive currents.
18-7
KS57P5616 OTP
KS57C5616/P5616
Table 18-6. Main System Oscillator Characteristics
(TA = – 40 °C + 85 C, VDD = 1.8 V to 5.5 V)
°
Oscillator
Clock
Parameter
Test Condition
Min
Typ Max Units
Configuration
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Ceramic
0.4
–
6.0
MHz
XIN
XOUT
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
0.4
–
–
–
3.0
4
Stabilization time (2)
Stabilization occurs
when VDD is equal to
ms
the minimum
oscillator voltage
range; VDD = 3.0 V
Oscillation frequency (1)
VDD = 2.7 V to 5.5 V
Crystal
0.4
–
6.0
MHz
XIN
XOUT
Oscillator
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
–
3.0
10
Stabilization time (2)
ms
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
–
30
XIN input frequency (1)
External
Clock
0.4
6.0
MHz
XIN
XOUT
VDD = 1.8 V to 5.5 V
–
0.4
–
–
3.0
XIN input high and low
83.3
1,250
ns
level width (tXH, tXL
)
RC
Oscillator
Frequency
–
–
2
–
–
MHz
R = 25 kW, VDD = 5 V
XIN
XOUT
R
1
R = 40 kW, VDD = 3 V
NOTES:
1. Oscillation frequency and XIN input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
18-8
KS57C5616/P5616
KS57P5616 OTP
Table 18-7. Subsystem Clock Oscillator Characteristics
°
°
(T = – 40 C + 85 C, V
= 1.8 V to 5.5 V)
A
DD
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
Oscillation frequency (1)
V
DD
= 1.8 V to 5.5 V
Crystal
32
32.768
35
kHz
XTIN XTOUT
Oscillator
C1
C2
Stabilization time (2)
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V
= 1.8 V to 5.5 V
= 1.8 V to 5.5 V
–
–
1.0
–
2
s
10
External
Clock
32
–
100
kHz
XTIN XTOUT
Open
XT input frequency (1)
IN
XT input high and low
IN
–
5
–
15
µs
level width (t )
, t
XTL XTH
NOTES:
1. Oscillation frequency and XT input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
Table 18-8. Input/Output Capacitance
°
(T = 25 C, V
= 0 V )
A
DD
Parameter
Input
Capacitance
Symbol
Condition
Min
Typ
Max
Units
C
IN
f = 1 MHz; Unmeasured pins
–
–
15
15
15
pF
pF
pF
are returned to V
SS
C
OUT
Output
Capacitance
–
–
–
–
C
IO
I/O Capacitance
18-9
KS57P5616 OTP
KS57C5616/P5616
Main Os. Freq. (Divided by 4)
6MHz
CPU Clock
1.5MHz
4.2MHz
3MHz
1.05MHz
0.75kHz
15.625kHz
1
2
3
4
5
6
7
1.8
2.7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n =4, 8 or 64)
Figure 18-2. Standard Operating Voltage Range
18-10
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