KS57P5308S [SAMSUNG]
Microcontroller, 4-Bit, OTPROM, 6MHz, CMOS, PDSO32, 0.450 INCH, SOP-32;
| 型号： | KS57P5308S |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 4-Bit, OTPROM, 6MHz, CMOS, PDSO32, 0.450 INCH, SOP-32 可编程只读存储器 微控制器 光电二极管 |
| 文件： | 总40页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
OVERVIEW
The KS57C5204/C5208/C5304/C5308/C5312 single-chip CMOS microcontroller has been designed for high-
performance using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core
is notable for its low energy consumption and low operating voltage.
You can select from three ROM sizes: 4K, 8K, or 12K bytes.
Except for the difference in ROM size, the features and functions of the KS57C5204 and the KS57C5208 are
identical and the KS57C5304, KS57C5308, and the KS57C5312 are identical.
With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, the KS57C5204/C5208
/C5304/C5308/C5312 offers an excellent design solution for a wide variety of telecommunication applications.
Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the KS57C5204/C5208, and up to 23 pins
of the available 30-pin SDIP or 32-pin SOP package for the KS57C5304/C5308/C5312 can be assign to I/O. Six
vectored interrupts for KS57C5204/C5208 and four vectored interrupts for KS57C5304/C5308/C5312 provide fast
response to internal and external events. In addition, the KS57C5204/C5208/C5304/C5308/C5312's advanced
CMOS technology provides for low power consumption and a wide operating voltage range.
OTP
The KS57C5204/C5208 microcontroller is also available in OTP (One Time Programmable) version, KS57P5208.
The KS57C5304/C5308/C5312 microcontroller is also available in OTP (One Time Programmable) version,
KS57P5308/P5312. The KS57P5208/P5308/P5312 microcontroller has an on-chip 8K-byte (P5208/P5308) or
12K-byte (P5312) one-time-programable EPROM instead of masked ROM. The KS57P5208 is comparable to
KS57C5204/C5208, both in function and in pin configuration. Also, the KS57P5308/P5312 is comparable to the
KS57C5304/C5308/C5312, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
FEATURES
Memory
format
·
768 ´ 4-bit RAM
Interrupts
4,096 ´ 8-bit ROM (KS57C5204/C5304)
8,192 ´ 8-bit ROM (KS57C5208/C5308)
12,288 ´ 8-bit ROM (KS57C5312)
·
3 external interrupt vectors (KS57C5204/C5208)
1 external interrupt vectors
(KS57C5304/C5308/C5312)
I/O Pins
·
·
3 internal interrupt vectors
2 quasi-interrupts
·
·
·
Input only: 4 pins (KS57C5204/C5208)
1 pins (KS57C5304/C5308/C5312)
I/O: 35 pins (KS57C5204/C5208)
Power-Down Modes
23 pins (KS57C5304/C5308/C5312)
·
·
Idle: Only CPU clock stops
Stop: System clock stops
N-channel open-drain I/O: 8 pins
Memory-Mapped I/O Structure
Data memory bank 15
Oscillation Sources
·
·
·
Crystal, or ceramic for main system clock
Main system clock frequency: 0.4–6.0 MHz
(typical)
DTMF Generator
16 dual-tone frequencies for tone dialing
·
·
CPU clock divider circuit (by 4, 8, or 64)
8-Bit Basic Timer
Instruction Execution Times
·
·
Programmable interval timer
Watchdog timer
·
·
·
0.95, 1.91, and 15.3 ms at 4.19 MHz
1.12, 2.23, 17.88 ms at 3.58 MHz
0.67, 1.33, 10.7 ms at 6.0 MHz
Two 8-Bit Timer/Counters
·
·
·
Programmable 8-bit timer
Operating Temperature
External event counter function
Arbitrary clock frequency output
°
– 40 C to 85 °C
·
Operating Voltage Range
1.8 V to 5.5 V
Watch Timer
·
·
·
Real-time and time interval generation
Four frequency outputs to the BUZ pin
Package Types
·
·
42 SDIP, 44 QFP (KS57C5204/C5208)
Bit Sequential Carrier
30 SDIP, 32 SOP (KS57C5304/C5308/C5312)
·
Supports 16-bit serial data transfer in arbitrary
1-2
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
BLOCK DIAGRAM
INT0, INT1, INT2, INT4
RESET
XIN
XOUT
8-Bit
Timer/
Watchdog
Timer
Counter 0
Interrupt
Control
Block
Basic
Timer
Stack
Pointer
Clock
8-Bit
Timer/
Counter 1
Watch
Timer
Program
Counter
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
Internal
Interrupts
P6.0-P6.3/
KS0-KS3
Input
Port 1
I/O Port 6
I/O Port 7
P7.0-P7.3/
KS4-KS7
Program
Status Word
Instruction Decoder
P2.0/TCLO0
P2.1/TCLO1
P2.2/CLO
I/O Port 8
I/O Port 9
P8.0 - P8.3
P9.0 - P9.2
Arithmetic
and
Logic Unit
I/O Port 2
I/O Port 3
P2.3/BUZ
P3.0/TCL0
P3.1/TCL1
P3.2
Flags
P3.3
P4.0/BTCO
P4.1-4.3
I/O Port 4
I/O Port 5
Program Memory
P5.0-P5.3
768x4-Bit
Data
Memory
KS57C5204/C5304: 4KBytes
KS57C5208/C5308: 8KBytes
KS57C5312: 12KBytes
DTMF
Generator
DTMF
NOTE: KS57C5304/C5308/C5312 does not use P1.1/INT1, P1.2/INT2, P1.3/INT4, P3.2, P3.3, INT1, INT2,
INT4, P8.0-P8.3, and P9.0-P9.2.
Figure 1-1. KS57C5204/C5208/C5304/C5308/C5312 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
PIN ASSIGNMENTS
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/TCLO0
P2.1/TCLO1
P2.2/CLO
P2.3/BUZ
P3.0/TCL0
P3.1/TCL1
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P9.2
P9.1
P9.0
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
9
10
11
12
13
14
15
16
17
18
19
20
21
V
DD
V
SS
XOUT
XIN
TEST
P4.0/BTCO
P4.1
RESET
P3.2
P3.3
P4.2
Figure 1-2. KS57C5204/C5208 Pin Assignment Diagram (42-SDIP)
1-4
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
DTMF
P9.0
P9.1
P9.2
NC
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
NC
P4.2
P3.3
P3.2
RESET
KS57C5204
/C5208
(44-QFP-1010B)
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/TCLO0
P2.1/TCLO1
Figure 1-3. KS57C5204/C5208 Pin Assignment Diagram (44-QFP)
1-5
PRODUCT OVERVIEW
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
V
X
X
SS
OUT
IN
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD
P3.1/TCL1
P3.0/TCL0
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P1.0/INT0
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
TEST
P4.0/BTCO
P4.1
RESET
P4.2
P4.3
P5.0
P5.1
P5.2
9
10
11
12
13
14
15
P5.3
P6.0/KS0
P6.1/KS1
Figure 1-4. KS57C5304/C5308/C5312 Pin Assignment Diagram (30-SDIP)
V
X
X
SS
OUT
IN
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
P3.1/TCL1
P3.0/TCL0
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P1.0/INT0
NC
TEST
P4.0/BTCO
P4.1
RESET
P4.2
NC
P4.3
P5.0
P5.1
P5.2
P5.3
9
10
11
12
13
14
15
16
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.0/KS0
P6.1/KS1
Figure 1-5. KS57C5304/C5308/C5312 Pin Assignment Diagram (32-SOP)
1-6
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. KS57C5204/C5208 Pin Descriptions
Pin
Pin Reset
Description
Pin
Share Circuit
Name Type Value
Number
Pin
Type
P1.0
P1.1
P1.2
P1.3
I
I
4-bit input port.
1-bit and 4-bit read and test is possible.
Each pull-up resistors are assignable by software.
1 (39)
2 (40)
3 (41)
4 (42)
INT0
INT1
INT2
INT4
A-4
P2.0
P2.1
P2.2
P2.3
I/O
I
4-bit I/O port.
5 (43)
6 (44)
7 (1)
TCLO0
TCLO1
CLO
D-2
D-4
E-2
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
8 (2)
BUZ
P3.0
P3.1
P3.2
P3.3
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 2 and 3 can be paired to enable 8-bit data
transfer.
9 (3)
10 (4)
19 (13)
20 (14)
TCL0
TCL1
P4.0
P4.1
P4.2
P4.3
I/O
I
4-bit I/O ports.
16 (10)
17 (11)
21 (15)
22 (17)
BTCO
1-bit and 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
N-channel open-drain or push-pull output can be
selected by software (1-bit unit)
P5.0-P5.3
27-30
(22-25)
Ports 4 and 5 can be paired to support 8-bit data
transfer.
P6.0-P6.3 I/O
P7.0-P7.3
I
4-bit I/O ports.
31-34
(26-29)
35-38
KS0-KS3
KS4-KS7
D-4
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
(30-33)
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
23-26
(18-21)
40-42
P8.0-P8.3 I/O
P9.0-P9.2
I
4-bit I/O port.
–
D-2
1-bit or 4-bit read/write and test is possible.
Individual pins are software configurable as input or
output.
(35-37)
4-bit pull-up resistors are software assignable to input
pins and are automatically disabled for output pins.
Ports 8 and 9 can be paired to enable 8-bit data
transfer.
1-7
PRODUCT OVERVIEW
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 1-1. KS57C5204/C5208 Pin Descriptions (Continued)
Pin Name Pin Reset
Type Value
Description
Pin
Number
Share
Pin
Circu
it
Type
DTMF
BTCO
O
I/O
I
–
I
DTMF output.
39 (34)
16 (10)
–
G-6
E-2
A-4
Basic timer clock output
P4.0
INT0
INT1
I
External interrupts. The triggering edge for INT0 and
INT1 is selectable.
1 (39)
2 (40)
P1.0
P1.1
INT2
INT4
I
I
I
I
Quasi-interrupt with detection of rising edges
3 (41)
4 (42)
P1.2
P1.3
A-4
A-4
External interrupt with detection of rising and falling
edges.
TCLO0
TCLO1
CLO
I/O
I/O
I/O
I/O
I
I
I
I
Timer/counter 0 clock output
Timer/counter 1 clock output
Clock output
5 (43)
6 (44)
7 (1)
P2.0
P2.1
P2.2
P2.3
D-2
D-2
D-2
D-2
BUZ
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the
watch timer clock frequency of 4.19 MHz for buzzer
sound
8 (2)
TCL0
I/O
I/O
I/O
I
I
I
External clock input for timer/counter 0
External clock input for timer/counter 1
Quasi-interrupt inputs with falling edge detection
9 (3)
10 (4)
31-34
P3.0
P3.1
D-4
D-4
TCL1
KS0-KS3
P6.0-P6.3 D-4
(26-29) P7.0-P7.3
35-38
KS4-KS7
(30-33)
VDD
–
–
–
–
Power supply
Ground
11 (5)
12 (6)
–
–
–
–
VSS
–
–
–
–
RESET signal
18 (12)
–
–
B
–
RESET
XIN
XOUT
Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use XIN and input XIN's
14 (8)
13 (7)
reverse phase to XOUT
)
TEST
NC
–
–
–
–
Chip test input pin, Hold GND when the device is
operating.
15 (9)
–
–
–
–
No connection
(16, 38)
NOTE: Parentheses indicate pin number for 44 QFP package.
1-8
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions
Pin
Name
Pin
Type
Description
Pin
Number
Share
Pin
Circuit
Type
P1.0
I
1-bit input port.
23 (25)
INT0
A-4
1-bit and 4-bit read and test is possible.
Each bit pull-up resistors are assignable.
P2.0
P2.1
P2.2
P2.3
I/O
4-bit I/O port.
24 (26)
25 (27)
26 (28)
27 (29)
TCLO0
TCLO1
CLO
D-2
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software assignable to
input pins and are automatically disabled for output
pins.
BUZ
Ports 2 and 3 can be paired to enable 8-bit data
transfer.
P3.0
P3.1
28 (30)
29 (31)
TCL0
TCL1
D-4
E-2
P4.0
P4.1
P4.2
P4.3
I/O
4-bit I/O ports.
5 (5)
6 (6)
8 (8)
9 (10)
10-13
(11-14)
BTCO
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software assignable to
input pins and are automatically disabled for output
pins.
P5.0-P5.3
The N-channel open-drain or push-pull output can be
selected by software (1-bit unit).
Ports 4 and 5 can be paired to enable 8-bit data
transfer.
P6.0-P6.3
P7.0-P7.3
I/O
4-bit I/O ports.
14-17
(15-18)
18-21
KS0-KS3
KS4-KS7
D-4
1-bit and 4-bit read/write and test is possible.
Each individual pin can be assignable as input or
output. 4-bit pull-up resisters are software assignable to
input pins and are automatically disabled for output
pins.
(19-22)
Ports 6 and 7 can be paired to enable 8-bit data
transfer.
1-9
PRODUCT OVERVIEW
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 1-2. KS57C5304/C5308/C5312 Pin Descriptions (Continued)
Pin Name
I/O
Type
Description
Pin
Number
Share
Pin
Circuit
Type
DTMF
INT0
O
I
DTMF output.
22 (23)
23 (25)
–
G-6
A-3
External interrupt input.
P1.0
The triggering edge for INT0 is selectable.
TCLO0
TCLO1
CLO
I/O
I/O
I/O
I/O
Timer/counter 0 clock output
Timer/counter 1 clock output
Clock output
24 (26)
25 (27)
26 (28)
27 (29)
P2.0
P2.1
P2.2
P2.3
D-2
D-2
D-2
D-2
BUZ
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the
watch timer clock frequency of 4.19 MHz for buzzer
sound
TCL0
TCL1
BTCO
VDD
I/O
I/O
I/O
–
External clock input for timer/counter 0
External clock input for timer/counter 1
Basic timer clock output
28 (30)
29 (31)
5 (5)
P3.0
P3.1
P4.0
–
D-4
D-4
E-2
–
Power supply
30 (32)
VSS
–
–
Ground
1 (1)
–
–
–
–
XIN
XOUT
Crystal, or ceramic oscillator signal for main system
clock. (For external clock input, use XIN and input XIN's
3 (3)
2 (2)
reverse phase to XOUT
)
NC
–
–
No connection
(9, 24)
4 (4)
–
–
–
–
TEST
Chip test input pin, Hold GND when the device is
operating.
–
RESET signal
7 (7)
–
B
RESET
KS0-KS3
I/O
Quasi-interrupt inputs with falling edge detection
14-17
(15-18)
18-21
P6.0-P6.3
P7.0-P7.3
D-4
KS4-KS7
(19-22)
NOTE: Parentheses indicate the pin number for 32-SOP package.
1-10
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD
VDD
Pull-Up
Resistor
P-Channel
N-Channel
In
In
Schmitt Trigger
Figure 1-8. Pin Circuit Type B
Figure 1-6. Pin Circuit Type A
VDD
VDD
Pull-Up
Resistor
P-Channel
Out
Resistor
Enable
Data
P-Channel
In
N-Channel
Output
DIsable
Schmitt Trigger
Figure 1-9. Pin Circuit Type C
Figure 1-7. Pin Circuit Type A-4
1-11
PRODUCT OVERVIEW
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
VDD
VDD
Pull-up
Resistor
Pull-up
Resistor
PNE
VDD
Pull-up
Enable
P-Channel
Pull-up
Resistor
Enable
Data
P-Channel
Data
Circuit
Type C
I/O
I/O
Output
DIsable
Output
Disable
N-Channel
Figure 1-10. Pin Circuit Type D-2
Figure 1-12. Pin Circuit Type E-2
VDD
Pull-up
Resistor
Pull-up
Enable
P-Channel
Data
DTMF Out
Circuit
Type C
I/O
Output
Disable
Output
Disable
Schmitt Trigger
Figure 1-11. Pin Circuit Type D-4
Figure 1-13. Pin Circuit Type G-6
1-12
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
ELECTRICAL DATA
13 ELECTRICAL DATA
OVERVIEW
In this section, information on KS57C5204/C5208/C5304/C5308/C5312 electrical characteristics is presented as
tables and graphics. The information is arranged in the following order:
Standard Electrical Characteristics
— Absolute maximum ratings
— D.C. electrical characteristics
— System clock oscillator characteristics
— I/O capacitance
— A.C. electrical characteristics
— Operating voltage range
Miscellaneous Timing Waveforms
— A.C timing measurement point
— Clock timing measurement at XIN and XOUT
— TCL timing
— Input timing for RESET
— Input timing for external interrupts
Stop Mode Characteristics and Timing Waveforms
— RAM data retention supply voltage in stop mode
— Stop mode release timing when initiated by RESET
— Stop mode release timing when initiated by an interrupt request
13-1
ELECTRICAL DATA
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 13-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
VDD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
V
VI1
VO
All I/O ports
V
V
– 0.3 to VDD + 0.3
– 15
Output Voltage
Output Current High
–
IOH
One I/O port active
mA
All I/O ports active
One I/O port active
– 35
IOL
Output Current Low
+ 30 (Peak value)
mA
+ 15 (note)
All I/O ports active
+ 100 (Peak value)
+ 60 (note)
°
TA
Operating Temperature
Storage Temperature
–
– 40 to + 85
C
°
C
Tstg
–
– 65 to + 150
NOTE: The values for output current low ( IOL ) are calculated as peak value ´
Duty .
Table 13-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those specified
below for VIH2 – VIH3
–
V
VIH2
VIH3
VIL1
0.8 VDD
VDD
VDD
Ports 1, 3, 6, 7, and RESET
XIN and XOUT
V
DD – 0.1
0.3 VDD
Input low
voltage
All input pins except those specified
below for VIL2–VIL3
–
–
V
VIL2
VIL3
0.2 VDD
0.1
Ports 1, 3, 6, 7, and RESET
XIN and XOUT
13-2
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VOH
IOH = – 1 mA
Ports except 1
VDD – 1.0
Output high
voltage
–
–
V
VOL1
VDD = 4.5 V to 5.5 V
IOL = 15 mA, Ports 4 and 5 only
Output low
voltage
–
–
2
V
V
VDD = 1.8 to 5.5 V, IOL = 1.6mA
–
–
–
–
0.4
2
VOL2
VDD = 4.5 V to 5.5 V
IOL= 4 mA, all out ports except 4,5
VDD = 1.8 to 5.5 V, IOL = 1.6mA
V = V
–
–
–
–
0.4
3
ILIH1
Input high
µA
I
DD
leakage current
All input pins except those specified
below
ILIH2
VI = VDD
20
XIN and XOUT
ILIL1
ILIL2
VI = 0 V
Input low
leakage current
–
–
– 3
µA
All input pins except below and RESET
VI = 0 V
– 20
XIN and XOUT only
ILOH
ILOL
RL1
VO = VDD
Output high
leakage current
–
–
–
–
3
µA
µA
kW
All out pins
VO = 0 V
Output low
leakage current
– 3
100
200
All out pins
VDD = 5 V; VI = 0 V
except RESET
VDD = 3 V
Pull-up resistor
25
50
47
95
RL2
VDD = 5 V; V = 0 V; RESET
I
100
200
220
450
400
800
VDD = 3 V
13-3
ELECTRICAL DATA
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 13-2. D.C. Electrical Characteristics (Concluded)
°
°
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
Parameter
Supply
Symbol
Conditions
Min
Typ
Max Units
Run mode; VDD = 5 V ± 10% (2)
IDD1
–
2.5
5.0
mA
(1)
current
(DTMF on)
3.58 MHz crystal oscillator,
C1 = C2 = 22 pF
V
DD = 3 V ± 10%
1.4
2.5
1.6
3.0
8.0
4.0
IDD2
6.0 MHz
–
–
–
mA
Run mode; VDD = 5 V ± 10%
crystal oscillator, C1 = C2 = 22 pF
VDD = 3 V ± 10%
3.58 MHz
(DTMF off)
6.0 MHz
1.2
0.7
4.0
2.3
3.58 MHz
IDD3
6.0 MHz
0.7
0.6
2.5
1.8
mA
µA
Idle mode; = VDD = 5 V ± 10%
crystal oscillator, C1 = C2 = 22 pF
VDD = 3 V ± 10%
3.58 MHz
6.0 MHz
0.3
0.2
1.5
1.0
3.58 MHz
IDD4
Stop mode; VDD = 5 V ± 10%
Stop mode; VDD = 3 V ± 10%
VDD = 2.0 V to 5.5 V
0.01
0.01
3
2
VROW
dBCR
Row tone level
– 16.0 – 14.0 – 11.0 dBV
RL = 12 kW, Temp = – 30 °C to 60 °C
VDD = 2.0 V to 5.5 V
Ratio of
column to row
tone
1
–
2
–
3
5
dB
%
RL = 12 kW, Temp = – 30 °C to 60 °C
VDD = 2.0 V to 5.5 V
Distortion
THD
(Dual tone)
1MHz band; RL= 12 kW
Temp = – 30 °C to 60 °C
NOTES:
1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers.
2. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
13-4
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
ELECTRICAL DATA
Table 13-3. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 C, VDD = 1.8 V to 5.5 V)
°
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
(1)
(1)
(1)
VDD = 2.7 V to 5.5 V
Ceramic
Oscillator
0.4
–
6.0
MHz
Oscillation frequency
IN
OUT
X
X
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
3
4
(2)
ms
Stabilization time
VDD = 2.7 V to 5.5 V
Crystal
Oscillator
0.4
6.0
MHz
Oscillation frequency
XIN
XOUT
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
3
(2)
10
6.0
ms
Stabilization time
VDD = 2.7 V to 5.5 V
External
Clock
0.4
MHz
XIN input frequency
X
IN
XOUT
VDD = 1.8 V to 5.5 V
–
0.4
–
–
3
XIN input high and low
level width (tXH, tXL
83.3
1250
ns
)
NOTES:
1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only.
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
13-5
ELECTRICAL DATA
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 13-4. Recommended Oscillator Constants
°
°
(T = – 40 C to + 85 C)
A
Manufacturer
Series
Number (1)
Frequency Range
Load Cap (pF)
Oscillator Voltage
Range (V)
Remarks
C1
33
(2)
C2
33
(2)
MIN
2.0
MAX
5.5
TDK
3.58 MHz-6.0 MHz
3.58 MHz-6.0 MHz
Leaded Type
FCR” ðÿM5
2.0
5.5
On-chip C
FCR” ðÿMC5
Leaded Type
(3)
(3)
3.58 MHz-6.0 MHz
2.0
5.5
On-chip C
SMD Type
CCR” ðÿMC3
NOTES:
1. Please specify normal oscillator frequency.
2. On-chip C: 30pF built in.
3. On-chip C: 38pF built in.
Table 13-5. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Symbol
Condition
Min
Typ
Max
Units
CIN
COUT
CIO
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
–
–
15
15
15
pF
Capacitance
Output
Capacitance
–
–
pF
pF
I/O Capacitance
13-6
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
ELECTRICAL DATA
Table 13-6. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 C, VDD = 1.8 V to 5.5 V)
°
Parameter
Symbol
tCY
Conditions
Min
Typ
Max
Units
V
DD = 2.7 V to 5.5 V
Instruction Cycle
Time
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
1.33
0
fTI0
f
TI1
TCL0, TCL1 Input
Frequency
–
–
1.5
MHz
,
VDD = 1.8 V to 5.5V
VDD = 2.7 V to 5.5 V
1
–
MHz
µs
tTIH0, tTIL0
tTIH1, tTIL1
TCL0, TCL1 Input
High, Low Width
0.48
VDD = 1.8 V to 5.5 V
1.8
10
tINTH, tINTL
tRSL
Interrupt Input
High, Low Width
INT0, INT1, INT2, INT4,
KS0-KS7
–
–
–
–
µs
µs
RESET Input Low
Width
Input
10
13-7
ELECTRICAL DATA
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Main Oscillator Frequency
(Divided by 4)
CPU Clock
1.5 MHz
6 MHz
0.75 MHz
3 MHz
15.625 kHz
1
2
3
4
5
6
7
1.8
2.7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 13-1. Standard Operating Voltage Range
Table 13-7. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
VDDDR
IDDDR
tSREL
Conditions
Min
1.8
–
Typ
–
Max
5.5
10
–
Unit
V
Data retention supply voltage
Data retention supply current
Release signal set time
–
VDDDR = 1.8 V
0.1
–
µA
µs
–
0
217/fx
tWAIT
Oscillator stabilization wait
Released by RESET
–
–
ms
time (1)
(2)
Released by interrupt
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
13-8
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
ELECTRICAL DATA
TIMING WAVEFORMS
Internal RESET
Operation
Idle Mode
Stop Mode
Operating Mode
Data Retention Mode
VDD
VDDDR
Execution of
STOP Instruction
RESET
t
WAIT
t
SREL
Figure 13-2. Stop Mode Release Timing When Initiated by RESET
Idle Mode
Normal
Operating
Mode
Stop Mode
Data Retention
VDD
VDDDR
t
SREL
Execution of
STOP Instruction
t
WAIT
Power-down Mode Terminating Signal
(Interrupt Request)
Figure 13-3. Stop Mode Release Timing When Initiated by Interrupt Request
13-9
ELECTRICAL DATA
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Timing Waveforms (continued)
0.8 V
0.2 V
0.8 V
DD
DD
Measurement
Points
0.2 V
DD
DD
Figure 13-4. A.C. Timing Measurement Points (Except for XIN)
1/fx
XL
XH
t
t
IN
X
DD
V
- 0.1 V
0.1 V
Figure 13-5. Clock Timing Measurement at XIN
1/fTI
t
TIL
tTIH
TCL
0.8 VDD
0.2 VDD
Figure 13-6. TCL Timing
13-10
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
ELECTRICAL DATA
t
RSL
RESET
0.2 V
DD
Figure 13-7. Input Timing for RESET Signal
t
INTL
tINTH
INT0, 1, 2, 4,
KS0 to KS7
0.8 VDD
0.2 V
DD
Figure 13-8. Input Timing for External Interrupts and Quasi-Interrupts
13-11
ELECTRICAL DATA
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
NOTES
13-12
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312MECHANICAL DATA
14 MECHANICAL DATA
OVERVIEW
The KS57C5204/C5208 microcontroller are available in a 42-pin SDIP package (42-SDIP-600), and a 44-pin QFP
package (44-QFP-1010B). The KS57C5304/C5308/C5312 microcontrollers are available in a 30-pin SDIP
package (30-SDIP-400) and a 32-pin SOP package (32-SOP-450A).
#42
#22
0-15
42-SDIP-600
#1
#21
39.50 MAX
39.10 ± 0.2
0.50 ± 0.1
1.00 ± 0.1
1.778
(1.77)
NOTE : Dimensions are in millimeters.
Figure 14-1. 42-SDIP-600 Package Dimensions
14-1
MECHANICAL DATA
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
13.20 ± 0.3
0-8
10.00
± 0.2
+ 0.10
0.15 - 0.05
0.10 MAX
44-QFP-1010B
#44
+ 0.10
- 0.05
#1
0.80
0.35
0.05 MIN
2.05 ± 0.10
2.30 MAX
(1.00)
NOTE : Dimensions are in millimeters.
Figure 14-2. 44-QFP-1010B Package Dimensions
14-2
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312MECHANICAL DATA
#30
#16
0-15
30-SDIP-400
#1
#15
27.88 MAX
27.48 ± 0.2
0.56 ± 0.1
1.12 ± 0.1
1.778
(1.77)
NOTE : Dimensions are in millimeters.
Figure 14-3. 30-SDIP-400 Package Dimensions
14-3
MECHANICAL DATA
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
#32
#17
32-SOP-450A
#1
#16
+ 0.1
0.20
- 0.05
19.90 ± 0.2
1.27
(0.43)
0.40 ± 0.1
NOTE: Dimensions are in millimeters
Figure 14-4. 32-SOP-450A Package Dimensions
14-4
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
KS57P5208/P5308/P5312 OTP
15 KS57P5208/P5308/P5312 OTP
OVERVIEW
The KS57P5208/P5308/P5312 single-chip CMOS microcontroller is the OTP (One Time Programmable) version
of the KS57C5204/C5208/C5304/C5308/C5312 microcontroller. It has an on-chip EPROM instead of masked
ROM. The EPROM is accessed by a serial data format.
The KS57P5208/P5308/P5312 is fully compatible with the KS57C5208/C5308/C5312, both in function and in pin
configuration. Because of its simple programming requirements, the KS57P5208/P5308/P5312 is ideal for use as
an evaluation chip for the KS57C5208/C5308/C5312.
P1.0/INT0
P1.1/INT1
P1.2/INT2
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P9.2
P9.1
P9.0
P1.3/INT4
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.1/KS1
P6.0/KS0
P5.3
P5.2
P5.1
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
P2.0/TCLO0
P2.1/TCLO1
P2.2/CLO
P2.3/BUZ
SDAT /P3.0/TCL0
SCLK /P3.1/TCL1
DD DD
9
10
11
12
13
14
15
16
17
18
19
20
21
V
/V
SS SS
/V
V
OUT
X
XIN
V
PP/TEST
P4.0/BTCO
P4.1
RESET
/
RESET
P3.2
P3.3
P4.2
Figure 15-1. KS57P5208 Pin Assignment Diagram (42-SDIP)
15-1
KS57P5208/P5308/P5312 OTP
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
DTMF
P9.0
P9.1
P9.2
NC
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P5.0
P8.3
P8.2
P8.1
P8.0
P4.3
NC
P4.2
KS57P5208
(44-QFP-1010B)
P1.0/INT0
P1.1/INT1
P1.2/INT2
P1.3/INT4
P2.0/TCLO0
P2.1/TCLO1
P3.3
P3.2
RESET/RESET
Figure 15-2. KS57P5208 Pin Assignment Diagram (44-QFP)
15-2
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
KS57P5208/P5308/P5312 OTP
V
SS/VSS
OUT
IN
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VDD/VDD
X
P3.1/TCL1/SCLK
P3.0/TCL0/SDAT
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P1.0/INT0
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
X
V
PP/TEST
P4.0/BTCO
P4.1
RESET/RESET
P4.2
P4.3
P5.0
P5.1
P5.2
P5.3
9
10
11
12
13
14
15
P6.0/KS0
P6.1/KS1
P6.3/KS3
P6.2/KS2
Figure 15-3. KS57P5308/P5312 Pin Assignment Diagram (30-SDIP)
V
SS/VSS
OUT
IN
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD/VDD
X
P3.1/TCL1/SCLK
P3.0/TCL0/SDAT
P2.3/BUZ
P2.2/CLO
P2.1/TCLO1
P2.0/TCLO0
P1.0/INT0
NC
X
V
PP/TEST
P4.0/BTCO
P4.1
RESET/RESET
P4.2
NC
P4.3
P5.0
P5.1
P5.2
P5.3
9
10
11
12
13
14
15
16
DTMF
P7.3/KS7
P7.2/KS6
P7.1/KS5
P7.0/KS4
P6.3/KS3
P6.2/KS2
P6.0/KS0
P6.1/KS1
Figure 15-4. KS57P5308/P5312 Pin Assignment Diagram (32-SOP)
15-3
KS57P5208/P5308/P5312 OTP
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 15-1. KS57P5208 Pin Descriptions Used to Read/Write the EPROM
During Programming
I/O
Main Chip
Pin Name
Pin Name
SDAT
Pin No.
Function
P3.0
9 (3)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P3.1
SCLK
10 (4)
15 (9)
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option) Hold GND when OPT is operating.
18 (12)
I
I
Chip initialization
RESET
RESET
VDD / VSS
VDD / VSS
Logic power supply pin. VDD should be tied to +5
V during programming.
11/12
(5/6)
NOTE: Parentheses indicate pin numbers of 44 QFP package.
Table 15-2. KS57P5308/P5312 Pin Descriptions Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
Pin Name
SDAT
Pin No.
I/O
Function
P3.0
28 (30)
I/O
Serial data pin. Output port when reading and
input port when writing. Can be assigned as a
Input / push-pull output port.
P3.1
SCLK
29 (31)
4 (4)
I/O
I
Serial clock pin. Input only pin.
VPP (TEST)
TEST
Power supply pin for EPROM cell writing
(indicates that OTP enters into the writing mode).
When 12.5 V is applied, OTP is in writing mode
and when 5 V is applied, OTP is in reading mode.
(Option) Hold GND when OPT is operating.
7 (7)
I
I
Chip initialization
RESET
RESET
VDD / VSS
VDD / VSS
Logic power supply pin. VDD should be tied to +5
V during programming.
30/1
(32/1)
NOTE: Parentheses indicate pin numbers of 32 SDIP package.
15-4
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
KS57P5208/P5308/P5312 OTP
KS57C5208
Table 15-3. Comparison of KS57P5208 and KS57C5208 Features
Characteristic
Program Memory
Operating Voltage (VDD
KS57P5208
8 K byte EPROM
8 K byte mask ROM
)
1.8 V (3 MHz) to 5.5 V
1.8 V (3 MHz) to 5.5 V
–
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
Pin Configuration
42 SDIP / 44 QFP
42 SDIP / 44 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
Table 15-4. Comparison of KS57P5308/P5312 and KS57C5308/C5312 Features
Characteristic
KS57P5308/P5312
8 K byte EPROM / 12 K (P5312)
1.8 V (3 MHz) to 5.5 V
KS57C5308/C5312
Program Memory
8 K byte mask ROM / 12 K (C5312)
1.8 V (3 MHz) to 5.5 V
Operating Voltage (VDD
)
VDD = 5 V, VPP (TEST) = 12.5 V
OTP Programming Mode
–
Pin Configuration
30 SOP / 32 SOP
30 SOP / 32 SOP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the Vpp(TEST) pin of the KS57P5208/P5308/P5312, the EPROM programming mode
is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the
pins listed in Table 15-3 below.
Table 15-5. Operating Mode Selection Criteria
V
DD
Vpp
(TEST)
REG/
MEM
Address
(A15-A0)
R/W
Mode
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5V
12.5V
12.5V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
15-5
KS57P5208/P5308/P5312 OTP
OTP ELECTRICAL DATA
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 15-6. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Symbol
Conditions
Rating
Units
VDD
Supply Voltage
Input Voltage
–
– 0.3 to + 6.5
– 0.3 to VDD + 0.3
V
VI1
VO
All I/O ports
V
V
– 0.3 to VDD + 0.3
– 15
Output Voltage
Output Current High
–
IOH
One I/O port active
mA
All I/O ports active
One I/O port active
– 35
IOL
Output Current Low
+ 30 (Peak value)
mA
+ 15 (note)
All I/O ports active
+ 100 (Peak value)
+ 60 (note)
°
TA
Operating Temperature
Storage Temperature
–
– 40 to + 85
C
°
C
Tstg
–
– 65 to + 150
NOTE: The values for output current low ( IOL ) are calculated as peak value ´
Duty .
Table 15-7. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VIH1
0.7 VDD
VDD
Input high
voltage
All input pins except those
specified below for VIH2 – VIH3
–
V
VIH2
VIH3
VIL1
0.8 VDD
VDD
VDD
Ports 1, 3, 6, 7, and RESET
XIN and XOUT
V
DD – 0.1
0.3 VDD
Input low
voltage
All input pins except those
specified below for VIL2–VIL3
–
–
V
VIL2
VIL3
0.2 VDD
0.1
Ports 1, 3, 6, 7, and RESET
XIN and XOUT
15-6
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
KS57P5208/P5308/P5312 OTP
Table 15-7. D.C. Electrical Characteristics (Continued)
(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)
Parameter
Symbol
Conditions
IOH = – 1 mA
Ports except 1
DD = 4.5 V to 5.5 V
Min
Typ
Max
Units
VOH
VDD – 1.0
Output high
voltage
–
–
V
VOL1
V
Output low
voltage
–
–
2
V
V
IOL = 15 mA, Ports 4 and 5 only
VDD = 1.8 to 5.5 V, IOL = 1.6mA
–
–
–
–
0.4
2
VOL2
VDD = 4.5 V to 5.5 V
IOL= 4 mA, all out ports except 4,5
VDD = 1.8 to 5.5 V, IOL = 1.6mA
V = V
–
–
–
–
0.4
3
ILIH1
Input high
µA
I
DD
leakage current
All input pins except those specified
below
ILIH2
VI = VDD
20
XIN and XOUT
ILIL1
ILIL2
VI = 0 V
Input low
leakage current
–
–
– 3
µA
All input pins except below and RESET
VI = 0 V
– 20
XIN and XOUT only
ILOH
ILOL
RL1
VO = VDD
Output high
leakage current
–
–
–
–
3
µA
µA
kW
All out pins
VO = 0 V
Output low
leakage current
– 3
100
200
All out pins
VDD = 5 V; VI = 0 V
except RESET
VDD = 3 V
Pull-up resistor
25
50
47
95
RL2
VDD = 5 V; V = 0 V; RESET
I
100
200
220
450
400
800
VDD = 3 V
15-7
KS57P5208/P5308/P5312 OTP
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 15-7. D.C. Electrical Characteristics (Concluded)
(TA = – 40 C to + 85 C, VDD = 1.8 V to 5.5 V)
°
°
Parameter
Supply
Symbol
Conditions
Min
Typ
Max Units
Run mode; VDD = 5 V ± 10% (2)
IDD1
–
2.5
5.0
mA
(1)
current
(DTMF on)
3.58 MHz crystal oscillator,
C1 = C2 = 22 pF
V
DD = 3 V ± 10%
Run mode; VDD = 5 V ± 10%
crystal oscillator, C1 = C2 = 22 pF 3.58 MHz
1.4
2.5
1.6
3.0
8.0
4.0
IDD2
6.0 MHz
–
–
–
mA
(DTMF off)
VDD = 3 V ± 10%
6.0 MHz
1.2
0.7
4.0
2.3
3.58 MHz
IDD3
6.0 MHz
0.7
0.6
2.5
1.8
mA
µA
Idle mode; = VDD = 5 V ± 10%
crystal oscillator, C1 = C2 = 22 pF 3.58 MHz
VDD = 3 V ± 10%
6.0 MHz
0.3
0.2
1.5
1.0
3.58 MHz
IDD4
Stop mode; VDD = 5 V ± 10%
Stop mode; VDD = 3 V ± 10%
VDD = 2.0 V to 5.5 V
0.01
0.01
3
2
VROW
dBCR
THD
Row tone level
– 16.0 – 14.0 – 11.0 dBV
RL = 12 kW, Temp = – 30 °C to 60 °C
VDD = 2.0 V to 5.5 V
Ratio of column
to row tone
1
–
2
–
3
5
dB
%
RL = 12 kW, Temp = – 30 °C to 60 °C
VDD = 2.0 V to 5.5 V
Distortion
(Dual tone)
1MHz band; RL= 12 kW
Temp = – 30 °C to 60 °C
NOTES:
1. D.C. electrical values for Supply Current (IDD1 to IDD3) do not include current drawn through internal pull-up registers.
2. For D.C. electrical values, the power control register (PCON) must be set to 0011B.
15-8
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
KS57P5208/P5308/P5312 OTP
Table 15-8. Main System Clock Oscillator Characteristics
(TA = – 40 °C + 85 C, VDD = 1.8 V to 5.5 V)
°
Oscillator
Clock
Parameter
Test Condition
Min
Typ
Max Units
Configuration
(1)
VDD = 2.7 V to 5.5 V
Ceramic
Oscillator
0.4
–
6.0
MHz
Oscillation frequency
IN
X
OUT
X
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
3
4
(2)
ms
Stabilization time
(1)
VDD = 2.7 V to 5.5 V
Crystal
Oscillator
0.4
6.0
MHz
Oscillation frequency
XIN
XOUT
C1
C2
VDD = 1.8 V to 5.5 V
VDD = 3 V
0.4
–
–
–
–
3
(2)
10
6.0
ms
Stabilization time
(1)
VDD = 2.7 V to 5.5 V
External
Clock
0.4
MHz
XIN input frequency
IN
X
OUT
X
VDD = 1.8 V to 5.5 V
–
0.4
–
–
3
XIN input high and low
level width (tXH, tXL
83.3
1250
ns
)
NOTES:
1. Oscillation frequency and X input frequency data are for oscillator characteristics only.
IN
2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is
terminated.
15-9
KS57P5208/P5308/P5312 OTP
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
Table 15-9. Input/Output Capacitance
°
(TA = 25 C, VDD = 0 V )
Parameter
Input
Symbol
Condition
Min
Typ
Max
Units
CIN
COUT
CIO
f = 1 MHz; Unmeasured pins
are returned to VSS
–
–
15
pF
Capacitance
Output
Capacitance
–
–
–
–
15
15
pF
pF
I/O Capacitance
Table 15-10. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 C, VDD = 1.8 V to 5.5 V)
°
Parameter
Symbol
tCY
Conditions
Min
Typ
Max
Units
V
DD = 2.7 V to 5.5 V
Instruction Cycle
Time
0.67
–
64
µs
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
1.33
0
fTI0
f
TI1
TCL0, TCL1 Input
Frequency
–
–
1.5
MHz
,
VDD = 1.8 V to 5.5V
VDD = 2.7 V to 5.5 V
1
–
MHz
µs
tTIH0, tTIL0
tTIH1, tTIL1
TCL0, TCL1 Input
High, Low Width
0.48
VDD = 1.8 V to 5.5 V
1.8
10
tINTH, tINTL
tRSL
Interrupt Input
High, Low Width
INT0, INT1, INT2, INT4,
KS0-KS7
–
–
–
–
µs
µs
RESET Input Low
Width
Input
10
15-10
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
KS57P5208/P5308/P5312 OTP
Main Oscillator Frequency
(Divided by 4)
CPU Clock
1.5 MHz
6 MHz
0.75 MHz
3 MHz
15.625 kHz
1
2
3
4
5
6
7
1.8
2.7
Supply Voltage (V)
CPU Clock = 1/n x oscillator frequency (n = 4, 8 or 64)
Figure 15-5. Standard Operating Voltage Range
Table 15-11. RAM Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
VDDDR
IDDDR
tSREL
Conditions
Min
1.8
–
Typ
–
Max
5.5
10
–
Unit
V
Data retention supply voltage
Data retention supply current
Release signal set time
–
VDDDR = 1.8 V
–
0.1
µA
µs
0
–
217/fx
(2)
tWAIT
Oscillator stabilization wait
Released by RESET
–
–
ms
time (1)
Released by interrupt
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
15-11
KS57P5208/P5308/P5312 OTP
KS57C5204/C5208/P5208/C5304/C5308/P5308/C5312/P5312
NOTES
15-12
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