KS88C0716N-XX [SAMSUNG]
Microcontroller, 8-Bit, MROM, CMOS, PDIP64, 0.750 INCH, SDIP-64;
| 型号： | KS88C0716N-XX |
| 厂家： | 
SAMSUNG |
| 描述： | Microcontroller, 8-Bit, MROM, CMOS, PDIP64, 0.750 INCH, SDIP-64 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总30页 (文件大小：229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS88C0716/P0716
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM8 PRODUCT FAMILY
Samsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupt
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum of six CPU clocks) can be assigned to
specific interrupt levels.
KS88C0716/P0716 MICROCONTROLLERS
KS88C0716/P0716 single-chip 8-bit microcontrollers are based on the powerful SAM87 CPU architecture. The
internal register file is logically expanded to increase the on-chip register space. The KS88C0716 has 16-Kbyte
mask-programmable ROM. The KS88P0716 has 16-Kbyte one-time-programmable EPROM.
Following Samsung's modular design approach, the following peripherals are integrated with the SAM87 core:
— Seven programmable I/O ports (total 56 pins)
— One 8-bit basic timer for oscillation stabilization and watchdog functions
— One synchronous operating mode and three full-duplex asynchronous UART modes
— Two 8-bit timers with interval timer and PWM modes
— Two 16-bit general-purpose timer/counters
OTP
The KS88C0716 microcontroller is also available in OTP (One Time Programmable) version, KS88P0716.
KS88P0716 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM.
The KS88P0716 is comparable to KS88C0716, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS88C0716/P0716
FEATURES
CPU
General I/O
•
SAM87 CPU core
•
•
•
Four nibble-programmable ports
One bit-programmable port
Memory
Two bit-programmable ports for external
interrupts
•
•
•
272-byte general purpose register area
16-Kbyte internal program memory
ROM-less operating mode
Timers
Two 8-bit timers with interval timer and PWM
modes
•
External Interface
•
•
64-Kbyte external data memory area
Timer/Counters
Two 16-bit general-purpose timer/counters
64-Kbyte external program memory area (ROM-
less mode)
•
Basic Timer
One 8-bit basic timer (BT) for oscillation
stabilization control and watch dog timer function.
Instruction Set
•
•
•
78instructions
IDLE and STOP instructions for power-down
mode
Serial Port
One synchronous operating mode and three full-
duplex asynchronous UART modes
•
Instruction Execution Time
500 ns at 12 MHz fCPU (Min.)
•
Operating Temperature Range
Interrupts
° °
– 40 C to + 85 C
•
•
•
•
•
17 interrupt sources
17 interrupt vectors
Operating Voltage Range
2.7 V to 5.5 V
Eight interrupt levels
Fast interrupt processing
•
Package Types
64-pin SDIP, 64-pin QFP
•
1-2
KS88C0716/P0716
PRODUCT OVERVIEW
Table 1-1. Comparison Table
KS88C0116
Feature
KS88C0716
Core
SAM8
SAM87
Same
Same
ROM
RAM
16 K bytes
272 bytes
I/O
54
56 (add two pins)
Port 6
I/O option
Timer
Open drain (9 V drive)
None
Normal C-MOS output
Same
None
8-bit back-up timer
Timer A, B
Same
— 8-bit
— Interval/PWM mode
— Timer A match interrupt
(some differ in interval mode,
see manual)
Timer C, D
Same
— Gate function
— Timer/counter
Watchdog timer
SIO
None
Watchdog timer (with BT)
Same
UART
— 8-bit/9-bit UART
— SIO
Interrupt
Same
External ´ 12
— P2.4–P2.7, P4.0–P4.7
Internal ´ 6
Internal ´ 5
— Timer A, C, D, SI, SO, Back-up
— Timer A, C, D, SI, SO
Power down
Stop/idle
Same
Oscillator
Crystal, ceramic
Same
CPU clock divider
Execution time (Min.)
1/2
1/1, 1/2, 1/8, 1/16
0.5 ms at 12 MHz (fCPU = 12 MHz)
0.6 ms at 20 MHz (fCPU = 10 MHz)
Max. 12 MHz (at 4.5 V) (2)
Max. 4 MHz (at 2.7 V)
Max. 20 MHz (fCPU = 10 MHz)
Operating frequency
Operating voltage
4.5–5.5 V
2.7–5.5 V at 4 MHz
4.5–5.5 V at 12 MHz
OTP/MTP
MTP
OTP
Pin assignment
Package
–
Different
Same
64SDIP/64QFP
0020h
Start address
0100h
P5CON, P6CON
Interrupt pending bit clear
BANK0
Write "1"
BANK1
Write "0"
NOTES:
1. The KS88C0716 can replace the KS88C0116. Their functions are mostly the same, but there are some differences.
Table 1-1 shows the comparison of KS88C0716 and KS88C0116.
1-3
PRODUCT OVERVIEW
KS88C0716/P0716
2. Operating frequency is maximum CPU clock; the maximum oscillation frequency is 22.1184 MHz.
BLOCK DIAGRAM
P0.0–P0.7
(A8–A15)
P1.0–P1.7
(AD0–AD7) P2.4/INT0–P2.7/INT3
P2.0–P2.3,
RESET
EA
PORT 0
PORT 1
PORT 2
SAM87 BUS
X
IN
MAIN
X
OSC
OUT
PORT 3
PORT 4
P3.0–P3.7
PORT I/O and
INTERRUPT CONTROL
BASIC
TIMER
P4.0/INT4 (TCG)
P4.1/INT5 (TDG)
P4.2/INT6–
P4.7/INT11
TA
TB
TIMERS
A and B
SAM87 CPU
P5.0–P5.3
P5.4–P5.7
PORT 5
PORT 6
TCCK
TDCK
TIMERS
C and D
272-BYTE
REGISTER FILE
P6.0–P6.7
16-KB ROM
RxD
TxD
SERIAL
PORT
Figure 1-1. KS88C0716 Block Diagram
1-4
KS88C0716/P0716
PRODUCT OVERVIEW
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.7/A15
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P0.1/A9
P0.0/A8
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
P4.1/INT5/TDG
P4.0/INT4/TCG
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P5.4
P5.3
P5.2
P5.1
P5.0
KS88C0716
64-SDIP
(Top View)
V
V
V
DD1
DD2
SS2
V
SS1
AS
X
P2.0/
P2.1/
OUT
DS
X
IN
W
EA
P5.6
P5.7
RESET
P2.2/R/
DM
P2.3/
WAIT
P2.4/INT0/
P2.5/INT1
P2.6/INT2
P2.7/INT3
P6.7
P6.6
P6.5
P6.4
P6.3
P3.7/RxD
P3.6/TxD
P3.5/TB
P3.4/TA
P3.3
P3.2
P3.1/TDCK
P3.0/TCCK
P6.0
P6.2
P6.1
Figure 1-2. KS88C0716 Pin Assignments (64-SDIP)
1-5
PRODUCT OVERVIEW
KS88C0716/P0716
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
P4.1/INT5/TDG
P4.0/INT4/TCG
KS88C0716
64-QFP
(Top View)
V
9
DD1
V
10
11
12
13
14
15
16
17
18
19
V
DD2
SS1
X
V
SS2
OUT
AS
DS
X
P2.0/
P2.1/
IN
EA
P5.6
P5.7
W
P2.2/R/
DM
P2.3/
RESET
WAIT
P2.4/INT0/
P2.5/INT1
P2.6/INT2
P2.7/INT3
P3.7/RxD
P3.6/TxD
P3.5/TB
Figure 1-3. KS88C0716 Pin Assignments (64-QFP)
1-6
KS88C0716/P0716
PRODUCT OVERVIEW
Table 1-2. KS88C0716 Pin Descriptions (64-SDIP)
Pin
Name
Pin
Type
Pin
Description
Circuit
Number
SDIP Pin
Number
Share
Pins
P0.0–P0.7
I/O
I/O port with nibble-programmable pins;
Input or push-pull, open-drain output and
software assignable pull-ups; also
configurable as external interface address
lines A8-A15.
E
1–7, 64
A8–A15
P1.0–P1.7
I/O
I/O
Same general characteristics as port 0; also
configurable as external interface
address/data lines AD0–AD7.
E
56–63
40–47
AD0–AD7
P2.0–P2.3
P2.4–P2.7
I/O port with bit-programmable pins; Input
or push-pull output. Lower nibble pins 0–3
are configurable for external interface
signals; upper nibble pins 4–7 are bit-
D-1 (lower
nibble);
AS, DS,
DM, R/W
D-1 (upper
INT0–INT3,
WAIT
programmable for external interrupts INT0– nibble; with
INT3. P2.4 can also be used for external
input.
noise filter)
P3.0–P3.7
P4.0–P4.7
I/O
I/O
I/O port with bit-programmable pins; Input
or push-pull output. Alternate functions
include software-selectable UART transmit
and receive on pins 3.7 and 3.6, timer B
and timer A outputs at pins 3.5 and 3.4, and
timer D and C clock inputs at pins 3.1 and
3.0.
D-1
24– 31
TCCK,
TDCK, TA,
TB, TxD,
RxD
I/O port with bit-programmable pins; Input
or push-pull output; software-assignable
pull-ups. Alternate functions include
D
8–15
INT4–
INT11,
TCG, TDG
(with noise
filter)
external interrupt inputs INT4-INT11 (with
interrupt enable and pending control) and
timer C and D gate input at P4.0 and P4.1.
P5.0–P5.7
P6.0–P6.7
I/O
O
I/O port with nibble-programmable pins;
Input or push-pull, open-drain output;
software-assignable pull-ups.
E
21, 22,
50–55
–
–
Output port with nibble-programmable pins;
push-pull, open-drain output; software-
assignable pull-ups.
E-8
32–39
RxD
I/O
I/O
I/O
I/O
I/O
Bi-directional serial data input pin
Serial data output pin
–
–
24
P3.7
TxD
25
P3.6
TA, TB
Timer A and B output pins
4
27, 26
30, 31
40–43
P3.4, P3.5
P3.0, P3.1
P2.4–P2.7
TCCK, TDCK
INT0–INT3
Timer C and D external clock input pins
D-1
External interrupts. I/O pin 2.4 (share pin
with INT0) is also configurable as a WAIT
signal input pin for the external interface.
D-1
(with noise
filter)
1-7
PRODUCT OVERVIEW
KS88C0716/P0716
Table 1-2. KS88C0716 Pin Descriptions (Continued)
Pin
Name
Pin
Type
Pin
Description
Circuit
Number
SDIP Pin
Number
Share
Pins
INT4–INT11
I/O
Bit-programmable external interrupt input
pins with interrupt pending and enable
/disable control
D
8–15
P4.0–P4.7
(with noise
filter)
XIN, XOUT
RESET
–
I
System clock input and output pins
–
18, 19
23
–
–
System reset pin
B
(internal pull-up: 280 KW)
EA
I
External access (EA) pin with three modes:
0 V: Normal operation (internal ROM)
–
20
–
5 V: ROM-less operation (external interface)
VDD2, VSS2
VDD1, VSS1
–
–
Power input pins for port output (external)
Power input pins for CPU (internal)
–
–
49, 48
16, 17
–
–
1-8
KS88C0716/P0716
PRODUCT OVERVIEW
PIN CIRCUIT
V
DD
Pull-Up Resistor
(Typical Value: 47
)
W
K
Pull-Up
Enable
V
DD
Data
In/Out
Open-Drain
Output Disable
In
Figure 1-4. Pin Circuit Type E (Ports 0, 1, 5)
V
DD
Pull-Up Resistor
(Typical Value: 47 K )
W
Pull-Up
Enable
V
DD
Open-Drain
Data
In/Out
VSS
Figure 1-5. Pin Circuit Type E-8 (Ports 6)
1-9
PRODUCT OVERVIEW
KS88C0716/P0716
Select
V
DD
Port 2 (Low Byte) Data
M
U
X
Data
External Interface
AS, DS, W, DM
(
)
R/
In/Out
Output Disable
VSS
In
Figure 1-6. Pin Circuit Type D-1 (P2.0–P2.3)
V
DD
Port 2 (High Byte) Data
In/Out
Output Disable
Normal Input or
WAIT
VSS
Input
External Interrupt
Noise Filter
Figure 1-7. Pin Circuit Type D-1 (P2.4–P2.7)
1-10
KS88C0716/P0716
PRODUCT OVERVIEW
Select
V
DD
Port 3 Data
M
U
X
Data
Control Output
In/Out
Output Disable
VSS
In
Figure 1-8. Pin Circuit Type D-1 (Port 3)
V
DD
Pull-Up Resistor
(Typical Value: 47
)
W
K
Pull-Up Enable
V
DD
Data
In/Out
Output Disable
Input
VSS
External
Interrpt Input
Noise Filter
Figure 1-9. Pin Circuit Type D (Port 4)
1-11
PRODUCT OVERVIEW
KS88C0716/P0716
V
DD
Pull-up Resistor
(Typical 210 K
W)
RESET
Figure 1-10. Pin Circuit Type B (RESET)
1-12
KS88C0716/P0716
ELECTRICAL DATA
14 ELECTRICAL DATA
OVERVIEW
In this section, KS88C0716 electrical characteristics are presented in tables and graphs. The information is
arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— I/O capacitance
— A.C. electrical characteristics
— Oscillation characteristics
— Oscillation stabilization time
14-1
ELECTRICAL DATA
KS88C0716/P0716
Table 14-1. Absolute Maximum Ratings
Conditions
°
(T = 25 C)
A
Parameter
Symbol
Rating
Unit
Supply voltage
Input voltage
VDD
– 0.3 to + 6.5
V
VI
VO
IOH
All ports (in input mode)
All ports (in output mode)
One I/O pin active
– 0.3 to V
– 0.3 to V
+ 0.3
DD
Output voltage
Output current high
+ 0.3
V
DD
– 10
mA
All I/O pins active
One I/O pin active
– 60
+ 30
Output current low
IOL
mA
Total pin current for ports 0–4
+ 100
+ 100
Total pin current for ports 5 and 6
Operating
temperature
TA
– 40 to + 85
°
°
C
Storage temperature
TSTG
– 65 to + 150
C
14-2
KS88C0716/P0716
ELECTRICAL DATA
Table 14-2. D.C. Electrical Characteristics
°
°
(TA = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
Parameter
Input high
Symbol
Conditions
Min
Typ
Max
Unit
VIH1
All input pins except VIH2
0.8 VDD
–
VDD
V
voltage
VIH2
VIL1
XIN
V
DD – 0.5
Input low voltage
All input pins except VIL2
XIN
–
–
–
0.2 VDD
V
V
VIL2
0.4
–
Output high
voltage
VOH1
VDD= 4.5 V to 5.5 V
IOH = – 4 mA
Port 5, 6
VDD – 1.0
VOH2
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
All output pins except
port 5, 6
Output low voltage
VOL1
VDD = 4.5 V to 5.5 V
–
–
1.0
V
IOL = 15 mA
Ports 5 and 6
VOL2
ILIH1
IOL = 2 mA
Ports 0–4
0.4
3
Input high leakage
current
VIN = VDD
All input pins except XIN, XOUT
–
–
–
–
–
–
mA
mA
mA
ILIH2
ILIL1
VIN = VDD X , X
20
,
IN
OUT
Input low leakage
current
VIN = 0 V
All input pins except XIN, XOUT
– 3
ILIL2
ILOH
VIN = 0 V, XIN, XOUT
– 20
5
Output high
leakage current
VOUT = VDD
All output pins
Output low leakage
current
I
VOUT = 0 V
–
–
– 5
70
mA
LOL
Pull-up resistor
R
VIN = 0 V; VDD = 5 V
Ports 0, 1, 4, 5 and 6
30
47
KW
L1
R
L2
VIN = 0 V; VDD = 5 V
RESET only
110
210
310
14-3
ELECTRICAL DATA
KS88C0716/P0716
Table 14-2. D.C. Electrical Characteristics (Continued)
= 2.7 V to 5.5 V)
°
°
(T = – 40 C to + 85 C, V
A
DD
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Supply current (1)
IDD1
(2)
VDD = 5 V ± 10%
12-MHz oscillation
–
12
25
mA
4-MHz oscillation
4.5
6
10
15
VDD = 3 V ± 10%
12-MHz oscillation
4-MHz oscillation
2.5
3
7
(2)
Idle mode; VDD = 5 V ± 10%
12-MHz oscillation
10
IDD2
4-MHz oscillation
1.5
1.2
4
3
Idle mode; VDD = 3 V ± 10%
12-MHz oscillation
4-MHz oscillation
0.6
0.1
1.5
3
IDD3
Stop mode:
mA
VDD = 5 V ± 10%
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2. At supply current, the CPU clock frequency is same with oscillation frequency (CPU use non divided clock).
Table 14-3. Data Retention Supply Voltage in Stop Mode
°
°
(T = – 40 C to + 85 C)
A
Parameter
Symbol
VDDDR
Conditions
Stop mode
Min
Typ
Max
Unit
Data retention
supply voltage
2
–
6
V
Data retention
supply current
IDDDR
Stop mode, VDDDR = 2.0 V
–
–
3
mA
NOTES:
1. During the oscillator stabilization wait time (tWAIT), all CPU operations must be stopped.
2. Supply current does not include drawn through internal pull–up resistors and external output current loads.
14-4
KS88C0716/P0716
ELECTRICAL DATA
Idle Mode
(Oscillation
Stabilzation Time)
Stop Mode
Data Retention Mode
V
DD
V
DDDR
Normal
Operating
Mode
Execution of
Stop Instruction
EXT INT
0.8 V
DD
0.2 V
DD
t
NOTE:
t
is the same as 16 x BT clock.
WAIT
WAIT
Figure 14-1. Stop Mode Release Timing When Initiated by an External Interrupt
Reset Occurs
Oscillation
Stabilzation
Time
Stop Mode
Data Retention Mode
V
DD
V
Normal
Operating
Mode
DDDR
Execution of
Stop Instruction
RESET
t
WAIT
NOTE:
t
is the same as 4096 x 16 x 1/f
WAIT
OSC.
Figure 14-2. Stop Mode Release Timing When Initiated by a Reset
14-5
ELECTRICAL DATA
KS88C0716/P0716
Table 14-4. Input/Output Capacitance
°
°
(T = – 40 C to + 85 C, VDD = 0 V)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input
CIN
f = 1 MHz; unmeasured
–
–
10
pF
capacitance
pins are connected to VSS
Output
capacitance
COUT
CIO
I/O capacitance
Table 14-5. A.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
A
Parameter
Symbol
tINTH
Conditions
P2.4–P2.7
Min
Typ
Max
Unit
Interrupt input high,
low width
100
–
–
ns
,
t
I
NTL
P4.0–P4.7
Input
100
10
RESET input low width
tRSL
–
–
ms
NOTE: User must keep the larger value with the min value.
t
t
INTL
INTH
0.8 V
DD
0.2 V
DD
Figure 14-3. Input Timing for External Interrupts (Port 2 and 4)
14-6
KS88C0716/P0716
ELECTRICAL DATA
t
RSL
RESET
0.2 V
DD
Figure 14-4. Input Timing for RESET
Table 14-6. Oscillation Characteristics
°
°
(T = – 20 C + 85 C, VDD = 4.5 V to 5.5 V)
A
Oscillator
Crystal
Clock Circuit
Test Condition
Min
Typ
Max
Unit
Oscillation frequency
1
1
1
–
22.1184 MHz
22.1184 MHz
22.1184 MHz
X
X
IN
C1
C2
OUT
Ceramic
Oscillation frequency
XIN input frequency
–
–
X
X
IN
C1
C2
OUT
External clock
X
X
IN
OUT
14-7
ELECTRICAL DATA
KS88C0716/P0716
Table 14-7. Main Oscillator Clock Stabilization Time (t
)
ST1
°
°
(T = – 20 C + 85 C, VDD = 4.5 V to 5.5 V)
A
Oscillator
Crystal
Test Condition
Min
Typ
Max
Unit
VDD = 4.5 V to 5.5 V
–
–
–
20
ms
Ceramic
Stabilization occurs when VDD is equal to the minimum
oscillator voltage range.
–
10
ms
NOTE: Oscillation stabilization time (t
) is the time required for the CPU clock to return to its normal oscillation
ST1
frequency after a power-on occurs, or when Stop mode is released by a RESET signal.
CPU clock
12 MHz
4 MHz
1 MHz
V
1
2
2.7
3
4
4.5
5
5.5
6
7
DD
Figure 14-5. Frequency vs. Voltage
14-8
KS88C0716/P0716
MECHANICAL DATA
ME
15 MECHANICAL DATA
OVERVIEW
The KS88C0716 microcontroller is available in a 64-pin SDIP package (64-SDIP-750) and a 64-pin QFP package
(64-QFP-1420F).
#64
#33
0 15
-
°
64-SDIP-75 0
#32
#1
58.20 MAX
57.80 ± 0.2
0.45 ± 0.1
(1.34)
1.00
1.778
± 0.1
:
Dimensions are in millimeters .
NOTE
Figure 15-1. 64-SDIP-750 Package Dimensions
15-1
MECHANICAL DATA
KS88C0716/P0716
13.20
10.00
± 0.3
± 0.2
0-8°
+0.10
- 0.05
0.15
44-QFP-1010B
0.10 MAX
#44
0.05 MIN
2.05
± 0.10
2.30 MAX
+0.10
- 0.05
#1
0.35
(1.00)
0.80
: Dimensions are in millimeters.
NOTE
Figure 15-2. 64-QFP-1420F Package Dimensions
15-2
KS88C0716/P0716
KS88P0716 OTP
16 KS88P0716 OTP
OVERVIEW
The KS88P0716 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS88C0716 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by
serial data format.
KS88P0716 is fully compatible with KS88C0716, both in function and in pin configuration. As it has simple
programming requirements, KS88P0716 is ideal for use as an evaluation chip for the KS88C0716.
16-1
KS88P0716 OTP
KS88C0716/P0716
P0.6/A14
P0.5/A13
P0.4/A12
P0.3/A11
P0.2/A10
P0.1/A9
P0.0/A8
P4.7/INT11
P4.6/INT10
P4.5/INT9
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P0.7/A15
P1.0/AD0
P1.1/AD1
P1.2/AD2
P1.3/AD3
P1.4/AD4
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P4.4/INT8
P4.3/INT7
P4.2/INT6
P5.4
P5.3
P5.2
P5.1
SDATA/P4.1/INT5/TDG
SCLK/P4.0/INT4/TCG
P5.0
KS88P0716
64-SDIP
(Top View)
V
/V
DD DD1
V
V
DD2
SS2
V
/V
SS SS1
AS
DS
X
OUT
P2.0/
P2.1/
X
IN
/EA
W
V
P2.2/R/
PP
DM
P5.6
P5.7
RESET /RESET
P2.3/
WAIT
P2.4/INT0/
P2.5/INT1
P2.6/INT2
P2.7/INT3
P6.7
P6.6
P6.5
P6.4
P6.3
P3.7/RxD
P3.6/TxD
P3.5/TB
P3.4/TA
P3.3
P3.2
P3.1/TDCK
P3.0/TCCK
P6.0
P6.2
P6.1
Figure 16-1. KS88P0716 Pin Assignments (64-SDIP Package)
16-2
KS88C0716/P0716
KS88P0716 OTP
P4.7/INT11
P4.6/INT10
P4.5/INT9
P4.4/INT8
P4.3/INT7
P4.2/INT6
1
2
3
4
5
6
7
8
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P1.5/AD5
P1.6/AD6
P1.7/AD7
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
SDATA/P4.1/INT5/TDG
SCLK/P4.0/INT4/TCG
KS88P0716
64-QFP
(Top View)
V
/V
DD DD1
9
V
/V
SS SS1
10
11
12
13
14
15
16
17
18
19
V
DD2
X
OUT
V
SS2
AS
DS
X
P2.0/
P2.1/
IN
/EA
V
PP
W
P2.2/R/
P5.6
P5.7
DM
P2.3/
RESET /RESET
WAIT
P2.4/INT0/
P2.5/INT1
P2.6/INT2
P2.7/INT3
P3.7/RxD
P3.6/TxD
P3.5/TB
Figure 16-2. KS88P0716 Pin Assignments (64-QFP Package)
16-3
KS88P0716 OTP
KS88C0716/P0716
Table 16-1. Descriptions of Pins Used to Read/Write the EPROM
During Programming
Main Chip
Pin Name
P4.1
Pin Name
Pin No.
I/O
Function
SDAT
14 (7)
I/O
Serial Data Pin (Output when reading, Input
when writing) Input and Push-pull Output Port
can be assigned.
P4.0
EA
SCLK
VPP
15 (8)
I
I
Serial Clock Pin (Input Only Pin)
20 (13)
EPROM Cell Writing Power Supply Pin
(Indicates OTP Mode Entering) When writing
12.5V is applied and when reading 5 V is applied
(Option).
23 (9)
I
I
Chip Initialization
RESET
RESET
VDD1/VSS1
VDD/VSS
Logic Power Supply Pin. V
should be tied to
DD
16/17
(9/10)
5V during programming.
NOTE: Parentheses indicate 64-QFP pin number.
Table 16-2. Comparison of KS88P0716 and KS88C0716 Features
Characteristic KS88P0716 KS88C0716
16 K byte EPROM 16 K bytes mask ROM
Program Memory
Operating Voltage (VDD
)
2.7 V to 5.5 V
2.7 V to 5.5V
VDD = 5 V, VPP (TEST) = 12.5V
OTP Programming Mode
Pin Configuration
64 SDIP, 64 QFP
64 SDIP, 64 QFP
EPROM Programmability
User Program 1 time
Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (TEST) pin of KS88P0716, the EPROM programming mode is entered. The
operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 15-3 below.
Table 16-3. Operating Mode Selection Criteria
V
DD
VPP
(TEST)
REG/
MEM
ADDRESS
(A15-A0)
R/W
MODE
5 V
5 V
0
0
0
1
0000H
0000H
0000H
0E3FH
1
0
1
0
EPROM read
12.5 V
12.5 V
12.5 V
EPROM program
EPROM verify
EPROM read protection
NOTE: "0" means Low level; "1" means High level.
16-4
KS88C0716/P0716
KS88P0716 OTP
D.C. ELECTRICAL CHARACTERISTICS
Table 16-4. D.C. Electrical Characteristics
°
°
(T = – 40 C to + 85 C, V
DD
= 2.7 V to 5.5 V)
A
Parameter
Input High
Symbol
Conditions
Min
Typ
Max
Unit
V
IH1
All input pins except VIH2
0.8 VDD
VDD
V
Voltage
V
IH2
XIN
VDD – 0.5
V
V
All input pins except VIL2
XIN
0.2 VDD
0.4
Input Low Voltage
V
V
IL1
IL2
V
OH1
VDD = 4.5 V to 5.5 V
V
DD – 1.0
DD – 1.0
Output High
Voltage
I
= – 4 mA
OH
Port 5, 6
V
OH2
VDD = 4.5 V to 5.5 V
IOH = – 1 mA
V
All output pins except port 5, 6
V
V
VDD = 4.5 V to 5.5 V
IOL = 15 mA
Output Low
Voltage
1.0
0.4
V
OL1
Ports 5 and 6
IOL = 2 mA
Ports 0 - 4
OL2
16-5
KS88P0716 OTP
KS88C0716/P0716
Table 16-4. D.C. Electrical Characteristics (Continued)
°
°
(T = – 40 C to + 85 C, VDD = 2.7 V to 5.5 V)
A
Parameter
Input High
Symbol
Conditions
Min
Typ
Max
Unit
ILIH1
VIN = VDD
–
–
3
uA
Leakage Current
All input pins except XIN, XOUT
ILIH2
ILIL1
VIN = VDD X , X
20
,
IN
OUT
VIN = 0 V
Input Low
–
–
– 3
uA
Leakage Current
All input pins except XIN, XOUT
ILIL2
ILOH
VIN = 0 V, XIN, XOUT
– 20
5
V
OUT = VDD
All output pins
VOUT = 0 V
Output High
Leakage Current
–
–
–
–
uA
uA
ILOL
RL1
Output Low
Leakage Current
– 5
70
VIN = 0 V; VDD = 5 V
Ports 0, 1, 4, 5 and 6
Pull-Up Resistor
Supply Current (1)
30
47
KW
RL2
VIN = 0 V; VDD = 5 V
RESET only
110
–
210
12
310
25
(2)
VDD = 5 V ± 10%
12-MHz oscillation
mA
IDD1
4-MHz oscillation
4.5
6
10
15
VDD = 3 V ± 10%
12-MHz oscillation
4-MHz oscillation
2.5
2.5
7
6
(2)
Idle mode; VDD = 5 V ± 10%
12-MHz oscillation
IDD2
4-MHz oscillation
1.5
1.2
4
3
Idle mode; VDD = 3 V ± 10%
12-MHz oscillation
4-MHz oscillation
0.6
0.1
1.5
3
IDD3
Stop mode:
uA
VDD = 5 V ± 10%
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2. At supply current, the CPU clock frequency is the same as oscillation frequency (CPU use non divided clock).
16-6
KS88C0716/P0716
KS88P0716 OTP
START
Address= First Location
V
=5V, V =12.5V
PP
DD
x = 0
Program One 1ms Pulse
Increment X
YES
x = 10
NO
FAIL
FAIL
NO
Verify Byte
Verify 1 Byte
Last Address
Increment Address
V
= V = 5 V
PP
DD
FAIL
Compare All Byte
PASS
Device Failed
Device Passed
Figure 16-3. OTP Programming Algorithm
16-7
KS88P0716 OTP
KS88C0716/P0716
NOTES
16-8
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