KS88C8316N-XX [SAMSUNG]
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| 型号： | KS88C8316N-XX |
| 厂家： | 
SAMSUNG |
| 描述： | 暂无描述 微控制器 |
| 文件： | 总19页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KS88C8316/C8324/P8324
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
SAM87 PRODUCT FAMILY
Samsung's SAM87 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Release by interrupt of Idle and Stop power-down modes
— Built-in basic timer circuit with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to
specific interrupt levels.
KS88C8316/C8324/P8324
The KS88C8316 microcontroller has 16 K bytes of on-chip program memory and the KS88C8324 has 24 K bytes.
Both chips have a 272-byte general-purpose internal register file. The interrupt structure has seven interrupt
sources with six interrupt vectors. The CPU recognizes six interrupt priority levels.
Using a modular design approach, the following peripherals were integrated with the SAM87 core to make the
KS88C8316/C8324/P8324 suitable for use in color television and other types of screen display applications:
— Four programmable I/O ports (26 pins total: 16 general-purpose I/O pins; 8 n-channel, open-drain output pins)
— 2 channel A/D converter (4-bit resolution)
— 14-bit PWM output (one channels: push-pull type)
— Basic timer (BT) with watchdog timer function
— One 8-bit timer/counter (T0) with interval timer
— One 8-bit general-purpose timer/counter (TA) with prescalers
— On-screen display (OSD) with a wide range of programmable features including halftone control signal output
The KS88C8316/C8324 are available in a versatile 42-pin SDIP package.
OTP
The KS88C8316/C8324 microcontroller is also available in OTP (One Time Programmable) version, KS88P8324.
KS88P8324 microcontroller has an on-chip 24K-byte one-time-programmable EPROM instead of masked ROM.
The KS88P8324 is comparable to KS88C8316/C8324, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
KS88C8316/C8324/P8324
FEATURES
CPU
Pulse Width Modulation Module
•
SAM87 CPU core
•
14-bit PWM with one-channel output (push-pull
type)
Memory
•
•
PWM counter and data capture input pin
•
•
16-K byte (KS88C8316) or 24-K byte
(KS88C8324) internal program memory
Frequency: 5.859 kHz to 23.437 kHz with a
6-MHz CPU clock
272-byte general-purpose register area
On-Screen Display (OSD)
Instruction Set
•
•
Video RAM: 252 ´ 12 bits
•
•
78 instructions
Character generator ROM: 256 ´ 18 ´ 16 bits
(256 display characters: fixed: 2, variable: 254)
IDLE and STOP instructions added for power-
down modes
•
•
•
•
•
•
•
252 display positions (12 rows ´ 21 columns)
16-dot ´ 18-dot character resolution
16 different character sizes
Instruction Execution Time
750 ns (minimum) with an 8-MHz CPU clock
•
Eight character colors
Interrupts
Vertical direction fade-in/fade-out control
Eight colors for character and frame background
•
•
•
7 interrupt sources with 6 vectors
Halftone control signal output; selectable for
individual characters
6 interrupt levels
Fast interrupt processing for select levels
•
Synchronous polarity selector for H-sync and
V-sync input
General I/O
•
•
•
Four I/O ports (26 pins total)
Oscillator Frequency
Six open-drain pins for up to 6-volt loads
Two open-drain pins for up to 5-volt loads
•
•
5-MHz to 8-MHz external crystal oscillator
Maximum 8-MHz CPU clock
8-Bit Basic Timer
Operating Temperature Range
•
•
Three selectable internal clock frequencies
Watchdog or oscillation stabilization function
° °
– 20 C to + 85 C
•
Operating Voltage Range
4.5 V to 5.5 V
Timer/Counters
•
•
One 8-bit timer/counter (T0) with three internal
clocks and interval timer mode.
Package Type
42-pin SDIP
•
One general-purpose 8-bit timer/counters with
interval timer mode (timer A)
•
A/D Converter
•
•
Two analog input pins; 4-bit resolution
3.125 µs conversion time (8-MHz CPU clock)
1-2
KS88C8316/C8324/P8324
PRODUCT OVERVIEW
BLOCK DIAGRAM
P0.0 - P0.7
PORT 0
P1.0 - P1.7
PORT 1
RESET
INT0 - INT1
TEST
X
SAM87 BUS
IN
MAIN
OSC
X
OUT
TIMER A
TIMER 0
PORT I/O and INTERRUPT
CONTROL
OSC
IN
L-C OSC
OSC
OUT
H-sync
V-sync
Vred
Vgreen
Vblue
Vblank
OSDHT
ON-
SCREEN
DISPLAY
SAM87 CPU
PWM
BLOCK
PWM
COUNTER
and DATA
CAPTURE
CAPA
16-KB ROM (8316)
24-KB ROM (8324)
272-BYTE
REGISTER FILE
ADC0
ADC1
4-BIT
ADC
14-BIT
PWM
PWM0
SAM87 BUS
PORT 2
PORT 3
P2.0 - P2.7
P3.0 - P3.1
Figure 1-1. Block Diagram
1-3
PRODUCT OVERVIEW
KS88C8316/C8324/P8324
PIN ASSIGNMENTS
P2.5/PWM0
P2.1
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P0.0
P0.1
P0.2
P0.3
P0.4
2
P2.2(
P2.3(
)
SCL
3
)
SDA
P2.4
P2.0
P2.6
4
5
6
V
SS2
7
CAPA
P0.5
P1.7
8
P3.0/ADC0
P3.1/ADC1
P0.6
9
V
DD
RESET
KS88C8316/
C8324/P8324
42-PIN SDIP
(Top View)
10
11
12
13
14
15
16
17
18
19
20
21
X
OUT
P0.7
X
IN
V
TEST
SS1
P1.0/INT0
P1.1/INT1
P1.2
OSC
OSC
OUT
IN
V-sync
H-sync
Vblank
Vred
P1.3
P1.4
P1.5
P1.6
Vgreen
Vblue
P2.7/OSDHT
Figure 1-2. KS88C8316/C8324/P8324 Pin Assignment Diagram
1-4
KS88C8316/C8324/P8324
PRODUCT OVERVIEW
Table 1-1. KS88C8316/C8324 Pin Descriptions
Pin Name
P0.0–P0.7
P1.0–P1.1
Pin
Type
Pin Description
Circuit
Type
Pin
Numbers
Share
Pins
I/O
General I/O port (8-bit), configurable for
digital input or push-pull output.
3
11–12, 35,
38–42
I/O
General I/O port (2-bit), configurable for
digital input or n-channel open-drain output.
P1.0–P1.1 can withstand up to 6-volt loads.
Multiplexed for alternative use as external
interrupt inputs INT0–INT1.
7
5
14–15
16–19
INT0–INT1
P1.2–P1.5
P1.6–P1.7
General I/O port (4-bit), configurable for
digital input or n-channel open-drain output.
P1.2–P1.5 can withstand up to 6-volt loads.
High current port (10mA).
General I/O port (2-bit), configurable for
digital input or push-pull output.
3
2
20, 8
2–7
P2.0–P2.4,
P2.6
I/O
General I/O port (6-bit). I/O mode or
n-channel open-drain, push-pull output
mode is software configurable. Pins can
withstand up to 5-volt loads.
P2.2: OTP serial clock pin
P2.3: OTP serial data pin
P2.5, P2.7
General I/O port (2-bit). I/O mode or
n-channel open-drain, push-pull output
mode is software configurable. Pins can
withstand up to 5-volt loads.
2
1, 21
PWM0
OSDHT
Each pin has an alternative function.
P2.5: PWM0 (14-bit PWM output)
P2.7: OSDHT (Halftone signal output)
1-5
PRODUCT OVERVIEW
KS88C8316/C8324/P8324
Table 1-1. KS88C8316/C8324 Pin Descriptions (Continued)
Pin Name
Pin
Type
Pin Description
Circuit
Type
Pin
Numbers
Share
Pins
P3.0–P3.1
I/O
General I/O port (2 bits), configurable for
digital input or n-channel open-drain output.
P3.0–P3.1 can withstand up to 5-volt loads.
Multiplexed for alternative use as external
interrupt inputs ADC0–ADC1.
6
9–10
ADC0
ADC1
PWM0
O
I
Output pin for 14-bit PWM0 circuit
Analog inputs for 4-bit A/D converter
2
6
1
P2.5
ADC0–ADC1
9,10
P3.0–
P3.1
INT0–INT1
OSDHT
I
External interrupt input pins
7
14,15
P1.0–
P1.1
O
O
Halftone control signal output for OSD
2
4
21
P2.7
–
Vblue, Vgreen
Vred, Vblank
Digital blue, green, red, and video blank
signal outputs for OSD
22–25
H-sync
I
H-sync input for OSD
V-sync input for OSD
8
26
27
–
V-sync
OSCIN, OSCOUT
I, O
I
L-C oscillator pins for OSD clock frequency
generation
–
–
28,29
–
–
0 V: Normal operation mode
5 V: Factory test mode
TEST
13
12.5 V: OTP write mode
XIN, XOUT
I, O
System clock pins
–
31, 32
–
I
System reset input pin
Power supply pins
1
–
33
13
–
–
RESET
VDD, VSS1, VSS2
–
CAPA
I
Input for capture A module
8
26
–
1-6
KS88C8316/C8324/P8324
PRODUCT OVERVIEW
PIN CIRCUITS
V
DD
VDD
DATA
I/O
200 K
W
NOISE
FILTER
IN
INPUT
V
SS
INPUT
Figure 1-3. Pin Circuit Type 1 (RESET)
Figure 1-5. Pin Circuit Type 3
(P0.0–P0.7, P1.6–P1.7)
V
DD
V
DD
DATA
I/O
OPEN-
DRAIN
DATA
I/O
OUTPUT
DISABLE
V
SS
V
SS
INPUT
Figure 1-4. Pin Circuit Type 2
(P2.0–P2.7, PWM0, OSDHT)
Figure 1-6. Pin Circuit Type 4
(Vblue, Vgreen, Vred, Vblank)
1-7
PRODUCT OVERVIEW
KS88C8316/C8324/P8324
I/O
I/O
DATA
DATA
V
SS
V
SS
INPUT
INT
INPUT
NOISE FILTER
Circuit type 5 can withstand up to
6-volt loads.
NOTE:
Circuit type 7 can withstand up to
6-volt loads.
NOTE:
Figure 1-9. Pin Circuit Type 7
(P1.0–P1.1, INT0–INT1)
Figure 1-7. Pin Circuit Type 5 (P1.2–P1.5)
I/O
DATA
V
SS
NOISE
FILTER
INPUT
IN
INPUT
A/D IN
Circuit type 6 can withstand up to
5-volt loads.
NOTE:
Figure 1-8. Pin Circuit Type 6
(P3.0–P3.1, ADC0–ADC1)
Figure 1-10. Pin Circuit Type 8
(V-Sync H-Sync, CAPA)
1-8
KS88C8316/C8324/P8324
ELECTRICAL DATA
15 ELECTRICAL DATA
OVERVIEW
In this section, KS88C8316/C8324 electrical characteristics are presented in tables and graphs. The information
is arranged in the following order:
— Absolute maximum ratings
— D.C. electrical characteristics
— I/O capacitance
— A.C. electrical characteristics
— Input timing measurement points for t
and t
NF2
NF1
— Data retention supply voltage in Stop mode
— Stop mode release timing when initiated by RESET
— Main oscillator and L-C oscillator frequency
— Clock timing measurement points for X
IN
— Main oscillator clock stabilization time (t
)
ST
— A/D converter electrical characteristics
— Characteristic curves
15-1
ELECTRICAL DATA
KS88C8316/C8324/P8324
Table 15-1. Absolute Maximum Ratings
°
(TA = 25 C)
Parameter
Supply Voltage
Input Voltage
Symbol
Conditions
Rating
Unit
V
VDD
–
– 0.3 to + 6.0
– 0.3 to + 7
VI1
VI2
VO
IOH
P1.0–P1.5 (open-drain)
V
All port pins except V
All output pins
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 18
I1
Output Voltage
V
Output Current
High
One I/O pin active
mA
All I/O pins active
One I/O pin active
– 60
+ 30
IOL
Output Current
Low
mA
Total pin current for port 1
+ 100
+ 100
Total pin current for ports 0, 2, and 3
–
TA
°
C
Operating
– 20 to + 85
Temperature
TSTG
°
C
Storage
–
– 65 to + 150
Temperature
Table 15-2. D.C. Electrical Characteristics
°
°
(TA = – 20 C to + 85 C, VDD = 4.5 V to 5.5 V)
Parameter
Input High
Symbol
Conditions
Min
Typ
Max
Unit
VIH1
All input pins except VIH2
0.8 VDD
VDD
–
V
Voltage
X
X
VIH2
VIL1
VIL2
VOH
2.7 V
–
IN, OUT
All input pins except VIL2
XIN, XOUT
0.2 VDD
1.0 V
–
Input Low Voltage
–
–
V
V
IOH = – 500 µA
VDD – 0.8
Output High
Voltage
P0, P1.6–P1.7, P2
R, G, B, Vblank
VOL1
VOL2
VOL3
VOL4
I
= 4 mA
Output Low
Voltage
–
–
–
–
–
–
–
–
0.4
0.8
0.4
0.4
V
OL
P0, P1.6–P1.7
= 10 mA
I
OL
P1.2–P1.5
= 2 mA
I
OL
P1.0–P1.1, P3.0–P3.1
= 1 mA
I
V
OL
R, G, B, Vblank, P2
15-2
KS88C8316/C8324/P8324
ELECTRICAL DATA
Table 15-2. D.C. Electrical Characteristics (Continued)
(T = – 20 C to + 85 C, VDD = 4.5 V to 5.5 V)
°
°
A
Parameter
Input High
Symbol
Conditions
VIN = VDD
Min
Typ
Max
Unit
ILIH1
–
–
3
µA
Leakage Current
All input pins except ILIH2
and ILIH3
ILIH2
ILIH3
ILIL1
VIN = VDD, OSCIN, OSCOUT
VIN = VDD, XIN, XOUT
10
20
2.5
–
10
–
VIN = 0 V
All input pins except ILIL2,
ILIL3, and RESET
Input Low
Leakage Current
– 3
µA
µA
ILIL2
ILIL3
VIN = 0 V, OSCIN, OSCOUT
– 10
– 20
3
V
IN
= 0 V, X X
IN,
OUT
– 2.5
–
– 10
–
ILOH1
VOUT = VDD
Output High
Leakage Current
All output pins except I
LOH2
ILOH2
ILOL
VOUT = 6 V
P1.0–P1.5
10
– 3
20
VOUT = 0 V
All output pins
Output Low
Leakage Current
–
–
–
7
µA
IDD1
Supply Current
(note)
Normal mode;
VDD = 4.5 V to 5.5 V
mA
8-MHz CPU clock
IDD2
Idle mode;
VDD = 4.5 V to 5.5 V
2
1
10
10
8-MHz CPU clock
IDD3
Stop mode;
µA
VDD = 4.5 V to 5.5 V
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
15-3
ELECTRICAL DATA
KS88C8316/C8324/P8324
Table 15-3. Input/Output Capacitance
°
°
(TA = – 20 C to + 85 C, VDD = 0 V)
Parameter
Input
capacitance
Symbol
Conditions
Min
Typ
Max
Unit
CIN
f = 1 MHz; unmeasured pins
are connected to VSS
–
–
10
pF
COUT
CIO
Output
capacitance
I/O capacitance
Table 15-4. A.C. Electrical Characteristics
°
°
(TA = – 20 C to + 85 C, VDD = 4.5 V to 5.5 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
tVW
V-sync Pulse
Width
–
4
–
–
µs
tHW
H-sync Pulse
Width
–
3
–
–
–
µs
ns
tNF1
tNF2
tNF3
tNF4
tNF5
Noise Filter
P1.0–P1.1, V-sync
–
–
–
–
–
350
1000
15
RESET
Glitch filter (oscillator block)
tCAPA
ns
CAPA
5
–
–
H-sync
650
NOTE: t
= f
/128.
OSC
CAPA
1tCPU
tNF1L
tNF2
tNF1H
0.8VDD
0.2VDD
Figure 15-1. Input Timing Measurement Points for t
and t
NF1
NF2
15-4
KS88C8316/C8324/P8324
ELECTRICAL DATA
Table 15-5. Data Retention Supply Voltage in Stop Mode
°
°
(TA = – 20 C to + 85 C)
Parameter
Symbol
VDDDR
Conditions
Stop mode
Min
Typ
Max
Unit
Data Retention
Supply Voltage
2
–
6
V
IDDDR
Stop mode, VDDDR = 2.0 V
Data Retention
Supply Current
–
–
5
µA
NOTES:
1. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
2. During the oscillator stabilization wait time (t
), all CPU operations must be stopped.
WAIT
OSCILLATION
STABILIZATION
TIME
t
SREL
STOP MODE
NORMAL
OPERATING
MODE
DATA RETENTION MODE
VDD
VDDDR
EXECUTION OF
STOP INSTRUCTION
RESET
tWAIT
t
is the same as 4096 x 16 x 1 / f
OSC
NOTE:
WAIT
Figure 15-2. Stop Mode Release Timing When Initiated by a Reset
15-5
ELECTRICAL DATA
KS88C8316/C8324/P8324
Table 15-6. Main Oscillator and L-C Oscillator Frequency
°
°
(T = – 20 C to + 85 C, VDD = 4.5 V to 5.5 V)
A
Oscillator
Crystal
Clock Circuit
Conditions
OSD block active
Min
Typ
Max
Unit
C1
5
6
8
MHz
XIN
XOUT
C2
C1
OSD block inactive
OSD block active
0.5
5
6
6
8
8
Ceramic
MHz
MHz
XIN
XOUT
C2
OSD block inactive
OSD block active
0.5
5
6
6
8
8
External Clock
XIN
XOUT
OSD block inactive
0.5
5
6
8
8
C1
L-C Oscillator
Recommend value:
C1 = C2 = 20 pF
6.5
MHz
MHz
OSC
IN
OSCOUT
C2
CPU Clock Frequency
–
0.032
6.0
8
1 / f
OSC
tXL
tXH
X
IN
2.7 V
1.0 V
Figure 15-3. Clock Timing Measurement Points for XIN
15-6
KS88C8316/C8324/P8324
ELECTRICAL DATA
Table 15-7. Main Oscillator Clock Stabilization Time
(T = – 20 C to + 85 C, VDD = 4.5 V to 5.5 V)
°
°
A
Oscillator
Crystal
Symbol
Test Condition
VDD = 4.5 V to 6.0 V
Min
Typ
Max
20
Unit
–
–
–
ms
Ceramic
(Oscillation stabilization occurs when
VDD is equal to the minimum oscillator
10
voltage range.)
X
IN
input High and Low level width
External Clock
65
–
100
ns
(tXH, tXL)
tSREL
tWAIT
Release Signal
Setup Time
Normal operation
–
–
1000
8.3
–
–
ns
Oscillation
Stabilization
Wait Time (1)
CPU clock = 8 MHz; Stop mode
released by RESET
ms
(2)
CPU clock = 8 MHz; Stop mode
released by an interrupt
NOTES:
1. Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency after a
power-on occurs, or when Stop mode is released.
2. The oscillation stabilization interval is determined by the basic timer (BT) input clock setting.
Table 15-8. A/D Converter Electrical Characteristics
°
°
(TA = – 20 C to + 85 C, VDD = 4.5 V to 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Absolute
Accuracy (1)
–
CPU clock = 8 MHz
–
–
LSB
± 0.5
tCON
Conversion
Time (2)
–
–
µs
t
CPU ´ 25
(3)
VIAN
RAN
VSS
2
VDD
–
Analog Input
Voltage
–
–
V
Analog Input
Impedance
MW
NOTES:
1. Excluding quantization error, absolute accuracy values are within ± 1/2 LSB.
2. 'Conversion time' is the time required from the moment a conversion operation starts until it ends.
3. The unit t means one CPU clock period.
CPU
15-7
KS88C8316/C8324/P8324
MECHANICAL DATA
16 MECHANICAL DATA
OVERVIEW
The KS88C8316/C8324 microcontrollers are available in a 42-pin SIP package (42-SDIP-600).
42
22
0 ~ 15 °
42-SDIP-600
#1
21
39.10 ± 0.2
(1.77)
1.778
0.50 ± 0.1
1.00 ± 0.1
: Package dimensions are in millimeters.
NOTE
Figure 16-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)
16-1
KS88C8316/C8324/P8324
KS88P8324 OTP
17 KS88P8324 OTP
OVERVIEW
The KS88P8324 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
KS88C8316/C8324 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is
accessed by serial data format.
The KS88P8324 is fully compatible with the KS88C8316/C8324, both in function and in pin configuration.
Because of its simple programming requirements, the KS88P8324 is ideal for use as an evaluation chip for the
KS88C8316/C8324.
17-1
KS88P8324 OTP
KS88C8316/C8324/P8324
P2.5/PWM0
P2.1
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P0.0
P0.1
P0.2
P0.3
P0.4
V
2
P2.2
P2.3
P2.4
P2.0
P2.6
P1.7
SCLK/
SDAT/
3
4
5
6
/
V
SS2 SS
7
CAPA
8
P0.5
P3.0/ADC0
P3.1/ADC1
P0.6
9
V
/
V
DD DD
RESET
RESET/
10
11
12
13
14
15
16
17
18
19
20
21
KS88P8324
42-PIN SDIP
(Top View)
X
OUT
P0.7
X
IN
/TEST
TEST
V
/
V
SS1
SS
P1.0/INT0
P1.1/INT1
P1.2
OSC
OSC
OUT
IN
V-sync
H-sync
Vblank
Vred
P1.3
P1.4
P1.5
P1.6
Vgreen
Vblue
P2.7/OSDHT
The bolds indicate an OTP pin name.
NOTE:
Figure 17-1. KS88P8324 Pin Assignments (42-SDIP)
17-2
KS88C8316/C8324/P8324
KS88P8324 OTP
Table 17-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip
Pin Name
P2.3 (Pin 4)
During Programming
I/O
Pin Name
Pin No.
Function
SDAT
4
I/O
Serial data Pin (Output when reading, Input
when writing) Input and Push-pull Output Port
can be assigned
P2.2 (Pin 3)
TEST
SCLK
3
I/O
I
Serial clock Pin (Input Only Pin)
VPP (TEST)
13
0 V: Operating mode
5 V: Test mode
12.5 V: OTP mode
33
I
I
0 V: Chip initialization, OTP mode
5 V: Operating mode
RESET
RESET
VDD/VSS
VDD/VSS
34/30, 37
Logic Power Supply Pin.
Table 17-2. Comparison of KS88P8324 and KS88C8316/C8324 Features
Characteristic KS88P8324 KS88C8316/C8324
24 K byte EPROM
Program Memory
24 K byte mask ROM
4.5 V to 5.5 V
Operating Voltage (VDD
)
4.5 V to 5.5 V
VDD = 5 V, V (TEST) = 12.5 V
PP
OTP Programming Mode
–
Pin Configuration
42 SDIP
42 SDIP
EPROM Programmability
User Program 1 time
Programmed at the factory
17-3
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