KT3170 [SAMSUNG]
LOW POWER DTMF RECEIVER; 低功耗双音多频接收器
| 型号： | KT3170 |
| 厂家： | 
SAMSUNG |
| 描述： | LOW POWER DTMF RECEIVER |
| 文件： | 总7页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KT3170
LOW POWER DTMF RECEIVER
INTRODUCTION
18-DIP-300A
The KT3170 is a complete Dual Tone Multiple Frequency
(DTMF) receiver that is fabricated by low power CMOS
and the Switched-Capacitor Filter technology.
This LSI consists of band split filters, which seperates
counting section which verifies the frequency and
duration of the received tones before passing the cor-
responding code to the output bus. It decodes all 16
DTMF tone pairs into a 4bits digital code.
The externally required components are minimized by
on chip provision of a differential input AMP, clock
oscillator and latched three state interface. The on chip
clock generator requires only a low cost TV cystal as
an external component.
FEATURES
·
·
·
·
·
·
Detects all 16 standard tones.
Low power consumption : 15mW (Typ)
Single power supply : 5V
Uses inexpensive 3.58MHz crystal
Three state outputs for microprocessor interface
Good quality and performance for using in
exchange system
ORDERING INFORMATION
Device
Package
Operating
KT3170N
18-DIP-300A
- 25°C ~ + 75°C
·
Power down mode/input inhibit
APPLICATIONS
PIN CONFIGURATION
·
·
·
·
·
·
·
·
·
·
PABX
Central Office
IN+
VDD
1
2
3
4
5
6
7
18
Paging Systems
Remote Control
Credit Card Systems
Key Phone System
Answering Phone
Home Automation System
Mobile Radio
IN-
GS
17 SI/GTO
ESO
16
VREF
DSO
15
KT3170
IIN
Q4
14
Remote Data Entry
PDN
OSC1
OSC2
GND
13 Q3
12 Q2
Q1
8
9
11
OE
10
Fig. 1
KT3170
LOW POWER DTMF RECEIVER
PIN DESCRIPTION
Pin No
Symbol
Description
1
2
IN +
IN -
Non inverting input of the op amp.
Inverting input of the op amp.
Gain Select. The output used for gain adjustment of analog input
signal with a feedback resistor.
3
4
5
GS
VREF
IIN
Reference Voltage output (VDD/2, Typ) can be used to bias the op amp
input of VDD/2.
Input inhibit. High input states inhibits the detection of tones. This
pin is pulled down internally.
Control input for the stand-by power down mode. Power down occurs
when the signal on this input is in high states. This pin is pulled down
internally.
6
PDN
Clock input/output. A inexpensive 3.579545MHz crystal connected
between these pins completes internal oscillator. Also, external clock
can be used.
OSC1
OSC2
7, 8
9
GND
OE
Ground pin.
Output Enable input. Outputs Q1-Q4 are CMOS push pull when OE is
High and open circuited (High impedance) when disabled by pulling OE
low. Internal pull up resistor built in.
10
Three state data output. When enabled by OE, these digital outputs
provide the hexadecimal code corresponding to the last valid tone
pair received.
11 - 14
Q1 - Q4
DSO
Delayed Steering Output. Indicates that valid frequencies have been
present for the required guard time, thus constituting a valid signal.
Presents a logic high when a received tone pair has been registered
and the output latch is updated. Returns to logic low when the
15
voltage on SI/GTO falls below VTH
.
Early Steering Outputs. Indicates detection of valid tone output a
logic high immediately when the digital algorithm detects a
recognizable tone pair. Any momentary loss of signal condition will
cause ESO to return to low.
16
ESO
Steering Input/Guard Time Output. A voltage greater the VTS
detected at SI causes the device to register the detected tone pair
and update the output latch. A voltage less than VTS frees the device
to accept a new tone pair. The GTO output acts to reset the external
steering time constant, and its state is a function of ESO and the
voltage on SI
17
18
SI/GTO
VDD
Power Supply (+5V, Typ)
KT3170
LOW POWER DTMF RECEIVER
ABSOLUTE MAXIMUM RATINGS
Characteristics
Symbol
Value
Unit
Power Supper Voltage
Analog Input Voltage Range
Digital Input Voltage Range
Output Voltage Range
Current On Any Pin
VDD
VI (A)
VI (D)
VO
6
V
V
- 0.3 ~ VDD + 0.3
- 0.3 ~ VDD + 0.3
- 0.3 ~ VDD + 0.3
10
V
V
II
mA
°C
°C
Operating Temperature
Storage Temperature
TOPR
TSTG
- 40 ~ + 85
-60 ~ + 150
ELECTRICAL CHARACTERISTICS (VDD = 5V, Ta = 25°C, unless otherwise noted)
Characteristic
Operating Voltage
Symbol
Test Conditions
Min
Typ
Max
Unit
VDD
IDD
-
-
-
-
-
4.75
-
3.0
15
-
5.25
9.0
45
1.5
-
V
mA
mW
V
Operating Current
-
Power Dissipation
PD
-
Input Voltage Low
VIL
-
Input Voltage High
VIH
3.5
-
V
Input Leakage Current
Pull Up Current On OE Pin
Analog Input Impedance
Steering Input Threshold Voltage
Output Voltage Low
II (LKG)
IPU
VIN = GND or VDD
-
0.1
7.5
10
-
-
mA
mA
MW
V
OE = GND
fIN = 1KHz
-
8
15
-
RI
VTH
-
2.2
-
2.5
0.03
VOL
No Load
-
V
-
VOH
No Load
4.97
1
-
V
Output Current
IO (SINK)
IO (SOURCE)
VO (REF)
RO (REF)
VIO
VOL = 0.4V
VOH = 4.6V
2.5
0.8
-
-
mA
mA
V
Output Current
0.4
2.4
-
-
2.8
-
VREF Output Voltage
VREF Output Resistance
Analog Input Offset Voltage
-
-
-
10
25
KW
mV
-
-
Gain Setting Amp
-
-
Power Supply Rejection Ratio
PSRR
60
dB
at 1KHz
Common Mode Rejection Ratio
Open Loop Voltage Gain
CMRR
GV
- 3.0V < VIN < 3.0V
-
-
-
-
-
60
65
-
-
-
-
-
dB
dB
Gain Setting Amp at 1KHz
Open Loop Unit Gain Bandwidth
Analog Output Voltage Swing
Acceptable Capacitive Load
BW
-
RL = 100K
GS
1.5
4.5
100
MHz
VP-P
pF
VO (P-P)
CL
Acceptable Resistive Load
RL
GS
-
-
50
-
-
KW
Analog Input Common Mode
Voltage Range
VCM
No Load
3.0
VP-P
KT3170
LOW POWER DTMF RECEIVER
AC ELECTRICAL CHARACTERISTICS (VDD = 5V, Ta = 25°C, fCK = 3.579545MHz)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Valid Input Signal Range
(each tone of composite signal)
Dual Tone Twist Accept
VI (VAL)
dBm
-
-29
-
1.0
-
TW
-
-
-
-
dB
-
± 10
± 1.5%
-
Acceptable Frequency Deviation
Df
± 2Hz
Frequency Deviation Reject
Third Tone Tolerance
-
-
-
-
-
-
-
DfR
T3rd
TN
± 3.5%
-
-25
-
-16
-12
22
dB
dB
dB
MHz
nS
nS
%
Noise Tolerance
-
Dial Tolerance
DT
-
18
Crystal Clock Frequency
fCK
-
3.5759 3.5795 3.5831
Maximum Clock Input Rise Time
Maximum Clock Input Fall Time
Acceptable Clock Input Duty Cycle
Acceptable Capacitive Load
Tone Present Detect Time
Tone Absent Detect Time
Minimum Tone Duration Accept
Maximum Tone Duration Reject
Acceptable Interdigit Pause
Rejectable Interdigit Pause
Propagation Delay Time SI to Q
Propagation Delay Time SI to DSO
Output Data Setup Q to DSO
tR (MAX)
tF (MAX)
DCK
External Clock
External Clock
External Clock
OSC2 PIN
-
-
-
-
-
110
110
60
30
14
8.5
40
-
40
-
50
-
CL
pF
tDET (P)
tDET (A)
tTDA (MIN)
tTDR (MAX)
tIDP (A)
tIDP (R)
tD (SI-Q)
tD (SI-D)
tSU
5
11
4
mS
mS
mS
mS
mS
mS
mS
mS
mS
-
0.5
-
User Adjustable
User Adjustable
User Adjustable
User Adjustable
OE = High
OE = High
OE = High
-
20
-
-
-
40
-
20
-
-
8
11
16
-
-
12
3.4
-
Propagation Delay Time OE to Q
(Enable)
nS
nS
-
-
RL = 10K, CL = 50pF
RL = 10K, CL = 50pF
50
60
-
tD (QE-Q) EN
Propagation Delay Time OE to Q
(disable)
tD (OE-Q) DIS
300
Notes : 1. Digit sequence consists of all 16 DTMF tones.
2. Tone duration = 40mS, Tone pause = 40mS.
3. Nominal DTMF frequencies are used.
4. Both tones in the composite signal have an equal amplitude.
5. Tone pair is deviated by ± 1.5% ± 2Hz.
6. Bandwidth limited (3KHz) Gaussian Noise.
7. The precise dial tone frequencies are (350Hz and 440Hz) ± 2%.
8. For an error rate of better than 1 in 10000.
9. Referenced to lowest level frequency component in DTMF signal.
10. Minimum signal acceptance level is measured with specitied maximum frequency deviation.
11. This item also applies to a third tone injected onto the power supply.
12. Referenced to Fig. 1 Input DTMF tone level at -28dBm.
KT3170
LOW POWER DTMF RECEIVER
TEST CIRCUIT
7
KS58006
8
KT3170
HL74HCTLS02
HL74LS47
LTS542R
KT3170
LOW POWER DTMF RECEIVER
TIMING DIAGRAM
tT
t T
tI D P
( A )
tI D P
( R )
D
R
(
M
A
X
)
D
A
(
M
I
N
)
D
T
M
F
#
n
D
T
M
F
#
n
+
1
D T M F # n + 1
D
T M F
I
N
P
U
T
tD
tD
E
E
T
( P
)
T ( A )
E
S
O
t P
t A
G
T
G
T
V T
H
S
I
/
G
T
O
t S
U
D
E
C
O D E D T O N E # ( n - 1 )
Q
1
-
Q
4
t D
( S I - D )
D
S
O
E
tD
(
O E - Q ) D I S
t D
(
O E - Q ) E N
O
Fig. 3
DIGITAL OUTPUT
Outputs Q1-Q4 are CMOS push pull when enabled (EO = High) and open circuited (high impedance) when disabled
by pulling EO = Low. These digital outputs provide the hexadecimal code corresponding to the DTMF signals. The table
below describes the hexadecimal.
LOW
HIGH
NO
OE
Q4
Q3
Q2
Q1
FREQUENCY FREQUENCY
1
2
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
-
1209
1336
1477
1209
1336
1477
1209
1336
1477
1336
1209
1477
1633
1633
1633
1633
-
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Z
3
4
5
6
7
8
9
0
*
#
A
B
C
D
ANY
Z : High Impedance
H : High Logic Level
L : Low Logic Level
KT3170
LOW POWER DTMF RECEIVER
APPLICATION CIRCUIT
+5V
IN+
IN-
VDD
0.1uF
100K
SI/GTO
10nF
C1
100K
IN+
1
2
100K
300K
+
_
GS
ESO
DSO
R1
IN-
VREF
GS
IIN
Q4
Q3
10nF
C2
100K
R2
R5
100K
3
4
PDN
R3
37.5K
R2
60K
3.58MHz
OSC1
Q2
VREF
KT3170
OSC2
GND
Q1
OE
R3 = R2R5/(R2+R5), VOLTAGE GAIN = R5/R1
INPUT IMPEDANCE : 2
2
+ (1/wC)2
ÖR1
All resistors are 1% tolerance
All capacitors are 5% tolerance
All resistors are 1% tolerance
All capacitors are 5% tolerance
Fig. 4 Single Ended Input Configuration
Fig. 5 Differential Ended Input Configuration
V
D D
C
C
S I / G T O
S I / G T O
R 1
R 1
R 2
R 2
E S O
E S O
tPGT = (R1C) In (VDD/VDD-VTH
)
tPGT = (RPC) In (VDD/VDD-VTH)
tAGT = (RPC) In (VDD/VTST
RP = R1R2/(R1 + R2)
)
tAGT = (R1C) In (VDD/VTH
RP = R1R2 (R1 + R2)
)
(a) Decreasing tAGT (tPGT > tAGT
)
(a) Decreasing tPGT (tPGT< tAGT)
Fig. 6 Guard Time Adjustment
K T 3 1 7 0
K T 3 1 7 0
3 0 p F
O S C 1
O S C 2
O S C 1
O S C 2
3 . 5 7 9 5 4 5 M H z
T O O S C 1 o f n ex t K T 3 1 7 0
Fig. 7 Oscillator Connection
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