M312L2820EG0-CB3 [SAMSUNG]
DDR DRAM Module, 128MX72, 0.7ns, CMOS, DIMM-184;型号: | M312L2820EG0-CB3 |
厂家: | SAMSUNG |
描述: | DDR DRAM Module, 128MX72, 0.7ns, CMOS, DIMM-184 动态存储器 双倍数据速率 |
文件: | 总30页 (文件大小:712K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
DDR SDRAM Registered Module
184pin Registered Module based on 256Mb E-die
with 72-bit ECC
66 TSOP-II and 60 ball FBGA
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
Table of Contents
1.0 Ordering Information................................................................................................................... 4
2.0 Operating Frequencies................................................................................................................ 4
3.0 Feature.......................................................................................................................................... 4
4.0 Pin Configuration (Front side/back side) ................................................................................. 5
5.0 Pin Description ............................................................................................................................ 5
6.0 Functional Block Diagram .......................................................................................................... 6
6.1 256MB, 32M x 72 ECC Module (M312L3223ET(U)S)........................................................................... 6
6.2 512MB, 64M x 72 ECC Module (M312L6423ET(U)S).......................................................................... 7
6.3 512MB, 64M x 72 ECC Module (M312L6420ET(U)S).......................................................................... 8
6.4 1GB, 128M x 72 ECC Module (M312L2828ET(U)0) ............................................................................ 9
6.5 256MB, 32M x 72 ECC Module (M312L3223EG(Z)0)....................................................................................... 10
6.6 512MB, 64M x 72 ECC Module (M312L6423EG(Z)0) ........................................................................ 11
6.7 512MB, 64M x 72 ECC Module (M312L6420EG(Z)0)....................................................................................... 12
6.8 1GB, 128M x 72 ECC Module (M312L2820EG(Z)0)......................................................................................... 13
7.0 Absolute Maximum Ratings...................................................................................................... 14
8.0 Power & DC Operating Conditions (SSTL_2 In/Out) .............................................................. 14
9.0 DDR SDRAM IDD spec table..................................................................................................... 15
9.1 M312L3223ET(U)S [ (32M x 8) * 9 , 256MB Module ]........................................................................ 15
9.2 M312L6423ET(U)S [ (32M x 8) * 18 , 512MB Module ]....................................................................... 15
9.3 M312L6420ET(U)S [ (64M x 4) * 18 , 512MB Module ] ..................................................................................... 16
9.4 M312L2828ET(U)0 [ (st.128M x 4) * 18 , 1GB Module ]..................................................................... 16
9.5 M312L3223EG(Z)0 [ (32M x 8) * 9 , 256MB Module ]....................................................................................... 17
9.6 M312L6423EG(Z)0 [ (32M x 8) * 18 , 512MB Module ] ...................................................................... 17
9.7 M312L6420EG(Z)0 [ (64M x 4) * 18 , 512MB Module ] ....................................................................... 18
9.8 M312L2820EG(Z)0 [ (64M x 4) * 36, 1GB Module ] ........................................................................... 18
10.0 AC Operating Conditions........................................................................................................ 19
11.0 Input/Output Capacitance....................................................................................................... 19
12.0 AC Timming Parameters & Specifications............................................................................ 20
13.0 System Characteristics for DDR SDRAM .............................................................................. 21
14.0 Component Notes.................................................................................................................... 22
15.0 System Notes........................................................................................................................... 23
16.0 Command Truth Table............................................................................................................. 24
17.0 Physical Dimensions............................................................................................................... 25
17.1 32M x 72 (M312L3223ET(U)S) .................................................................................................... 25
17.2 64M x 72 (M312L6423ET(U)S), (M312L6420ET(U)S) ...................................................................... 26
17.3 st.128M x 72 (M312L2828ET(U)0) ............................................................................................... 27
17.4 32M x 72 (M312L3223EG(Z)0) .................................................................................................... 28
17.5 64M x 72 (M312L6423EG(Z)0), (M312L6420EG(Z)0)....................................................................... 29
17.6 128M x 72 (M312L2820EG(Z)0)................................................................................................... 30
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
Revision History
Revision
Month
Year
History
1.0
July
2005
- Merged TSOP and FBGA based RDIMM, Deleted 1.7” Height DIMM
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
184Pin Registered DIMM based on 256Mb E-die (x4, x8)
1.0 Ordering Information
Part Number
Density
256MB
512MB
512MB
1GB
256MB
512MB
512MB
1GB
Organization
32M x 72
64M x 72
64M x 72
128M x 72
32Mx72
64M x 72
64M x 72
128M x 72
Component Composition
Height
1,200mil
1,200mil
1,200mil
1,200mil
1,125mil
1,125mil
1,125mil
1,200mil
M312L3223ET(U)S-CA2/B0
M312L6423ET(U)S-CA2/B0
M312L6420ET(U)S-CA2/B0
M312L2828ET(U)0-CA2/B0
M312L3223EG(Z)0-CCC/B3
M312L6423EG(Z)0-CCC/B3
M312L6420EG(Z)0-CCC/B3
M312L2820EG(Z)0-CCC/B3
32Mx8( K4H560838E) * 9EA
32Mx8( K4H560838E) * 18EA
64Mx4( K4H560438E) * 18EA
st.128Mx4( K4H510638E) * 18EA
32Mx8( K4H560838E) * 9EA
32Mx8( K4H560838E) * 18EA
64Mx4( K4H560438E) * 18EA
64Mx4( K4H560438E) * 36EA
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N
(T : 66 TSOP with Leaded, U : 66 TSOP with Lead-free)
(G : 60 FBGA with Leaded, Z : 60 FBGA with Lead-free)
2.0 Operating Frequencies
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
133MHz
166MHz
-
133MHz
133MHz
-
100MHz
133MHz
-
166MHz
200MHz
3-3-3
2.5-3-3
2-3-3
2.5-3-3
3.0 Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• SSTL_2 Interface
• 66pin TSOP II and 60 ball FBGA Leaded & Pb-Free(RoHS compliant) package
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
4.0 Pin Configuration (Front side/back side)
Pin
1
Front
VREF
DQ0
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Front
A5
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
WE
Pin
93
Back
VSS
DQ4
Pin
124
125
126
127
128
Back
VSS
A6
DQ28
DQ29
VDDQ
Pin
154
155
156
157
158
Back
RAS
DQ45
VDDQ
CS0
2
3
4
5
6
7
8
9
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
DQS8
A0
94
95
96
97
98
99
100
101
102
103
104
105
106
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
RESET
VSS
DQ8
DQ41
CAS
VSS
DQ5
VDDQ
DM0/DQS9
DQ6
CS1
DQS5
DQ42
DQ43
VDD
*CS2
DQ48
DQ49
VSS
*CK2
*CK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
129 DM3/DQS12 159 DM5/DQS14
DQ7
VSS
NC
NC
130
131
132
133
134
135
136
137
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
160
161
162
163
164
165
166
167
168
VSS
DQ46
DQ47
*CS3
VDDQ
DQ52
DQ53
*A13
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NC
VDDQ
DQ12
DQ13
DQ9
DQS1
VDDQ
*CK1
*CK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
107 DM1/DQS10 138
CK0
VSS
VDD
108
109
110
111
112
113
114
115
116
117
118
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
139
169 DM6/DQS15
140 DM8/DQS17 170
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
CB2
VSS
CB3
BA1
141
142
143
144
A10
CB6
VDDQ
CB7
171
172
173
174
175
176
KEY
KEY
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
145
146
147
148
VSS
DQ36
DQ37
VDD
VSS
DQ21
A11
177 DM7/DQS16
178
179
DQS7
DQ58
DQ59
VSS
NC
SDA
DQ62
DQ63
VDDQ
SA0
SA1
SA2
A9
DQ18
A7
VDDQ
DQ19
119 DM2/DQS11 149 DM4/DQS13 180
120
121
122
123
VDD
DQ22
A8
150
151
152
153
DQ38
DQ39
VSS
181
182
183
184
SCL
DQ23
DQ44
VDDSPD
Note :
1. * : These pins are not used in this module.
2. Pins 111, 158 are NC for 1row module & used for 2row module.
3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).
5.0 Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
DM0 ~ DM8 Data - in mask
Power supply
BA0 ~ BA1A
DQ0 ~ DQ63
Bank Select Address
Data input/output
VDD
(2.5V for DDR266/333, 2.6V for DDR400)
Power Supply for DQS
(2.5V for DDR266/333, 2.6V for DDR400)
VDDQ
DQS0 ~ DQS17
CK0,CK0 ~ CK2, CK2
CKE0, CKE1(for double banks) Clock enable input
CS0, CS1(for double banks)
Data Strobe input/output
Clock input
VSS
VREF
VDDSPD
SDA
Ground
Power supply for reference
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
Chip select input
RAS
CAS
WE
CB0 ~ CB7
Row address strobe
Column address strobe
Write enable
SCL
Serial clock
SA0 ~ 2
VDDID
NC
Address in EEPROM
VDD, VDDQ level detection
No connection
Check bit(Data-in/data-out)
Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ)
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
6.0 Functional Block Diagram
6.1 256MB, 32M x 72 ECC Module (M312L3223ET(U)S)
(Populated as 1 bank of x8 DDR SDRAM Module)
RCS0
DQS0
DM0
DQS4
DM4
DM/
CS DQS
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
D0
D4
DQS1
DM1
DQS5
DM5
DM/
CS DQS
DM/
CS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 7
I/O 4
I/O 2
I/O 0
I/O 6
I/O 5
I/O 3
I/O 1
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS6
DM6
DM/
CS DQS
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 6
I/O 5
I/O 3
I/O 1
I/O 7
I/O 4
I/O 2
I/O 0
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
D2
D6
DQS3
DM3
DQS7
DM7
DM/
CS DQS
DM/
CS DQS
Serial PD
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 2
I/O 5
I/O 6
I/O 1
I/O 3
I/O 4
I/O 7
I/O 6
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 3
I/O 1
SCL
WP
D3
D7
SDA
A2
A0
A1
SA0 SA1 SA2
DQS8
DM8
V
SPD
DDSPD
DM/
CS DQS
D0 - D8
D0 - D8
V
/V
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 5
I/O 4
I/O 2
I/O 0
I/O 7
I/O 6
I/O 3
I/O 1
DD DDQ
D8
D0 - D8
VREF
D0 - D8
V
SS
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
RCS0
CS0
R
E
G
I
Notes:
BA0 -BA1 : SDRAMs DQ0 - D8
RBA0 - RBA1
RA0 - RA12
RRAS
BA0-BA1
A0-A12
RAS
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
A0 -A12 : SDRAMs D0 - D8
RAS : SDRAMs D0 - D8
CAS : SDRAMs D0 - D8
CKE : SDRAMs D0 - D8
WE: SDRAMs D0 - D8
S
T
E
R
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
RCAS
CAS
CKE0
WE
RCKE0
RWE
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
PCK
PCK
RESET
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
6.2 512MB, 64M x 72 ECC Module (M312L6423ET(U)S)
(Populated as 2 bank of x8 DDR SDRAM Module)
RCS1
RCS0
DQS0
DM0
DQS4
DM4
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 7
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
D9
D4
D13
D0
DQS1
DM1
DQS5
DM5
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
I/O 7
I/O 4
I/O 2
I/O 0
I/O 6
I/O 5
I/O 3
I/O 1
I/O 0
I/O 3
I/O 5
I/O 7
I/O 1
I/O 2
I/O 4
I/O 6
DQ9
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS6
DM6
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 6
I/O 5
I/O 3
I/O 1
I/O 7
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 2
I/O 0
I/O 6
I/O 4
I/O 3
I/O 1
I/O 1
I/O 2
I/O 4
I/O 6
I/O 0
I/O 3
I/O 5
I/O 7
I/O 0
I/O 2
I/O 5
I/O 7
I/O 1
I/O 3
I/O 4
I/O 6
D2
D11
D15
D6
DQS3
DM3
DQS7
DM7
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 5
I/O 2
I/O 1
I/O 6
I/O 4
I/O 3
I/O 0
I/O 6
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 3
I/O 1
I/O 0
I/O 2
I/O 5
I/O 6
I/O 1
I/O 3
I/O 4
I/O 7
I/O 1
I/O 3
I/O 5
I/O 7
I/O 0
I/O 2
I/O 4
I/O 6
D3
D7
D12
D16
DQS8
DM8
DM/
CS DQS
DM/
CS DQS
I/O 5
I/O 4
I/O 2
I/O 0
I/O 7
I/O 6
I/O 3
I/O 1
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 2
I/O 3
I/O 5
I/O 7
I/O 0
I/O 1
I/O 4
I/O 6
D8
D17
V
V
SPD
DDSPD
Serial PD
SCL
WP
D0 - D17
D0 - D17
/V
DD DDQ
SDA
A0
A1
A2
D0 - D17
VREF
SA0 SA1 SA2
D0 - D17
V
SS
RCS0
CS0
CS1
R
E
G
I
S
T
E
R
PLL*
* Wire per Clock Loading table/wiring Diagrams
CK0,CK0
RCS1
BA0 -BA1 : SDRAMs DQ0 - D17
A0 -A12 : SDRAMs D0 - D17
RAS : SDRAMs D0 - D17
CAS : SDRAMs DQ0 - D17
CKE : SDRAMs D0 - D8
CKE : SDRAMs D9 - D17
RBA0 - RBA1
BA0-BA1
RA0 - RA12
RRAS
A0-A12
Notes:
RAS
CAS
CKE0
CKE1
WE
RCAS
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
RCKE0
RCKE1
RWE
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
WE: SDRAMs D0 - D17
PCK
PCK
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RESET
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
6.3 512MB, 64M x 72 ECC Module (M312L6420ET(U)S)
(Populated as 1 bank of x4 DDR SDRAM Module)
VSS
RCS0
DQS0
DQS9
(DM0)
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
CS
CS
I/O 0
DQ0
DQ1
DQ2
DQ3
I/O 3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 2
I/O 1
I/O 0
D9
D0
DQS1
DQS10
(DM1)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ8
DQ12
DQ13
DQ14
DQ15
DQ9
D10
D1
DQ10
DQ11
DQS11
(DM2)
DQS2
DQS3
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
D11
D2
DQS12
(DM3)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
D12
D3
DQS13
(DM4)
DQS4
DQS5
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 3
I/O 2
I/O 1
I/O 0
DQ32
DQ33
DQ34
DQ35
D13
D4
DQS14
(DM5)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
D14
D5
DQS15
(DM6)
DQS6
DQS
DQS
CS
Serial PD
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
SCL
WP
D15
D6
SDA
A2
A0
A1
DQS7
DQS8
DQS16
(DM7)
DQS
DQS
CS
CS
SA0 SA1 SA2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D16
D7
V
DDSPD
SPD
DQS17
(DM8)
V
/V
DD DDQ
D0 - D17
D0 - D17
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
I/O 3
I/O 2
I/O 1
I/O 0
CB0
CB1
CB2
CB3
D17
D8
VREF
D0 - D17
D0 - D17
V
SS
Strap: see Note 4
PLL*
CK0,CK0
RS0
S0
R
E
G
I
S
T
E
R
* Wire per Clock Loading table/wiring Diagrams
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
BA0-BA1
A0-A12
RAS
CAS
CKE0
WE
BA0 -BA1 : SDRAMs DQ0 - D17
A0 -A12 : SDRAMs D0 - D17
RAS : SDRAMs D0 - D17
CAS : SDRAMs DQ0 - D17
CKE : SDRAMs D0 - D17
WE: SDRAMs D0 - D17
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
RWE
3. DQ, DQS, DM resistors: 22 Ohms.
PCK
PCK
RESET
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
6.4 1GB, 128M x 72 ECC Module (M312L2828ET(U)0)
(Populated as 2 bank of x4 DDR SDRAM Module)
V
SS
RCS1
RCS0
DQS0
DM0/DQS9
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
CS
CS
CS
CS
DQ0
DQ1
DQ2
DQ3
I/O 3
I/O 3
I/O 0
I/O 0
DQ4
DQ5
DQ6
DQ7
I/O 2
I/O 1
I/O 0
I/O 2
I/O 1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D18
D9
D27
DQS1
DQS2
DQS3
DM1/DQS10
DM2/DQS11
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ8
DQ12
DQ13
DQ14
DQ15
DQ9
D1
D19
D10
D28
DQ10
DQ11
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
D2
D20
D11
D29
DM3/DQS12
DM4/DQS13
DM5/DQS14
DM6/DQS15
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
D3
D21
D12
D30
DQS4
DQS5
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ32
DQ33
DQ34
DQ35
D4
D22
D13
D31
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ40
DQ41
DQ42
DQ43
D5
D23
D14
D32
DQS6
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
D24
D15
D33
DQS7
DQS8
DM7/DQS16
DM8/DQS17
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
D25
D16
D34
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
CB0
CB1
CB2
CB3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
CB4
CB5
CB6
CB7
D8
D26
D35
D17
V
DDSPD
SPD
Serial PD
V
/V
DD DDQ
D0 - D35
D0 - D35
SCL
WP
SDA
A0
A1
A2
VREF
D0 - D35
D0 - D35
PLL
CK0,CK0
V
SS
SA0 SA1 SA2
CS0
RCS0
R
E
G
I
CS1
RCS1
Notes:
RBA0 - RBA1
RA0 - RA12
BA0-BAn: SDRAMs D0 - D35
A0-An: SDRAMs D0 - D35
BA0-BA1
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
A0-A12
S
T
E
R
RRAS
RAS: SDRAMs D0 - D35
RAS
CAS
CKE0
CKE1
WE
RCAS
RCKE0
RCKE1
CAS: SDRAMs D0 - D35
CKE: SDRAMs D0 - D17
CKE: SDRAMs D18 - D35
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RWE
WE: SDRAMs D0 - D35
PCK
PCK
RESET
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
6.5 256MB, 32M x 72 ECC Module (M312L3223EG(Z)0)
(Populated as 1 bank of x8 DDR SDRAM Module)
RCS0
DQS0
DM0
DQS4
DM4
DM
I/O 7
CS
DQS
DQS
CS
DM
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 2
I/O 4
I/O 7
I/O 3
I/O 1
I/O 6
I/O 5
D4
D0
DQS5
DM5
DQS1
DM1
DQS
DM
CS
DQS
CS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 0
I/O 2
I/O 4
I/O 7
I/O 3
I/O 1
I/O 6
I/O 5
DQ8
DQ9
D5
D1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS6
DM6
DQS2
DM2
DM
CS DQS
CS DQS
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D6
D2
DQS7
DM7
DQS3
DM3
CS
DM
DQS
CS
DQS
DM
I/O 0
I/O 2
I/O 4
I/O 7
I/O 3
I/O 1
I/O 6
I/O 5
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D7
D3
DQS8
DM8
V
DDSPD
SPD
V
/V
DDR SDRAMs D0 - D8
DD DDQ
DM
CS
DQS
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D8
VREF
DDR SDRAMs D0 - D8
DDR SDRAMs D0 - D8
V
SS
Serial PD
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
SCL
WP
SDA
A0
A1
A2
SA0 SA1
SA2
RCS0
CS0
R
BA0 -BA1 : DDR SDRAMs D0 - D8
A0 -A12 : DDR SDRAMs D0 - D8
RAS : DDR SDRAMs D0 - D8
CAS : DDR SDRAMs D0 - D8
CKE : DDR SDRAMs D0 - D8
WE: DDR SDRAMs D0 - D8
E
G
I
RBA0 - RBA1
RA0 - RA12
RRAS
BA0-BA1
A0-A12
RAS
S
T
E
R
RCAS
CAS
CKE0
WE
RCKE0
RWE
PCK
PCK
RESET
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
6.6 512MB, 64M x 72 ECC Module (M312L6423EG(Z)0)
(Populated as 2 bank of x8 DDR SDRAM Module)
RCS1
RCS0
DQS0
DM0
DQS4
DM4
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
D9
D4
D13
D0
DQS1
DM1
DQS5
DM5
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
DQ9
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS6
DM6
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
D2
D11
D15
D6
DQS3
DM3
DQS7
DM7
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
D3
D7
D12
D16
DQS8
DM8
DM/
CS DQS
DM/
CS DQS
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D8
D17
V
V
SPD
DDSPD
Serial PD
SCL
WP
D0 - D17
D0 - D17
/V
DD DDQ
SDA
A0
A1
A2
D0 - D17
VREF
SA0 SA1 SA2
D0 - D17
V
SS
RCS0
CS0
CS1
R
E
G
I
S
T
E
R
PLL*
* Wire per Clock Loading table/wiring Diagrams
CK0,CK0
RCS1
RBA0 - RBA1
BA0 -BA1 : DDR SDRAM DQ0 - D17
A0 -A12 : DDR SDRAM D0 - D17
RAS : DDR SDRAM D0 - D17
CAS : DDR SDRAM DQ0 - D17
CKE : DDR SDRAM D0 - D8
CKE : DDR SDRAM D9 - D17
WE: DDR SDRAM D0 - D17
BA0-BA1
RA0 - RA12
RRAS
A0-A12
Notes:
RAS
CAS
CKE0
CKE1
WE
RCAS
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
RCKE0
RCKE1
RWE
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
PCK
PCK
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RESET
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
6.7 512MB, 64M x 72 ECC Module (M312L6420EG(Z)0)
(Populated as 1 bank of x4 DDR SDRAM Module)
VSS
RCS0
DQS0
DQS9
(DM0)
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
CS
CS
I/O 0
DQ0
DQ1
DQ2
DQ3
I/O 3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 2
I/O 1
I/O 0
D9
D0
DQS1
DQS10
(DM1)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ8
DQ12
DQ13
DQ14
DQ15
DQ9
D10
D1
DQ10
DQ11
DQS11
(DM2)
DQS2
DQS3
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
D11
D2
DQS12
(DM3)
DQS
DQS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
D12
D3
DQS13
(DM4)
DQS4
DQS5
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 3
I/O 2
I/O 1
I/O 0
DQ32
DQ33
DQ34
DQ35
D13
D4
DQS14
(DM5)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
D14
D5
DQS15
(DM6)
DQS6
DQS
DQS
CS
Serial PD
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
SCL
WP
D15
D6
SDA
A2
A0
A1
DQS7
DQS8
DQS16
(DM7)
DQS
DQS
CS
CS
SA0 SA1 SA2
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D16
D7
V
DDSPD
SPD
DQS17
(DM8)
V
/V
DD DDQ
D0 - D17
D0 - D17
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
I/O 3
I/O 2
I/O 1
I/O 0
CB0
CB1
CB2
CB3
D17
D8
VREF
D0 - D17
D0 - D17
V
SS
PLL*
CK0,CK0
RCS0_1
RCS0_2
CS0
R
E
G
I
S
T
E
R
* Wire per Clock Loading table/wiring Diagrams
RBA0 - RBA1
RA0 - RA12
RRAS
BA0 -BA1 : DDR SDRAM DQ0 - D17
A0 -A12 :DDR SDRAM D0 - D17
RAS : DDR SDRAM D0 - D17
CAS : DDR SDRAM DQ0 - D17
CKE : DDR SDRAM D0 - D8
CKE : DDR SDRAM D9 - D17
BA0-BA1
A0-A12
RAS
CAS
CKE0
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
RCAS
RCKE0A
RCKE0B
RWE
WE
WE:DDR SDRAM D0 - D17
3. DQ, DQS, DM resistors: 22 Ohms.
PCK
PCK
RESET
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
6.8 1GB, 128M x 72 ECC Module (M312L2820EG(Z)0)
(Populated as 2 bank of x4 DDR SDRAM Module)
V
SS
RCS1
RCS0
DQS0
DQS9
(DM0)
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
DM
DM
DM
DM
DM
DM
DM
DM
DM
CS
CS
CS
CS
DQ0
DQ1
DQ2
DQ3
I/O 0
I/O 3
I/O 0
I/O 3
DQ4
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 2
I/O 1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 2
I/O 1
I/O 0
D0
D18
D9
D27
DQS1
DQS2
DQS3
DQS10
(DM1)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ8
DQ12
DQ13
DQ14
DQ15
DQ9
D1
D19
D10
D28
DQ10
DQ11
DQS11
(DM2)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
DQ16
DQ17
DQ18
DQ19
D2
D20
D11
D29
DQS12
(DM3)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ28
DQ29
DQ30
DQ31
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
D3
D21
D12
D30
DQS13
(DM4)
DQS4
DQS5
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ32
DQ33
DQ34
DQ35
D4
D22
D13
D31
DQS14
(DM5)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
D5
D23
D14
D32
DQS15
(DM6)
DQS6
DQS7
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
D24
D15
D33
DQS16
(DM7)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
D25
D16
D34
DQS17
(DM8)
DQS8
DQS
CS
DQS
CS
DQS
DM
DQS
DM
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
D17
D35
D8
D26
V
DDSPD
SPD
Serial PD
V
/V
DD DDQ
D0 - D35
D0 - D35
SCL
WP
SDA
A0
A1
A2
VREF
D0 - D35
D0 - D35
V
SA0 SA1 SA2
SS
CS0
RCS0
R
E
G
I
CS1
RCS1
PLL*
CK0,CK0
RBA0 - RBA1
RA0 - RA12
BA0-BA1: DDR SDRAM D0 - D35
A0-A12: DDR SDRAM D0 - D35
BA0-BA1
* Wire per Clock Loading table/wiring Diagrams
A0-A12
S
T
E
R
RRAS
RAS: DDR SDRAM D0 - D35
RAS
CAS
CKE0
CKE1
WE
Notes:
RCAS
RCKE0
RCKE1
CAS: DDR SDRAM D0 - D35
CKE: DDR SDRAM D0 - D17
CKE: DDR SDRAM D18 - D35
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RWE
WE: DDR SDRAM D0 - D35
PCK
PCK
RESET
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
7.0 Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD,VDDQ
TSTG
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
Unit
V
V
°C
W
mA
-55 ~ +150
1.5 * # of component
50
Power dissipation
Short circuit current
PD
IOS
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
8.0 Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit Note
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
VDD
2.3
2.7
V
Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
VDD
2.5
2.7
2.7
2.7
V
V
V
V
V
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
I/O Reference voltage
VDDQ
VDDQ
VREF
VTT
2.3
2.5
0.49*VDDQ
VREF-0.04
0.51*VDDQ
VREF+0.04
1
2
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VI(Ratio)
II
VREF+0.15
-0.3
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.4
V
V
V
V
-0.3
0.36
0.71
-2
3
4
-
2
5
uA
uA
mA
Output leakage current
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOZ
-5
IOH
-16.8
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
IOH
IOL
16.8
-9
mA
mA
mA
9
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may
not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track
variations in the DC level of VREF.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,
for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers
due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to
source voltages from 0.1 to 1.0.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
9.0 DDR SDRAM IDD spec table
9.1 M312L3223ET(U)S [ (32M x 8) * 9 , 256MB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
IDD1
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1,350
1,570
360
810
490
1,350
1,570
360
810
490
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
600
600
1,030
1,890
1,840
2,070
360
1,030
1,890
1,840
2,070
360
IDD6
Normal
Low power
IDD7A
340
2,250
340
2,250
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
9.2 M312L6423ET(U)S [ (32M x 8) * 18 , 512MB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
IDD1
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Unit
Notes
1,880
2,100
510
1,110
780
1,880
2,100
510
1,110
780
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
990
990
1,560
2,420
2,370
2,600
510
1,560
2,420
2,370
2,600
510
IDD6
Normal
Low power
IDD7A
480
3,410
480
3,410
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
9.3 M312L6420ET(U)S [ (64M x 4) * 18 , 512MB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
IDD1
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
2,070
2,430
380
990
650
2,070
2,430
380
990
650
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
870
870
1,440
2,790
3,060
3,510
379
1,440
2,790
3,060
3,510
379
IDD6
Normal
Low power
IDD7A
352
4,950
352
4,950
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
9.4 M312L2828ET(U)0 [ (st.128M x 4) * 18 , 1GB Module ]
(VDD=2.7V, T = 10°C)
Unit Notes
Symbol
IDD0
A2(DDR266@CL=2)
3,000
B0(DDR266@CL=2.5)
3,000
3,360
558
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
3,360
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
558
1,470
1,100
1,530
2,370
3,720
3,990
4,440
1,470
1,100
1,530
2,370
3,720
3,990
4,440
558
IDD6
Normal
Low power
IDD7A
558
504
5,880
504
5,880
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
9.5 M312L3223EG(Z)0 [ (32M x 8) * 9 , 256MB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
IDD1
CC (DDR400@CL=3)
B3 (DDR333@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1,650
1,880
420
1,020
600
1,560
1,790
410
980
560
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
870
700
1,430
2,370
2,460
2,420
410
1,250
2,190
2,190
2,280
410
IDD6
Normal
Low power
IDD7A
390
3,450
390
3,270
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
9.6 M312L6423EG(Z)0 [ (32M x 8) * 18 , 512MB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
IDD1
CC (DDR400@CL=3)
B3 (DDR333@CL=2.5)
Unit
Notes
2,450
2,680
580
1,420
950
1,490
2,230
3,170
3,260
3,220
560
2,180
2,410
560
1,330
860
1,130
1,870
2,810
2,810
2,900
560
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
Normal
Low power
IDD7A
530
4,250
530
3,890
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
9.7 M312L6420EG(Z)0 [ (64M x 4) * 18 , 512MB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
IDD1
CC (DDR400@CL=3)
B3 (DDR333@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
2,250
3,000
450
1,290
830
1,370
2,100
3,630
4,170
4,080
430
2,370
2,730
430
1,200
740
1,010
1,740
3,270
3,630
3,810
430
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
Normal
Low power
IDD7A
410
5,790
410
5,430
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
9.8 M312L2820EG(Z)0 [ (64M x 4) * 36, 1GB Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
IDD1
CC (DDR400@CL=3)
B3 (DDR333@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
4,150
4,600
770
3,490
3,850
610
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
2,080
1,530
2,610
3,700
5,230
5,770
5,680
740
1,780
1,220
1,760
2,860
4,390
4,750
4,930
610
IDD6
Normal
Low power
IDD7A
680
7,390
560
6,550
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
10.0 AC Operating Conditions
Parameter/Condition
Symbol
Min
VREF + 0.31
Max
Unit
V
V
V
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VREF - 0.31
VDDQ+0.6
0.7
1
2
VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
CLOAD=30pF
VREF
=0.5*VDDQ
Output Load Circuit (SSTL_2)
11.0 Input/Output Capacitance
(TA= 25°C, f=100MHz)
M312L3223ET(U), M312L6420ET(U)
M312L6423ET(U) M312L2820ET(U)
Parameter
Symbol
Unit
Min
9
Max
11
11
11
12
11
11
11
Min
9
9
Max
11
11
11
12
16
16
16
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1
Input capacitance(CKE0)
Input capacitance( CS0)
Input capacitance( CLK0, CLK0 )
Input capacitance(DM0~DM8)
pF
pF
pF
pF
pF
pF
pF
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
9
9
9
11
10
10
10
11
14
14
14
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
M312L3223EG(Z), M312L6420EG(Z) M312L6423EG(Z), M312L2820EG(Z)
Parameter
Symbol
Unit
Min
9
Max
11
11
11
12
11
11
11
Min
9
Max
11
11
11
12
15
15
15
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1
Input capacitance(CKE0)
Input capacitance( CS0)
Input capacitance( CLK0, CLK0 )
Input capacitance(DM0~DM8)
pF
pF
pF
pF
pF
pF
pF
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
9
9
9
9
11
10
10
10
11
13
13
13
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
12.0 AC Timming Parameters & Specifications
CC
B3
A2
B0
(DDR400@CL=3.0) (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.5)
Parameter
Symbol
Unit Note
Min
55
Max
Min
60
Max
Min
65
75
45
20
Max
Min
65
75
45
20
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
Refresh row cycle time
Row active time
RAS to CAS delay
70
72
40
70K
42
70K
70K
70K
15
18
Row precharge time
15
18
20
20
Row active to Row active delay
Write recovery time
Last data in to Read command
tRRD
tWR
tWTR
10
15
2
-
6
5
12
15
1
7.5
6
15
15
1
7.5
7.5
-
15
15
1
10
7.5
-
CL=2.0
CL=2.5
CL=3.0
-
12
10
12
12
-
12
12
-
12
12
-
Clock cycle time
tCK
-
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tCH
tCL
tDQSCK
tAC
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.7
0.7
-0.65
-0.65
10
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
0.8
-0.7
-0.7
12
0.55
0.55
+0.6
+0.7
0.45
1.1
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
1.0
1.0
-0.75
-0.75
15
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
1.0
1.0
-0.75
-0.75
15
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
tCK
tCK
ns
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
tIS
tIH
tHZ
tLZ
tMRD
tDS
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
22
13
0.6
1.25
DQS-in low level width
15, 17~19
15, 17~19
16~19
16~19
11
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
+0.65
+0.65
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
11
DQ & DM setup time to DQS
0.4
0.45
0.5
0.5
j, k
j, k
ns
DQ & DM hold time to DQS
tDH
0.4
0.45
0.5
0.5
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
tIPW
tDIPW
tXSNR
tXSRD
tREFI
2.2
1.75
75
2.2
1.75
75
2.2
1.75
75
2.2
1.75
75
ns
ns
ns
tCK
us
18
18
200
200
200
200
7.8
7.8
7.8
7.8
-
14
21
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
ns
ns
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
-
20, 21
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
tQHS
tWPST
0.5
0.6
0.55
0.6
0.75
0.6
0.75
0.6
ns
tCK
21
12
0.4
15
0.4
18
0.4
20
0.4
20
tRAP
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Autoprecharge write recovery +
Precharge time
tDAL
tCK
23
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
13.0 System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system
performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR333
DDR266
DDR200
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
Units
Notes
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
DCSLEW
TBD
TBD
TBD
TBD
0.5
4.0
V/ns
a, l
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
∆tIS
∆tIH
Units
Notes
0.5 V/ns
0
0
0
0
ps
i
i
i
0.4 V/ns
+50
+100
ps
0.3 V/ns
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
∆tDS
∆tDH
Units
Notes
0.5 V/ns
0
0
ps
k
k
k
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
∆tDS
∆tDH
Units
Notes
+/- 0.0 V/ns
0
0
ps
j
j
j
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Typical Range
Minimum
Maximum
Slew Rate Characteristic
Notes
(V/ns)
(V/ns)
(V/ns)
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g,h
b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
Minimum
Maximum
Slew Rate Characteristic
Notes
(V/ns)
(V/ns)
(V/ns)
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g,h
b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS
DDR266B
DDR200
PARAMETER
Output Slew Rate Matching Ratio (Pullup to Pulldown)
MIN
TBD
MAX
TBD
MIN
0.67
MAX
1.5
Notes
e, l
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
14.0 Component Notes
1. All voltages referenced to Vss.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related speci-
fications and device operation are guaranteed for the full voltage range specified.
3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise rep-
resentation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions
(generally a coaxial transmission line terminated at the tester electronics).
VDDQ
50Ω
Output
(Vout)
30pF
Figure 1 : Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the cross-
ing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew
rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing
the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is recognized as LOW.
7. Enables on.chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other
than CK/CK, is VREF.
10. The output timing reference voltage level is VTT.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage
level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance
(bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is
defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will
be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this
time, depending on tDQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
17. For CK & CK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
19. Slew Rate is measured between VOH(ac) and VOL(ac).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater
than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the
clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration dis-
tortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transi-
tion, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers.
22. tDQSQ - Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
23. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15
ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
15.0 System Notes:
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.
Test point
50Ω
Output
VSSQ
Figure 2 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 3.
VDDQ
50Ω
Output
Test point
Figure 3 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range.
For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is
based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate
is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either
VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of
the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or
VIH(DC) to VIL(DC), and similarly for rising transitions.
l. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC
region must be monotonic.
m. In case of Registered DIMM, device operation defines Power up and Power Management.
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption
during low power mode. One feature is externally controlled via a system-generated RESET signal; the second is based on module detection of the
input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-
Refresh mode. device operation describes this more detailly.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
16.0 Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
A0 ~ A9
Note
COMMAND
CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP
A11, A12
Register
Register
Extended MRS
Mode Register Set
Auto Refresh
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
3
3
H
L
L
L
H
X
X
Entry
Refresh
Self
Refresh
L
H
H
X
H
X
H
X
Exit
L
H
H
H
X
X
3
Row Address
(A0~A9, A11,A12)
Bank Active & Row Addr.
L
L
H
H
V
V
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
4
4, 6
7
Read &
Column Address
Column
Address
L
H
L
H
Write &
Column Address
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
Burst Stop
X
Bank Selection
All Banks
V
X
L
H
Precharge
X
5
H
L
X
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
L
H
L
Active Power Down
X
X
Exit
Entry
H
Precharge Power Down Mode
DM
H
L
Exit
L
H
H
H
X
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note :
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
17.0 Physical Dimensions
17.1 32M x 72 (M312L3223ET(U)S)
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.171
(131.350)
5.077
(128.950)
REG
0.0787
R (2.00)
PLL
0.78
(19.80)
A
A
B
B
2.500 +0.1/-0.0
M
0.10
C B A
0.157 Max
(3.99 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00 Min)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
Detail A
0.071
(1.80)
0.050
0.1575 ± 0.004
(4.00 ± 0.1)
(1.270)
C
0.10
B
AM
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 32Mx8 DDR SDRAM, TSOPII
SDRAM Part No : K4H560838E
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
17.2 64Mx72 (M312L6423ET(U)S), 64Mx72 (M312L6420ET(U)S)
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.171
(131.350)
5.077
(128.950)
REG
0.0787
R (2.00)
PLL
0.78
(19.80)
A
A
B
B
2.500 +0.1/-0.0
M
0.10
C B A
0.157 Max
(3.99 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00 Min)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
Detail A
0.071
(1.80)
0.050
0.1575 ± 0.004
(4.00 ± 0.1)
(1.270)
C
AM
0.10
B
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 32Mx8, 64Mx4 DDRSDRAM, TSOPII
SDRAM Part No. : K4H560838E, K4H560438E
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
17.3 st.128Mx72 (M312L2828ET(U)0)
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.171
(131.350)
5.077
(128.950)
0.0787
Reg.
R (2.00)
0.78
(19.80)
A
A
B
B
2.500 +0.1/-0.0
M
0.10
C B A
0.268 Max
(6.81 Max)
PLL
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00 Min)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
Detail A
0.071
(1.80)
0.050
(1.270)
0.1575 ± 0.004
(4.00 ± 0.1)
C
0.10
B
AM
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is st.128Mx4 SDRAM, 66TSOPII
SDRAM Part NO : K4H510638E
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
17.4 32Mx72 (M312L3223EG(Z)0)
Units : Millimeters
133.35 A
128.95 A
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
1
a
b
92
2.99 MAX
6.35
64.77 P2
49.53 P3
120.65 P1
184
93
6.35 X
X1
X2
2.175
4.175
D
1.0 +/-0.05
3.80 W
V
1.80
E
MAX 0.178 D1
1.27
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 32Mx8 DDR SDRAM, FBGA
DDR SDRAM Part No : K4H560838E
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
17.5 64Mx72 (M312L6423EG(Z)0), (M312L6420EG(Z)0)
Units : Millimeters
133.35 A
128.95 A
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
a
b
1
92
3.99 MAX
6.35
64.77 P2
49.53 P3
120.65 P1
93
184
6.35 X
X1
X2
2.175
4.175
D
1.0 +/-0.05
3.80 W
V
1.80
E
MAX 0.178 D1
1.27
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 32Mx8, 64Mx4 DDR SDRAM, FBGA
DDR SDRAM Part No. : K4H560838E, K4H560438E
Rev. 1.0 July 2005
256MB, 512MB, 1GB Registered DIMM
DDR SDRAM
17.6 128Mx72 (M312L2820EG(Z)0)
Units : Millimeters
133.35 A
128.95 A
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
a
b
1
92
3.99 MAX
6.35
64.77 P2
49.53 P3
120.65 P1
92
1
6.35 X
X1
X2
2.175
4.175
D
1.0 +/-0.05
3.80 W
V
1.80
E
MAX 0.178 D1
1.27
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx4 DDR SDRAM, FBGA
DDR SDRAM Part No : K4H560438E
Rev. 1.0 July 2005
相关型号:
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