M312L2923FH3-CB3 [SAMSUNG]
DDR DRAM Module, 128MX72, 0.7ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-184;型号: | M312L2923FH3-CB3 |
厂家: | SAMSUNG |
描述: | DDR DRAM Module, 128MX72, 0.7ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-184 动态存储器 双倍数据速率 |
文件: | 总24页 (文件大小:445K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
DDR SDRAM Registered Module
184pin Registered Module based on 512Mb F-die
with 72-bit ECC
66 TSOP-II and 60 ball FBGA with Lead-Free and Halogen-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.01 August 2008
1 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
Table of Contents
1.0 Ordering Information ..................................................................................................................2
2.0 Operating Frequencies ...............................................................................................................2
3.0 Feature .........................................................................................................................................2
4.0 Pin Configuration (Front side/back side) ................................................................................3
5.0 Pin Description ...........................................................................................................................3
6.0 Functional Block Diagram .........................................................................................................4
6.1 1GB, 128M x 72 ECC Module (M312L2920FLS) ...............................................................................4
6.2 512MB, 64M x 72 ECC Module (M312L6523FH3) .............................................................................5
6.3 1GB, 128M x 72 ECC Module (M312L2923FH3) ...............................................................................6
6.4 1GB, 128M x 72 ECC Module (M312L2920FH3) ...............................................................................7
6.5 2GB, 256M x 72 ECC Module (M312L5720FH3) ...............................................................................8
7.0 Absolute Maximum Ratings .......................................................................................................9
8.0 Power & DC Operating Conditions (SSTL_2 In/Out) ...............................................................9
9.0 DDR SDRAM IDD spec table ....................................................................................................10
9.1 1GB, 128M x 72 ECC Module (M312L2920FLS) ............................................................................10
9.2 512MB, 64M x 72 ECC Module (M312L6523FH3) ...........................................................................10
9.3 1GB, 128M x 72 ECC Module (M312L2923FH3) .............................................................................11
9.4 1GB, 128M x 72 ECC Module (M312L2920FH3) .............................................................................11
9.5 2GB, 256M x 72 ECC Module (M312L5720FH3) .............................................................................12
10.0 AC Operating Conditions .......................................................................................................13
11.0 Input/Output Capacitance ......................................................................................................13
12.0 AC Timming Parameters & Specifications ...........................................................................14
13.0 System Characteristics for DDR SDRAM .............................................................................15
14.0 Component Notes ...................................................................................................................16
15.0 System Notes: .........................................................................................................................17
16.0 Command Truth Table ............................................................................................................18
17.0 Physical Dimensions ..............................................................................................................19
17.1 128Mx72 (M312L2920FLS) ........................................................................................................19
17.2 64Mx72 (M312L6523FH3) ..........................................................................................................20
17.3 128Mx72 (M312L2923FH3), (M312L2920FH3) ...............................................................................21
17.4 256Mx72 (M312L5720FH3) ........................................................................................................22
Rev. 1.01 August 2008
2 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
Revision History
Revision
Month
August
August
Year
2008
2008
History
1.0
- Initial Release
- Corrected Typo
1.01
Rev. 1.01 August 2008
3 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
184Pin Registered DIMM based on 512Mb F-die (x4, x8)
1.0 Ordering Information
Part Number
M312L2920FLS-CB0
M312L6523FH3-CCC/B3
M312L2923FH3-CCC/B3
M312L2920FH3-CB3
M312L5720FH3-CB3
Note:
Density
1GB
Organization
128M x 72
64Mx72
Component Composition
Height
1,200mil
1,125mil
1,125mil
1,125mil
1,200mil
128Mx4( K4H510438F) * 18EA
64Mx8( K4H510838F) * 9EA
64Mx8( K4H510838F) * 18EA
128Mx4( K4H510438F) * 18EA
128Mx4( K4H510438F) * 36EA
512MB
1GB
128M x 72
128M x 72
256M x 72
1GB
2GB
1. “H” and “L” of Part number(11th digit) stand for Lead-Free, Halogen-Free, and RoHS compliant products.
2.0 Operating Frequencies
CC(DDR400@CL=3)
166MHz
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
166MHz
-
133MHz
-
200MHz
3-3-3
2.5-3-3
2.5-3-3
3.0 Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR266(2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• SSTL_2 Interface
• 66pin TSOP II and 60 ball FBGA package
• All of products are Lead-Free, Halogen-Free, and RoHS compliant
Rev. 1.01 August 2008
4 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
4.0 Pin Configuration (Front side/back side)
Pin
1
Front
VREF
DQ0
VSS
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Front
A5
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
VDDQ
WE
Pin
93
Back
VSS
Pin
124
125
126
127
128
Back
VSS
Pin
154
155
156
157
158
Back
RAS
DQ45
VDDQ
CS0
2
DQ24
VSS
94
DQ4
A6
3
DQ41
CAS
95
DQ5
DQ28
DQ29
VDDQ
4
DQ1
DQS0
DQ2
VDD
DQ25
DQS3
A4
96
VDDQ
DM0/DQS9
DQ6
5
VSS
97
CS1
6
DQS5
DQ42
DQ43
VDD
98
129 DM3/DQS12 159 DM5/DQS14
7
VDD
DQ26
DQ27
A2
99
DQ7
130
131
132
133
134
135
136
137
A3
DQ30
VSS
160
161
162
163
164
165
166
167
168
VSS
DQ46
DQ47
*CS3
VDDQ
DQ52
DQ53
*A13
VDD
8
DQ3
NC
100
101
102
103
104
105
106
VSS
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RESET
VSS
*CS2
DQ48
DQ49
VSS
NC
DQ31
CB4
CB5
VDDQ
CK0
CK0
VSS
VSS
NC
DQ8
DQ9
DQS1
VDDQ
*CK1
*CK1
VSS
A1
VDDQ
DQ12
DQ13
CB0
CB1
VDD
DQS8
A0
*CK2
*CK2
VDDQ
DQS6
DQ50
DQ51
VSS
107 DM1/DQS10 138
108
109
110
111
112
113
114
115
116
117
118
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
139
169 DM6/DQS15
140 DM8/DQS17 170
DQ54
DQ55
VDDQ
NC
CB2
VSS
141
142
143
144
A10
CB6
VDDQ
CB7
171
172
173
174
175
176
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
CB3
BA1
VDDID
DQ56
DQ57
VDD
DQ60
DQ61
VSS
KEY
KEY
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
145
146
147
148
VSS
DQ36
DQ37
VDD
VSS
177 DM7/DQS16
DQS7
DQ58
DQ59
VSS
DQ21
A11
178
179
DQ62
DQ63
VDDQ
SA0
A9
119 DM2/DQS11 149 DM4/DQS13 180
DQ18
A7
120
121
122
123
VDD
DQ22
A8
150
151
152
153
DQ38
DQ39
VSS
181
182
183
184
BA0
NC
SA1
VDDQ
DQ19
DQ35
DQ40
SDA
SA2
SCL
DQ23
DQ44
VDDSPD
Note :
1. * : These pins are not used in this module.
2. Pins 111, 158 are NC for 1row module & used for 2row module.
3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).
5.0 Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A12
Address input (Multiplexed)
DM0 ~ DM8 Data - in mask
Power supply
VDD
BA0 ~ BA1
Bank Select Address
Data input/output
(2.5V for DDR266/333, 2.6V for DDR400)
Power Supply for DQS
DQ0 ~ DQ63
VDDQ
(2.5V for DDR266/333, 2.6V for DDR400)
DQS0 ~ DQS17
Data Strobe input/output
Clock input
VSS
VREF
Ground
CK0,CK0
Power supply for reference
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
CKE0, CKE1(for double rank)
Clock enable input
Chip select input
VDDSPD
SDA
CS0, CS1(for double rank)
RAS
Row address strobe
Column address strobe
Write enable
SCL
Serial clock
CAS
SA0 ~ 2
VDDID
NC
Address in EEPROM
VDD, VDDQ level detection
No connection
WE
CB0 ~ CB7
Check bit(Data-in/data-out)
Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ
)
Rev. 1.01 August 2008
5 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
6.0 Functional Block Diagram
6.1 1GB, 128M x 72 ECC Module (M312L2920FLS)
(Populated as 1 rank of x4 DDR SDRAM Module)
V
SS
RCS0
DQS0
DQS9
(DM0)
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DM
DM
DM
DM
DM
DM
DM
DM
DM
CS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D9
D0
DQS1
DQS2
DQS3
DQS10
(DM1)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D10
D1
DQS11
(DM2)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
D11
D2
DQS12
(DM3)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
D12
D3
DQS13
(DM4)
DQS4
DQS5
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 3
I/O 2
I/O 1
I/O 0
DQ32
DQ33
DQ34
DQ35
D13
D4
DQS14
(DM5)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
D14
D5
DQS15
(DM6)
DQS6
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D15
D6
DQS7
DQS8
DQS16
(DM7)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D16
D7
DQS17
(DM8)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
I/O 3
I/O 2
I/O 1
I/O 0
CB0
CB1
CB2
CB3
D17
D8
RS0
S0
R
E
G
I
S
T
E
R
V
DDSPD
RBA0 - RBA1
RA0 - RA12
RRAS
BA0-BA1
A0-A12
RAS
BA0 -BA1 : SDRAMs DQ0 - D17
A0 -A12 : SDRAMs D0 - D17
RAS : SDRAMs D0 - D17
SPD
V
/V
DD DDQ
D0 - D17
D0 - D17
Serial PD
CAS
RCAS
CAS : SDRAMs DQ0 - D17
SCL
WP
V
CKE0
WE
RCKE0
CKE : SDRAMs D0 - D17
WE: SDRAMs D0 - D17
REF
SDA
D0 - D17
D0 - D17
RWE
A0
A1
A2
V
SS
PCK
PCK
RESET
SA0 SA1 SA2
PLL
CK0,CK0
Note :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
Rev. 1.01 August 2008
6 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
6.2 512MB, 64M x 72 ECC Module (M312L6523FH3)
(Populated as 1 rank of x8 DDR SDRAM Module)
RCS0
DQS0
DM0
DQS4
DM4
DM
I/O 7
CS
DQS
DQS
CS
DM
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 2
I/O 4
I/O 7
I/O 3
I/O 1
I/O 6
I/O 5
D4
D0
DQS5
DM5
DQS1
DM1
DQS
DM
CS
DQS
CS
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 0
I/O 2
I/O 4
I/O 7
I/O 3
I/O 1
I/O 6
I/O 5
DQ8
DQ9
D5
D1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS6
DM6
DQS2
DM2
DM
CS DQS
DM
CS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D6
D2
DQS7
DM7
DQS3
DM3
DM
CS DQS
DM
CS
DQS
I/O 0
I/O 2
I/O 4
I/O 7
I/O 3
I/O 1
I/O 6
I/O 5
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D7
D3
DQS8
DM8
Serial PD
DM
CS
DQS
I/O 7
I/O 5
I/O 3
I/O 0
I/O 4
I/O 6
I/O 1
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
SCL
WP
D8
SDA
A0
A1
A2
SA0 SA1 SA2
V
DDSPD
/V
SPD
V
DDR SDRAMs D0 - D8
DD DDQ
RCS0
CS0
R
V
DDR SDRAMs D0 - D8
DDR SDRAMs D0 - D8
REF
BA0 -BA1 : DDR SDRAMs D0 - D8
A0 -A12 : DDR SDRAMs D0 - D8
RAS : DDR SDRAMs D0 - D8
CAS : DDR SDRAMs D0 - D8
CKE : DDR SDRAMs D0 - D8
WE: DDR SDRAMs D0 - D8
E
G
I
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
BA0-BA1
A0-A12
RAS
CAS
CKE0
WE
V
SS
S
T
E
R
PLL
CK0,CK0
RWE
PCK
PCK
RESET
Note :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
Rev. 1.01 August 2008
7 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
6.3 1GB, 128M x 72 ECC Module (M312L2923FH3)
(Populated as 2 rank of x8 DDR SDRAM Module)
RCS1
RCS0
DQS0
DM0
DQS4
DM4
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
D9
D4
D13
D0
DQS1
DM1
DQS5
DM5
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS6
DM6
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
D2
D11
D15
D6
DQS3
DM3
DQS7
DM7
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
D3
D7
D12
D16
DQS8
DM8
Serial PD
DM/
CS DQS
DM/
CS DQS
SCL
WP
I/O 1
I/O 0
I/O 7
I/O 6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 5
I/O 4
I/O 3
I/O 2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
SDA
D8
D17
A0
A1
A2
SA0 SA1 SA2
V
SPD
DDSPD
D0 - D17
D0 - D17
V
/V
DD DDQ
RCS0
CS0
R
E
G
I
S
T
E
R
RCS1
RBA0 - RBA1
RA0 - RA12
RRAS
RCAS
RCKE0
RCKE1
RWE
CS1
BA0-BA1
A0-A12
BA0 -BA1 : DDR SDRAM DQ0 - D17
A0 -A12 : DDR SDRAM D0 - D17
RAS : DDR SDRAM D0 - D17
CAS : DDR SDRAM DQ0 - D17
CKE : DDR SDRAM D0 - D8
CKE : DDR SDRAM D9 - D17
WE: DDR SDRAM D0 - D17
D0 - D17
D0 - D17
V
V
REF
RAS
CAS
CKE0
CKE1
WE
SS
PLL
CK0,CK0
PCK
PCK
RESET
Note :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
Rev. 1.01 August 2008
8 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
6.4 1GB, 128M x 72 ECC Module (M312L2920FH3)
(Populated as 1 rank of x4 DDR SDRAM Module)
V
SS
RCS0
DQS0
DQS9
(DM0)
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DM
DM
DM
DM
DM
DM
DM
DM
DM
CS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D9
D0
DQS1
DQS2
DQS3
DQS10
(DM1)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D10
D1
DQS11
(DM2)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
D11
D2
DQS12
(DM3)
DQS
DQS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
D12
D3
DQS13
(DM4)
DQS4
DQS5
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 3
I/O 2
I/O 1
I/O 0
DQ32
DQ33
DQ34
DQ35
D13
D4
DQS14
(DM5)
DQS
DQS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
D14
D5
DQS15
(DM6)
DQS6
DQS
DQS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D15
D6
DQS7
DQS8
DQS16
(DM7)
DQS
DQS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D16
D7
Serial PD
SCL
WP
DQS17
(DM8)
SDA
A2
DQS
DQS
CS
CS
A0
A1
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
I/O 3
I/O 2
I/O 1
I/O 0
CB0
CB1
CB2
CB3
D17
D8
SA0 SA1
SA2
V
DDSPD
SPD
V
/V
DD DDQ
D0 - D17
D0 - D17
RCS0_1
CS0
R
RCS0_2
E
G
I
S
T
E
R
RBA0 - RBA1
RA0 - RA12
RRAS
V
BA0 -BA1 : DDR SDRAM DQ0 - D17
A0 -A12 :DDR SDRAM D0 - D17
REF
BA0-BA1
A0-A12
RAS
CAS
CKE0
D0 - D17
D0 - D17
V
SS
RAS : DDR SDRAM D0 - D17
CAS : DDR SDRAM DQ0 - D17
CKE : DDR SDRAM D0 - D8
CKE : DDR SDRAM D9 - D17
RCAS
RCKE0A
RCKE0B
RWE
PLL
CK0,CK0
WE
WE:DDR SDRAM D0 - D17
PCK
PCK
RESET
Note :
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
Rev. 1.01 August 2008
9 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
6.5 2GB, 256M x 72 ECC Module (M312L5720FH3)
(Populated as 2 rank of x4 DDR SDRAM Module)
V
SS
RCS1
RCS0
DQS0
DQS9
(DM0)
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DM
DM
DM
DM
DM
DM
DM
DM
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DM
DM
DM
DM
DM
DM
DM
DM
DM
CS
CS
CS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D18
D9
D27
DQS1
DQS2
DQS3
DQS10
(DM1)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D19
D10
D28
DQS11
(DM2)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
DQ16
DQ17
DQ18
DQ19
D2
D20
D11
D29
DQS12
(DM3)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ28
DQ29
DQ30
DQ31
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ24
DQ25
DQ26
DQ27
D3
D21
D12
D30
DQS13
(DM4)
DQS4
DQS5
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ32
DQ33
DQ34
DQ35
D4
D22
D13
D31
DQS14
(DM5)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
D5
D23
D14
D32
DQS15
(DM6)
DQS6
DQS7
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D6
D24
D15
D33
DQS16
(DM7)
DQS
DQS
DQS
DQS
CS
CS
CS
CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D7
D25
D16
D34
DQS17
(DM8)
DQS8
DQS
DQS
CS
CS
DQS
DM
DQS
DM
CS
CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB0
CB1
CB2
CB3
D17
D35
D8
D26
V
DDSPD
SPD
Serial PD
V
/V
DD DDQ
D0 - D35
D0 - D35
SCL
WP
SDA
A0
A1
A2
V
REF
D0 - D35
D0 - D35
V
SA0 SA1
SA2
SS
PLL*
CK0,CK0
CS0
CS1
BA0-BA1
A0-A12
RCS0
R
E
G
I
S
T
E
R
RCS1
RBA0 - RBA1
RA0 - RA12
BA0-BA1: DDR SDRAM D0 - D35
A0-A12: DDR SDRAM D0 - D35
Note :
RAS: DDR SDRAM D0 - D35
RRAS
RAS
CAS
CKE0
CKE1
WE
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.
3. DQ, DQS, DM resistors: 22 Ohms.
RCAS
CAS: DDR SDRAM D0 - D35
CKE: DDR SDRAM D0 - D17
CKE: DDR SDRAM D18 - D35
RCKE0
RCKE1
RWE
WE: DDR SDRAM D0 - D35
PCK
PCK
RESET
Rev. 1.01 August 2008
10 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
7.0 Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN,VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to VSS
Storage temperature
Power dissipation
VDD,VDDQ
TSTG
PD
-1.0 ~ 3.6
-55 ~ +150
V
°C
W
1.5 * # of component
50
Short circuit current
IOS
mA
Note :
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
2. Functional operation should be restricted to recommended operating condition.
3. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
8.0 Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit Note
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
VDD
2.3
2.7
2.7
V
V
V
V
Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333)
I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
I/O Reference voltage
VDD
VDDQ
VDDQ
VREF
VTT
2.5
2.3
2.7
2.5
2.7
0.49*VDDQ
VREF-0.04
VREF+0.15
-0.3
0.51*VDDQ
VREF+0.04
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.4
V
V
1
2
I/O Termination voltage(system)
Input logic high voltage
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VI(Ratio)
II
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
-0.3
V
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
0.36
3
4
V
0.71
-
-2
2
uA
uA
mA
mA
mA
mA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOH
-16.8
16.8
IOL
IOH
-9
IOL
9
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may
not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track
variations in the DC level of VREF
.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,
for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers
due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to
source voltages from 0.1 to 1.0.
Rev. 1.01 August 2008
11 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
9.0 DDR SDRAM IDD spec table
9.1 1GB, 128M x 72 ECC Module (M312L2920FLS)
(VDD=2.7V, T = 10°C)
Symbol
IDD0
B0(DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
2335
2875
415
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
1165
775
865
1435
2875
2965
4135
415
IDD6
Normal
Low power
IDD7A
379
6475
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
9.2 512MB, 64M x 72 ECC Module (M312L6523FH3)
(VDD=2.7V, T = 10°C)
Unit Notes
Symbol
IDD0
CC (DDR400@CL=3)
B3 (DDR333@CL=2.5)
1830
2100
420
1695
1965
420
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
1020
600
1020
600
780
645
1290
2145
2325
2730
420
1155
2010
2100
2595
420
IDD6
Normal
Low power
IDD7A
402
402
4215
3990
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.01 August 2008
12 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
9.3 1GB, 128M x 72 ECC Module (M312L2923FH3)
(VDD=2.7V, T = 10°C)
Symbol
IDD0
CC (DDR400@CL=3)
B3 (DDR333@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
2495
2765
590
2225
2495
590
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
1415
950
1415
950
1310
1955
2810
2990
3395
590
1040
1685
2540
2630
3125
590
IDD6
Normal
Low power
IDD7A
554
554
4880
4520
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
9.4 1GB, 128M x 72 ECC Module (M312L2920FH3)
(VDD=2.7V, T = 10°C)
Unit Notes
Symbol
IDD0
B3 (DDR333@CL=2.5)
2640
3180
465
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
1290
825
915
1560
3270
3450
4440
465
IDD6
Normal
Low power
IDD7A
429
7230
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.01 August 2008
13 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
9.5 2GB, 256M x 72 ECC Module (M312L5720FH3)
(VDD=2.7V, T = 10°C)
Symbol
IDD0
B3 (DDR333@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
3700
4240
805
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
2080
1525
1705
2620
4330
4510
5500
805
IDD6
Normal
Low power
IDD7A
733
8290
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.01 August 2008
14 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
10.0 AC Operating Conditions
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Note :
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
Max
Unit
V
Note
VREF + 0.31
VREF - 0.31
VDDQ+0.6
V
0.7
V
1
2
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
VTT=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
11.0 Input/Output Capacitance
(TA= 25°C, f=100MHz)
M312L2920FLS
Parameter
Symbol
Unit
Min
9
Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1
11
11
11
12
11
11
11
pF
pF
pF
pF
pF
pF
pF
Input capacitance(CKE0)
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
9
Input capacitance( CS0)
9
Input capacitance( CLK0, CLK0 )
Input capacitance(DM0~DM8)
11
10
10
10
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
M312L6523FH3
M312L2920FH3
M312L2923FH3
M312L5720FH3
Parameter
Symbol
Unit
Min
Max
Min
Max
11
11
11
12
15
15
15
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) CIN1
9
9
11
11
11
12
11
11
11
9
9
pF
pF
pF
pF
pF
pF
pF
Input capacitance(CKE0)
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
Input capacitance( CS0)
9
9
Input capacitance( CLK0, CLK0 )
Input capacitance(DM0~DM8)
11
10
10
10
11
13
13
13
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
Rev. 1.01 August 2008
15 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
12.0 AC Timming Parameters & Specifications
CC
B3
B0
(DDR266@CL=2.5)
(DDR400@CL=3.0)
(DDR333@CL=2.5)
Parameter
Symbol
Unit Note
Min
55
Max
Min
60
Max
Min
65
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
Refresh row cycle time
Row active time
70
72
75
40
70K
42
70K
45
70K
ns
RAS to CAS delay
15
18
20
ns
Row precharge time
15
18
20
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
10
12
15
ns
15
15
15
ns
Last data in to Read command
tWTR
2
1
1
tCK
ns
CL=2.5
CL=3.0
6
12
10
6
12
-
7.5
-
12
-
Clock cycle time
tCK
5
-
ns
Clock high level width
Clock low level width
tCH
tCL
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.45
0.45
-0.75
-0.75
-
0.55
0.55
+0.75
+0.75
0.5
tCK
tCK
ns
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tDSS
tDSH
tDQSH
tDQSL
tIS
ns
tCK
tCK
tCK
ns
22
13
0.9
0.4
0.72
0
1.1
0.9
0.4
0.75
0
0.9
0.4
0.75
0
1.1
Read Postamble
0.6
0.6
0.6
CK to valid DQS-in
1.28
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.7
0.7
-0.65
-0.65
10
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
0.8
-0.7
-0.7
12
0.25
0.2
0.2
0.35
0.35
0.9
0.9
1.0
1.0
-0.75
-0.75
15
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
15, 17~19
15, 17~19
16~19
16~19
11
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
tIH
ns
tIS
ns
tIH
ns
tHZ
+0.65
+0.65
+0.7
+0.7
+0.75
+0.75
ns
tLZ
ns
11
tMRD
tDS
ns
DQ & DM setup time to DQS
0.4
0.45
0.5
ns
j, k
j, k
ns
DQ & DM hold time to DQS
tDH
0.4
0.45
0.5
Control & Address input pulse width
DQ & DM input pulse width
tIPW
tDIPW
tXSNR
tXSRD
tREFI
2.2
1.75
75
2.2
1.75
75
2.2
1.75
75
ns
ns
18
18
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
ns
200
200
200
tCK
us
7.8
7.8
7.8
-
14
21
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
ns
ns
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
20, 21
Data hold skew factor
tQHS
0.5
0.6
0.55
0.6
0.75
0.6
ns
21
12
DQS write postamble time
tWPST
0.4
15
0.4
18
0.4
20
tCK
Active to Read with Auto precharge
command
tRAP
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Autoprecharge write recovery +
Precharge time
tDAL
tCK
23
Rev. 1.01 August 2008
16 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
13.0 System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR400, DDR333, DDR266 devices to ensure proper system per-
formance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
PARAMETER
DDR400
DDR333
DDR266
SYMBOL
Units
Notes
MIN
MAX
MIN
MAX
MIN
MAX
DQ/DM/DQS input slew rate measured between
DCSLEW
0.5
4.0
0.5
4.0
0.5
4.0
V/ns
a, l
V
IH(DC), VIL(DC) and VIL(DC), VIH(DC)
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
∆tIS
0
∆tIH
Units
ps
Notes
0
0
0
i
i
i
0.4 V/ns
+50
+100
ps
0.3 V/ns
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
∆tDS
0
∆tDH
0
Units
ps
Notes
k
k
k
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
+/- 0.0 V/ns
∆tDS
0
∆tDH
0
Units
ps
Notes
j
j
j
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g,h
b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g,h
b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS
PARAMETER
DDR400
DDR333
DDR266
Notes
e,l
MIN
0.67
MAX
MIN
MAX
MIN
MAX
Output Slew Rate Matching Ratio (Pullup to Pulldown)
1.5
0.67
1.5
0.67
1.5
Rev. 1.01 August 2008
17 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
14.0 Component Notes
1. All voltages referenced to VSS
.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related speci-
fications and device operation are guaranteed for the full voltage range specified.
3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise rep-
resentation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or
other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions
(generally a coaxial transmission line terminated at the tester electronics).
VDDQ
50Ω
Output
(Vout)
30pF
Figure 1 : Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing
point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate
for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing
the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is recognized as LOW.
7. Enables on.chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other
than CK/CK, is VREF
.
10. The output timing reference voltage level is VTT
.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage
level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance
(bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is
defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will
be transitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this
time, depending on tDQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
17. For CK & CK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
correlation.
19. Slew Rate is measured between VOH(AC) and VOL(AC).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater
than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the
clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration dis-
tortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transi-
tion, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers.
22. tDQSQ - Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
23. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15
ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks
Rev. 1.01 August 2008
18 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
15.0 System Notes:
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.
Test point
50Ω
Output
V
SSQ
Figure 2 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 3.
V
DDQ
50Ω
Output
Test point
Figure 3 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range.
For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is
based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate
is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either
V
IH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of
the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(AC) to VIL(AC)
or VIH(DC) to VIL(DC), and similarly for rising transitions.
l. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC
region must be monotonic.
m. In case of Registered DIMM, device operation defines Power up and Power Management.
184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption
during low power mode. One feature is externally controlled via a system-generated RESET signal; the second is based on module detection of the
input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations
and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-
Refresh mode. device operation describes this more detailly.
Rev. 1.01 August 2008
19 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
16.0 Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
A0 ~ A9
Note
COMMAND
CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP
A11, A12
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
Self
3
Refresh
L
H
X
H
X
H
X
3
Refresh
Exit
L
H
H
H
X
X
H
3
Row Address
(A0~A9, A11,A12)
Bank Active & Row Addr.
L
L
L
H
L
H
H
V
V
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
Read &
Column Address
Column
Address
H
4
Write &
Column Address
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
X
Bank Selection
All Banks
V
X
L
Precharge
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
L
H
L
Active Power Down
X
X
Exit
X
H
L
Entry
H
Precharge Power Down Mode
DM
H
L
Exit
L
H
H
H
X
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note :
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.01 August 2008
20 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
17.0 Physical Dimensions
17.1 128Mx72 (M312L2920FLS)
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.171
(131.350)
5.077
(128.950)
REG
0.0787
R (2.00)
PLL
0.78
(19.80)
A
A
B
B
2.500 +0.1/-0.0
M
0.10
C B A
0.157 Max
(3.99 Max)
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00 Min)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
0.050
(1.270)
0.1575 ± 0.004
(4.00 ± 0.1)
(1.80)
Detail A
0.10
C
M AM
B
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 128Mx4 DDRSDRAM, TSOPII
SDRAM Part No. : K4H510438F-L***
Rev. 1.01 August 2008
21 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
17.2 64Mx72 (M312L6523FH3)
Units : Millimeters
133.35 A
128.95 A
1.27 +/-0.1
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
2x DIA. 2.50 +0.1/-0.00 N
1
a
b
92
2.99 MAX
6.35
64.77 P2
49.53 P3
120.65 P1
93
184
6.35 X
X1
X2
2.175
4.175
D
1.0 +/-0.05
3.80 W
V
1.80
E
1.27
MAX 0.178 D1
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8 DDR SDRAM, FBGA
DDR SDRAM Part No. : K4H510838F-H***
Rev. 1.01 August 2008
22 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
17.3 128Mx72 (M312L2923FH3), (M312L2920FH3)
Units : Millimeters
133.35 A
128.95 A
1.27 +/-0.1
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
2x DIA. 2.50 +0.1/-0.00 N
1
a
b
92
3.99 MAX
6.35
64.77 P2
49.53 P3
120.65 P1
93
184
6.35 X
X1
X2
2.175
4.175
D
1.0 +/-0.05
3.80 W
V
1.80
E
1.27
MAX 0.178 D1
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 64Mx8, 128Mx4 DDR SDRAM, FBGA
DDR SDRAM Part No. : K4H510838F-H***, K4H510438F-H***
Rev. 1.01 August 2008
23 of 24
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM
17.4 256Mx72 (M312L5720FH3)
Units : Millimeters
133.35 A
128.95 A
1.27 +/-0.1
2x 3.00 MIN W1
4x 4.00+/-0.1 V1
1 2x DIA. 2.50 +0.1/-0.00 N
6.35
a
b
92
3.99 MAX
64.77 P2
49.53 P3
120.65 P1
93
184
6.35 X
X1 X2
2.175
4.175
D
1.0 +/-0.05
3.80 W
V
1.80
E
1.27
MAX 0.178 D1
Detail A
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 128Mx4 DDR SDRAM, FBGA
DDR SDRAM Part No : K4H510438F-H***
Rev. 1.01 August 2008
24 of 24
相关型号:
M312L2923FH3-CCC
DDR DRAM Module, 128MX72, 0.65ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-184
SAMSUNG
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