M364E0484CT0-C60 [SAMSUNG]
EDO DRAM Module, 4MX64, 60ns, CMOS, DIMM-168;型号: | M364E0484CT0-C60 |
厂家: | SAMSUNG |
描述: | EDO DRAM Module, 4MX64, 60ns, CMOS, DIMM-168 动态存储器 内存集成电路 |
文件: | 总22页 (文件大小:468K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DRAM MODULE
M364E040(8)4CT0-C
Buffered 4Mx64 DIMM
(4Mx16 base)
Revision 0.0
June 1999
DRAM MODULE
M364E040(8)4CT0-C
Revision History
Version 0.0 (June 1999)
• The 4th. generation of 64Mb DRAM components are applied for this module.
c
DRAM MODULE
M364E040(8)4CT0-C
M364E040(8)4CT0-C EDO Mode
4M x 64 DRAM DIMM Using 4Mx16, 4K & 8K Refresh, 5V
GENERAL DESCRIPTION
FEATURES
• Part Identification
The Samsung M364E040(8)4CT0-C is a 4Mx64bits Dynamic
RAM high density memory module. The Samsung
M364E040(8)4CT0-C consists of four CMOS 4Mx16bits
DRAMs in TSOP-II 400mil packages and two 16 bits driver IC
in TSSOP package mounted on a 168-pin glass-epoxy sub-
strate. A 0.1 or 0.22uF decoupling capacitor is mounted on
the printed circuit board for each DRAM. The
M364E040(8)4CT0-C is a Dual In-line Memory Module and is
intended for mounting into 168 pin edge connector sockets.
Part number
PKG
Ref.
4K
CBR Ref.
ROR Ref.
8K/64ms
M364E0404CT0-C TSOPll
M364E0484CT0-C TSOPll
4K/64ms
8K
4K/64ms
• Extended Data Out Mode Operation
• CAS-before-RAS Refresh capability
• RAS-only and Hidden refresh capability
• TTL compatible inputs and outputs
• Single 5V±10% power supply
PERFORMANCE RANGE
Speed
tRAC
50ns
60ns
tCAC
18ns
20ns
tRC
tHPC
20ns
25ns
• JEDEC standard pinout & Buffered PDpin
• Buffered input except RAS and DQ
• PCB : Height(1000mil), single sided component
-C50
84ns
104ns
-C60
PIN NAMES
PIN CONFIGURATIONS
Pin
Pin Front Pin Front
Front Pin Back Pin Back Pin Back
Pin Names
Function
A0, B0, A1 - A11 Address Input(4K ref.)
A0, B0, A1 - A12 Address Input(8K ref.)
57
58
59
60
61
62
63
64
65
66
1
2
3
4
5
6
7
8
9
VSS
29 CAS2
DQ22 85
DQ23 86 DQ36 114 *RAS1 142 DQ59
87 DQ37 115 RFU 143 VCC
DQ24 88 DQ38 116 VSS 144 DQ60
VSS 113 CAS3 141 DQ58
DQ0 30 RAS0
DQ0 - DQ71
W0, W2
OE0, OE2
RAS0, RAS2
CAS0 - CAS7
VCC
Data In/Out
DQ1 31
DQ2 32
DQ3 33
OE0
VSS
A0
VCC
Read/Write Enable
Output Enable
RFU 89 DQ39 117
RFU 90 VCC 118
RFU 91 DQ40 119
RFU 92 DQ41 120
DQ25 93 DQ42 121
A1
A3
A5
A7
A9
145 RFU
146 RFU
147 RFU
148 RFU
149 DQ61
VCC
34
A2
Row Address Strobe
Column Address Strobe
Power(+5V)
DQ4 35
DQ5 36
DQ6 37
A4
A6
A8
10 DQ7 38
11 *DQ8 39
12
13 DQ9 41 RFU
14 DQ10 42 RFU
15 DQ11 43
16 DQ12 44
17 DQ13 45 RAS2
18 46 CAS4
19 DQ14 47 CAS6
20 DQ15 48
21 DQ16 49
A10
A12
VCC
*DQ26 94 DQ43 122 A11 150 *DQ62
VSS
Ground
67 DQ27 95 *DQ44 123 *A13 151 DQ63
68
69
70
71
72
73
74
75
76
77
VSS
40
VSS
96
DQ28 97 DQ45 125 RFU 153 DQ64
DQ29 98 DQ46 126 B0 154 DQ65
VSS 124 VCC 152 VSS
NC
No Connection
Presence Detect Enable
Presence Detect
ID bit
PDE
PD1 - 8
ID0 - 1
VSS
OE2
DQ30 99 DQ47 127 VSS 155 DQ66
DQ31 100 DQ48 128 RFU 156 DQ67
VCC 101 DQ49 129 *RAS3 157 VCC
DQ32 102 VCC 130 CAS5 158 DQ68
DQ33 103 DQ50 131 CAS7 159 DQ69
DQ34 104 DQ51 132 PDE 160 DQ70
*DQ35 105 DQ52 133 VCC 161 *DQ71
VSS 106 *DQ53 134 RSVD 162 VSS
PD1 107 VSS 135 RSVD 163 PD2
PD3 108 RSVD 136 DQ54 164 PD4
PD5 109 RSVD 137 DQ55 165 PD6
PD7 110 VCC 138 VSS 166 PD8
ID0 111 RFU 139 DQ56 167 ID1
VCC 112 CAS1 140 DQ57 168 VCC
RSVD
Reserved Use
VCC
RFU
Reserved for Future Use
Pins marked ¢*¢ are not used in this module.
W2
VCC
PD & ID Table
22 *DQ17 50 RSVD 78
Pin
50NS
60NS
79
80
81
82
83
84
23
VSS
51 RSVD
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
1
1
0
1
1
0
0
1
1
1
0
1
1
1
1
1
24 RSVD 52 DQ18
25 RSVD 53 DQ19
26
27
VCC
W0
54
VSS
55 DQ20
28 CAS0 56 DQ21
NOTE : A12 is used for only M364E0484CT-C (8K Ref.)
ID0
ID1
0
0
0
0
PD Note :PD & ID Terminals must each be pulled up through a resistor to VCC at the next higher
level assembly. PDs will be either open (NC) or driven to VSS via on-board buffer circuits.
ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer.
PD : 0 for Vol of Drive IC & 1 for N.C
ID : 0 for Vss & 1 for N.C
DRAM MODULE
M364E040(8)4CT0-C
FUNCTIONAL BLOCK DIAGRAM
RAS0
W0
RAS2
W2
OE2
OE0
B0
A0
A1-A11(A12)
A1-A11(A12)
LCAS
CAS0
LCAS
CAS4
DQ36
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ37
DQ1
DQ38
DQ2
DQ39
DQ40
DQ41
DQ42
DQ43
DQ3
DQ4
DQ5
DQ6
DQ7
U2
U0
UCAS
CAS1
UCAS
CAS5
DQ8
DQ9
DQ8
DQ9
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
LCAS
LCAS
CAS6
CAS2
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
U1
UCAS
UCAS
CAS7
CAS3
DQ63
DQ64
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ8
DQ9
DQ8
DQ9
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Note : A12 is used for only M364E0484CT (8K ref.)
A0
U0-U1
B0
A1-A11(A12)
W0, OE0
U2-U3
U0-U3
U0-U1
U2-U3
Vcc
W2, OE2
0.1 or 0.22uF Capacitor
under each DRAM
To all DRAMs
Vss
DRAM MODULE
M364E040(8)4CT0-C
ABSOLUTE MAXIMUM RATINGS *
Item
Symbol
Rating
Unit
Voltage on any pin relative VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC
-1 to +7.0
-1 to +7.0
-55 to +125
4
V
V
°C
W
Tstg
PD
Power Dissipation
Short Circuit Output Current
IOS
50
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70°C)
Item
Symbol
Min
Typ
Max
Unit
4.5
0
2.4
5.5
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
5.0
0
-
V
V
V
V
0
*1
VCC
*2
-
-1.0
0.8
*1 : VCC+2.0V at pulse width£20ns, which is measured at VCC.
*2 : -2.0V at pulse width£20ns, which is measured at VSS.
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted)
M364E0404CT0
M364E0484CT0
Symbol
Speed
Unit
Min
Max
Min
Max
-50
-60
480
440
-
-
360
320
mA
mA
-
-
ICC1
ICC2
ICC3
Don¢t care
-
100
-
100
mA
-50
-60
-
-
480
440
-
-
360
320
mA
mA
-50
-60
-
-
440
400
-
-
400
360
mA
mA
ICC4
ICC5
ICC6
Don¢t care
-
30
-
30
mA
-50
-60
-
-
480
440
-
-
360
320
mA
mA
II(L)
IO(L)
-10
-5
10
5
-10
-5
10
5
uA
uA
Don¢t care
Don¢t care
VOH
VOL
2.4
-
-
2.4
-
-
V
V
0.4
0.4
ICC1*
ICC2
ICC3*
ICC4*
ICC5
ICC6*
I(IL)
: Operating Current * (RAS, CAS, Address cycling @tRC=min)
: Standby Current (RAS=CAS=W=VIH)
: RAS Only Refresh Current * (CAS=VIH, RAS cycling @tRC=min)
: Extended Data Out Mode Current * (RAS=VIL, CAS cycling : tHPC=min)
: Standby Current (RAS=CAS=W=Vcc-0.2V)
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @tRC=min)
: Input Leakage Current (Any input 0£VIN£Vcc+0.5V, all other pins not under test=0 V)
: Output Leakage Current(Data Out is disabled, 0V£VOUT£Vcc)
: Output High Voltage Level (IOH = -5mA)
I(OL)
VOH
VOL
: Output Low Voltage Level (IOL = 4.2mA)
* NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1 and ICC3, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.
DRAM MODULE
M364E040(8)4CT0-C
CAPACITANCE (TA = 25°C, f = 1MHz)
Item
Symbol
Min
Max
Unit
Input capacitance[A0, B0, A1 - A12]
Input capacitance[W0, W2, OE0, OE2]
Input capacitance[RAS0, RAS2]
Input capacitance[CAS0 - CAS7]
Input/Output capacitance[DQ0 - 71]
CIN1
CIN2
CIN3
CIN4
CDQ
20
20
24
20
17
pF
pF
pF
pF
pF
-
-
-
-
-
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.0/0.8V, output loading CL=100pF
-50
-60
Parameter
Symbol
Unit
Note
Min
84
Max
Min
104
155
Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
tRC
133
tRWC
tRAC
tCAC
tAA
50
18
30
60
20
35
Access time from CAS
3,4,5,13
3,10,13
3,13
Access time from column address
CAS to output in Low-Z
8
8
8
8
tCLZ
tOLZ
tCEZ
tT
OE to output in Low-Z
3,13
Output buffer turn-off delay from CAS
Transition time(rise and fall)
RAS precharge time
8
18
50
8
18
50
6,11,13
2
1
1
30
50
18
36
8
40
60
20
43
10
18
13
10
5
tRP
RAS pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCS
tWCH
tWP
RAS hold time
13
13
CAS hold time
CAS pulse width
10K
32
10K
40
RAS to CAS delay time
18
13
10
5
4,13
10,13
13
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
20
25
13
8
8
13
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold referenced to CAS
Read command hold referenced to RAS
Write command set-up time
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
0
0
14
8
10
35
0
14
30
0
13
0
0
8
8,13
7
-2
0
-2
0
10
10
18
8
10
10
20
10
-2
15
13
17
tRWL
tCWL
tDS
-2
13
9,13
9,13
Data hold time
tDH
Refresh period(4K & 8K)
CAS to W delay time
64
64
tREF
tCWD
tRWD
36
73
38
83
7,16
7,13
RAS to W delay time
DRAM MODULE
M364E040(8)4CT0-C
AC CHARACTERISTICS (0°C£TA£70°C, VCC=5.0V±10%. See notes 1,2.)
-50
-60
Parameter
Symbol
Unit
Note
Min
48
53
10
8
Max
Min
53
60
10
8
Max
Column address to W delay time
CAS precharge time to W delay time
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tHPC
tHPRWC
tCP
13,18
13
3
3
13
Access time from CAS precharge
Hyper page cycle time
33
40
3,13
12
20
70
8
25
77
10
60
40
15
8
Hyper page read-modify-write cycle time
CAS precharge time(Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
OE access time
12
15
50
35
15
8
200K
200K
tRASP
tRHCP
tWRP
tWRH
tOEA
tOED
tOEZ
tOEH
tDOH
tREZ
13
13
13
13
13
13
18
18
20
18
OE to data delay
18
8
18
8
Output buffer turn off delay time from OE
OE command hold time
13
10
3
15
10
3
Output data hold time(C-B-R refresh)
Output buffer turn off delay time from RAS
Output buffer turn off delay time from W
W to data delay
13
6,11
6,13
13
15
18
15
20
8
8
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
20
5
20
5
OE to CAS hold time
CAS hold time to OE
5
5
OE precharge time
5
5
W pulse width (Hyper page cycle)
5
5
Present Detect Read Cycle
PDE to Valid PD bit
10
7
10
7
ns
ns
tPD
PDE to PD bit Inactive
2
2
tPDOFF
DRAM MODULE
M364E040(8)4CT0-C
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
1.
10.
11.
Operation within the tRAD(max) limit insures that tRAC(max)
can be met. tRAD(max) is specified as reference point only. If
tRAD is greater than the specified tRAD(max) limit, then
access time is controlled by tAA.
2. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between VIH(min) and VIL(max) and
are assumed to be 5ns for all inputs.
If RAS goes high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes high before RAS high going , the open circuit condition
of the output is achieved by RAS going.
3.
Measured with a load equivalent to 2 TTL loads and 100pF.
12. tASC³ 6ns.
4. Operation within the tRCD(max) limit insures that tRAC(max)
can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then
access time is controlled exclusively by tCAC.
13. The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
tASC, tCAH are referenced to the earlier CAS falling edge.
14.
15.
5.
6.
Assumes that tRCD³ tRCD(max).
tCP is specified from the last CAS rising edge in the previous
cycle to the first CAS falling edge in the next cycle.
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to VOH or
VOL.
tCWD is referenced to the later CAS falling edge at word read-
modify-write cycle.
16.
17.
7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If tWCS³ tWCS(min) the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If tRWD³ tRWD(min),
tCWD³ tCWD(min), tAWD³ tAWD(min) and tCPWD³ tCPWD(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
tCWL is specified from W falling edge to the earlier CAS rising
edge.
18. tCSR is referenced to earlier CAS falling low before RAS tran-
sition low.
8.
Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to the CAS leading edge in
early write cycles.
DRAM MODULE
M364E040(8)4CT0-C
READ CYCLE
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
VIH -
CAS
tCAS
VIL -
tRAD
tRAL
tASR
tRAH
tASC
tRCS
tCAH
VIH -
A
ROW
ADDRESS
COLUMN
ADDRESS
VIL -
tRCH
tRRH
VIH -
W
VIL -
tWEZ
tCEZ
tAA
tOEZ
VIH -
tOEA
tOLZ
OE
VIL -
tCAC
tCLZ
tREZ
tRAC
VOH -
DQ
OPEN
DATA-OUT
VOL -
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tASR
tCRP
tRCD
tRSH
VIH -
CAS
VIL -
tCAS
tRAD
tRAL
tRAH
tASC
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tCWL
tRWL
tWCH
tWCS
VIH -
tWP
W
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRP
VIH -
RAS
VIL -
tCSH
tCRP
tCRP
tRCD
tRSH
tCAS
VIH -
CAS
VIL -
tRAD
tASC
tRAL
tASR
tRAH
tCAH
VIH -
A
ROW
ADDRESS
COLUMN
ADDRESS
VIL -
tCWL
tRWL
VIH -
tWP
W
VIL -
VIH -
OE
tOEH
VIL -
tOED
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
READ - MODIFY - WRITE CYCLE
tRWC
tRAS
tRP
VIH -
VIL -
RAS
CAS
tCRP
tASR
tRCD
tRSH
VIH -
VIL -
tCAS
tCSH
tRAD
tRAH
tASC
tCAH
VIH -
VIL -
ROW
ADDR
COLUMN
ADDRESS
A
tAWD
tCWD
tRWL
tCWL
VIH -
VIL -
W
tWP
tRWD
tOEA
VIH -
VIL -
OE
tOLZ
tCLZ
tCAC
tAA
tOED
tDS
tDH
tOEZ
tRAC
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
DQ
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
HYPER PAGE READ CYCLE
tRP
tRASP
VIH -
VIL -
RAS
¡ó
tCSH
tRCD
tRHCP
tHPC
tHPC
tCAS
tHPC
tCRP
tASR
tCP
tCP
tCP
tCAS
tCAS
tCAS
VIH -
VIL -
CAS
tRAD
tRAH tASC
tCAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
tREZ
VIH -
VIL -
ROW
COLUMN
ADDRESS
COLUMN
ADDRESS
COLUMN
ADDR
COLUMN
ADDRESS
A
ADDR
tRRH
tRCS
tRCH
VIH -
VIL -
tCPA
W
tCAC
tCAC
tAA
tCHO
tCAC
tAA
tCPA
tOCH
tOEA
tAA
tCPA
tAA
tCAC
tOEP
VIH -
VIL -
tOEA
OE
DQ
tOEP
tOEZ
tOEA
tCAC
tDOH
tOEZ
tOEZ
tRAC
VOH -
VOL -
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-OUT
tOLZ
tCLZ
VALID
DATA-OUT
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
tRASP
¡ó
VIH -
RAS
tRHCP
VIL -
tHPC
tHPC
tRSH
tCAS
tCRP
tRCD
tCP
tCP
VIH -
VIL -
tCAS
tCAS
¡ó
CAS
tRAD
tRAH
tCSH
tASC
tASR
tCAH
tASC
tCAH
COLUMN
tASC
tCAH
¡ó
¡ó
VIH -
VIL -
ROW
ADDR.
COLUMN
ADDRESS
COLUMN
ADDRESS
A
ADDRESS
tWCS
tWCH
tWCS
tWP
tWCH
tWCS
tWCH
tWP
¡ó
VIH -
VIL -
tWP
W
tCWL
tCWL
tCWL
tRWL
¡ó
¡ó
VIH -
VIL -
OE
tDS
tDH
tDS
tDH
tDS
tDH
¡ó
¡ó
VIH -
VIL -
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
DQ
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
tCP
VIH -
VIL -
tCSH
tRSH
RAS
CAS
tHPRWC
tCRP
tCRP
tRCD
VIH -
VIL -
tCAS
tCAS
tRAL
tRAD
tRAH
tCAH
tCAH
tASR
tASC
tASC
VIH -
VIL -
ROW
ADDR
COL.
ADDR
COL.
ADDR
A
W
tRWL
tCWL
tRCS
tCWL
VIH -
VIL -
tWP
tWP
tCWD
tAWD
tRWD
tCWD
tAWD
tCPWD
VIH -
VIL -
tOEA
tOEA
OE
tOED
tOED
tCAC
tCAC
tDH
tDH
tAA
tAA
tOEZ
tOEZ
tDS
tDS
tRAC
VI/OH -
VI/OL -
DQ
tCLZ
tCLZ
VALID
tOLZ
tOLZ
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
DATA-IN
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
HYPER PAGE READ AND WRITE MIXED CYCLE
tRP
tRASP
READ(tCPA)
VIH -
VIL -
READ(tCAC)
READ(tAA)
WRITE
RAS
tHPC
tHPC
tHPC
tCP
tCP
tCP
VIH -
VIL -
tCAS
tCAS
tCAS
tCAS
tCAH
CAS
A
tRAD
tRAH
tASR
tASC tCAH
tCAH
tASC
tASC
tCAH
tASC
COLUMN
VIH -
VIL -
COL.
ADDR
COL.
ADDR
COLUMN
ROW
ADDR
ADDRESS
ADDRESS
tRCS
tRCH
tRCS
tRCH
tWCH
tRCH
VIH -
VIL -
tWCS
W
tWPE
tCPA
tCLZ
tWED
VIH -
VIL -
OE
tDH
tDS
tOEA
tCAC
tAA
tRAC
tWEZ
tREZ
tAA
tWEZ
VI/OH -
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
VALID
DATA-OUT
DQ
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, DIN = Don¢t care
DOUT = OPEN
tRC
tRP
VIH -
RAS
VIL -
tRAS
tRPC
tCRP
tCRP
VIH -
CAS
VIL -
tASR
tRAH
VIH -
VIL -
ROW
ADDR
A
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tRPC
tCP
tCSR
VIH -
CAS
VIL -
tCHR
tWRP
tWRH
VIH -
W
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
Don¢t care
Undefined
* In RAS-only refresh cycle of 64Mb A-dile & B-die, when CAS signal transits from Low to High, the valid data may be cut off.
DRAM MODULE
M364E040(8)4CT0-C
HIDDEN REFRESH CYCLE ( READ )
tRC
tRC
tRAS
tRP
tRP
tRAS
VIH -
VIL -
RAS
CAS
tCRP
tASR
tRCD
tRSH
tCHR
VIH -
VIL -
tRAD
tRAH
tASC
tRCS
tCAH
COLUMN
ADDRESS
VIH -
VIL -
ROW
ADDRESS
A
W
tWRH
tWRP
tRRH
VIH -
VIL -
tAA
VIH -
VIL -
tOEA
OE
tCEZ
tOLZ
tCAC
tREZ
tWEZ
tCLZ
tRAC
tOEZ
VOH -
VOL -
DATA-OUT
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
tRAS
tRC
tRP
tRAS
tRP
VIH -
RAS
VIL -
tCRP
tRCD
tRSH
tCHR
VIH -
CAS
VIL -
tRAD
tASR
tRAH
tASC
tCAH
VIH -
ROW
ADDRESS
COLUMN
ADDRESS
A
VIL -
tWRH
tWRP
tWCS
tWCH
VIH -
tWP
W
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE
tRP
VIH -
RAS
VIL -
tRAS
tCPT
tRSH
tCAS
tCSR
VIH -
CAS
VIL -
tCHR
tRAL
tASC
COLUMN
ADDRESS
tCAH
VIH -
VIL -
A
tRRH
tRCH
tAA
tWRP
tWRH
tWRH
tWRH
READ CYCLE
tRCS
tCAC
VIH -
W
VIL -
VIH -
OE
VIL -
tWEZ
tCEZ
tREZ
tOEA
tOEZ
tCLZ
VOH -
DQ
DATA-OUT
VOL -
WRITE CYCLE
tRWL
tWRP
tCWL
VIH -
W
tWCS
tWCH
tWP
VIL -
VIH -
OE
VIL -
tDS
tDH
DATA-IN
VIH -
DQ
VIL -
READ-MODIFY-WRITE
tAWD
tCWD
tCWL
tRWL
tWRP
tRCS
VIH -
tWP
W
tCAC
tOEA
VIL -
tAA
VIH -
OE
tOED
tOEZ
VIL -
tDH
tCLZ
tDS
VI/OH -
DQ
VI/OL -
VALID
DATA-OUT
VALID
DATA-IN
Don¢t care
NOTE : This timing diagram is applied to all devices besides 64M DRAM based modules.
Undefined
DRAM MODULE
M364E040(8)4CT0-C
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don¢t care
tRP
tRASS
tRPS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCHS
tCSR
VIH -
CAS
VIL -
tCEZ
VOH -
DQ
OPEN
VOL -
VIH -
W
VIL -
tWRP
tWRH
TEST MODE IN CYCLE
NOTE : OE , A = Don¢t care
tRC
tRP
tRP
tRAS
VIH -
RAS
VIL -
tRPC
tCP
tRPC
tCSR
tWTS
VIH -
VIL -
tCHR
CAS
W
tWTH
VIH -
VIL -
tCEZ
VOH -
VOL -
DQ
OPEN
Don¢t care
Undefined
DRAM MODULE
M364E040(8)4CT0-C
PACKAGE DIMENSIONS
Units : Inches (millimeters)
5.250
(133.350)
0.054
(1.372)
R 0.079
0.118
(3.000)
5.014
(127.350)
(R 2.000)
0.157±0.004
(4.000±0.100)
B
C
A
.118DIA±.004
(3.000DIA±.100)
0.250
(6.350)
0.250
(6.350)
1.450
2.150
0.350
(8.890)
(36.830)
(54.61)
.450
(11.430)
4.550
(115.57)
( Front view )
0.100Max
(2.54Max)
0.050±0.0039
(1.270±0.10)
( Back view )
0.250
(6.350)
0.250
(6.350)
0.039±.002
(1.000±.050)
0.1230±.0050
(3.125±.125)
0.1230±.0050
(3.125±.125)
0.01Max
(0.25 Max)
0.050
(1.270)
0.079±.0040
(2.000±.100)
0.079±.0040
(2.000±.100)
Detail A
Detail B
Detail C
Tolerances : ±.005(.13) unless otherwise specified
The used device is 4Mx16 DRAM with EDO mode, TSOP II.
DRAM Part No. : M364E0404CT0 - K4E641611C-T
M364E0484CT0 - K4E661611C-T
相关型号:
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