M366S1654HUS-C7A [SAMSUNG]
Synchronous DRAM Module, 16MX64, 5.4ns, CMOS, ROHS COMPLIANT, DIMM-168;
| 型号： | M366S1654HUS-C7A |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM Module, 16MX64, 5.4ns, CMOS, ROHS COMPLIANT, DIMM-168 时钟 动态存储器 内存集成电路 |
| 文件： | 总18页 (文件大小：371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
SDRAM Unbuffered Module
168pin Unbuffered Module based on 256Mb H-die
54 TSOP-II with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
Table of Contents
1.0 Ordering Information ................................................................................................................... 2
2.0 Operating Frequencies ................................................................................................................ 2
3.0 Feature .......................................................................................................................................... 2
4.0 Pin Configuration (Front side/back side) .................................................................................. 3
5.0 Pin Description ............................................................................................................................. 3
6.0 Functional Block Diagram ........................................................................................................... 5
6.1 128MB, 64M x 64 Module (M366S1654HUS) ...................................................................................... 5
6.2 256MB, 32M x 64 Non ECC Module (M366S3253HUS) ........................................................................ 6
6.3 512MB, 64M x 64 Non ECC Module (M366S6453HUS) ........................................................................ 7
7.0 Absolute Maximum Ratings ........................................................................................................ 8
8.0 DC Operating Conditions ............................................................................................................ 8
9.0 DC CHARACTERISTICS .............................................................................................................. 9
9.1 M366S1654HUS (16M x 64,128MB Module) ...................................................................................... 9
9.2 M366S3253HUS (32M x 64, 256MB Module) ...................................................................................... 9
9.3 M366S6453HUS (64M x 64, 512MB Module) .................................................................................... 10
10.0 AC Operating Conditions......................................................................................................... 11
11.0 OPERATING AC PARAMETER ................................................................................................ 11
12.0 AC CHARACTERISTICS .......................................................................................................... 12
13.0 SIMPLIFIED TRUTH TABLE ..................................................................................................... 13
14.0 Physical Dimensions ............................................................................................................... 14
14.1 16M x 64 (M366S1654HUS) ........................................................................................................ 14
14.2 32Mx64 (M366S3253HUS) ......................................................................................................... 15
14.3 64Mx64 (M366S6453HUS) ......................................................................................................... 16
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
Revision History
Revision
0.0
Month
July
Year
2005
2005
History
- First release
- Revision 1.0
1.0
November
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
168Pin Unbuffered DIMM based on 256Mb H-die (x8, x16)
1.0 Ordering Information
Component
Package
Part Number
Density
Organization
Component Composition
Height
M366S1654HUS-C7A
M366S3253HUS-C7A
M366S6453HUS-C7A
128MB
256MB
512MB
16M x 64
32M x 64
64M x 64
16M x 16 (K4S561632H) * 4EA
32M x 8 (K4S560832H) * 8EA
32M x 8 (K4S560832H) * 16EA
1,000mil
1,375mil
1,375mil
54-TSOP(II)
2.0 Operating Frequencies
7A
@CL3
133MHz(7.5ns)
3 - 3 - 3
@CL2
100MHz(10ns)
2 - 2 - 2
Maximum Clock Frequency
CL-tRCD-tRP(clock)
3.0 Feature
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
• 54pin TSOP II Pb-Free package
• RoHS compliant
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
4.0 Pin Configuration (Front side/back side)
Pin
Front
Pin
Back
Pin
Back
Pin
Back
Pin
Back
Pin
Back
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
1
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
**CS0
DU
DQ18
DQ19
VDD
85
86
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
**CS1
RAS
VSS
A1
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
DQ50
DQ51
VDD
2
3
87
4
VSS
A0
DQ20
NC
88
DQ52
NC
5
89
6
A2
*VREF
**CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
90
A3
*VREF
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
7
A4
91
A5
8
A6
92
A7
9
A8
93
A9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A10/AP
BA1
VDD
VDD
**CLK0
VSS
DU
94
BA0
95
A11
96
VDD
**CLK1
A12
97
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
98
99
VSS
**CKE0
**CS3
DQM6
DQM7
*A13
VDD
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
**CS2
DQM2
DQM3
DU
VDD
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ28
DQ29
DQ30
DQ31
VSS
DQ60
DQ61
DQ62
DQ63
VSS
DQ46
DQ47
CB4
CB1
CB5
VSS
NC
**CLK2
NC
VSS
NC
**CLK3
NC
NC
CB6
CB7
VSS
DQ48
DQ49
NC
NC
NC
SA0
VDD
WE
SDA
VDD
SA1
SCL
CAS
SA2
DQM0
VDD
DQM4
VDD
1. * These pins are not used in this module.
2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD.
3. Pins 21,22,52,53,105,106,136,137are used only ECC(x72) Module.
4. ** About these pins, Refer to the Block Diagram of each.
5.0 Pin Description
Pin Description
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0 ~ 3
CKE0, CKE1
CS0 ~ CS3
RAS
Function
Address input (Multiplexed)
Select bank
Data input/output
Check bit (Data-in/data-out)
Clock input
Clock enable input
Chip select input
Row address strobe
Colume address strobe
Write enable
Pin Name
DQM0 ~ 7
VDD
Function
DQM
Power supply (3.3V)
Ground
Power supply for reference
Register enable
Serial data I/O
Serial clock
VSS
VREF
REGE
SDA
SCL
SA0 ~ 2
DU
Address in EEPROM
Don′t use
CAS
WE
NC
No connection
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin
Name
Input Function
CLK
CS
System clock
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tss prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12
Column address : (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
A0 ~ A12
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data input/output mask
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
REGE
Register enable
DQ0 ~ 63
CB0 ~ 7
VDD/VSS
Data input/output
Check bit
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
Power supply/ground
Power and ground for the input buffers and the core logic.
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
6.0 Functional Block Diagram
6.1 128MB, 64M x 64 Module (M366S1654HUS)
(Populated as 1 bank of x16 SDRAM Module)
•
CS0
DQM0
DQM4
LDQM CS
LDQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ0
DQ1
DQ2
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U0
U2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
UDQM
DQM5
UDQM
DQ8
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
•
CS2
DQM2
DQM6
LDQM CS
LDQM CS
DQ16
DQ0
DQ1
DQ2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
U1
U3
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQM3
UDQM
DQM7
UDQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ8
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
Serial PD
SDRAM U0 ~ U3
A0 ~ A12, BA0 & 1
SCL
SDA
WP
A0 A1 A2
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
RAS
CAS
WE
47KΩ
SA0 SA1 SA2
10Ω
U0/U2
U1/U3
•
•
CLK0/2
CKE0
15pF
10Ω
DQn
Every DQpin of SDRAM
10Ω
CLK1/3
VDD
Vss
•
•
•
•
Two 0.1uF
Capacitors
10pF
To all SDRAMs
per each SDRAM
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
6.2 256MB, 32M x 64 Non ECC Module (M366S3253HUS)
(Populated as 1 bank of x8 SDRAM Module)
•
CS0
DQM0
DQM4
DQM CS
DQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
U4
DQM1
DQM5
DQM CS
DQM CS
DQ8
DQ9
DQ0
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
U5
•
CS2
DQM2
DQM6
DQM CS
DQM CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
DQM3
DQM7
DQM CS
DQM CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
Serial PD
SCL
SDA
WP
A0 A1 A2
47KΩ
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
A0 ~ A12, BA0 & 1
SA0 SA1 SA2
RAS
CAS
WE
U0/U2
U4/U6
•
10Ω
•
CLK0/2
CKE0
U1/U3
U5/U7
•
10Ω
DQn
3.3pF*1
Every DQpin of SDRAM
•
•
•
VDD
10Ω
One 0.1uF and one 0.22 uF Cap.
per each SDRAM
CLK2/3
To all SDRAMs
10pF
•
Vss
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
6.3 512MB, 64M x 64 Non ECC Module (M366S6453HUS)
(Populated as 2 bank of x8 SDRAM Module)
CS1
•
CS0
•
•
•
DQM0
DQM4
DQM CS
DQM CS
DQM CS
DQM CS
DQ0
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
DQ32
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
U12
U0
U8
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
•
•
DQM1
DQM5
DQM CS
DQM CS
DQM CS
DQM CS
DQ8
DQ9
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ1
DQ0
DQ1
DQ1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U5
U13
U1
U9
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
CS3
•
•
CS2
•
DQM2
DQM6
•
DQM CS
DQM CS
DQM CS
DQM CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ0
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
DQ1
DQ2
U14
U6
U2
U10
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
•
DQM3
•
DQM7
DQM CS
DQM CS
DQM CS
DQM CS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
DQ1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U7
U15
U3
U11
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
A0 ~ A12, BA0 & 1
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U7
Serial PD
VDD
SCL
RAS
CAS
WE
SDA
WP
A0 A1 A2
47KΩ
10KΩ
SA0 SA1 SA2
CKE0
CKE1
•
SDRAM U8 ~ U15
CLK0/1/2/3
U0/U1/U2/U3
10Ω
•
10Ω
DQn
Every DQpin of SDRAM
U4/U5/U6/U7
•
U8/U9/U10/U11
U12/U13/U14/U15
•
•
VDD
•
•
•
Two 0.1uF Capacitors
per each SDRAM
To all SDRAMs
3.3pF
Vss
•
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
7.0 Absolute Maximum Ratings
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
Unit
V
-1.0 ~ 4.6
V
-55 ~ +150
1.0 * # of component
50
°C
W
Power dissipation
PD
Short circuit current
IOS
mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
8.0 DC Operating Conditions
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
3.3
3.0
0
Max
Unit
V
Note
3.6
Input high voltage
Input low voltage
VDDQ+0.3
V
1
VIL
0.8
-
V
2
Output high voltage
Output low voltage
Input leakage current
VOH
VOL
ILI
-
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
M366S1654HUS
M366S3253HUS
M366S6453HUS
Sym-
Parameter
Unit
bol
Min
15
15
15
10
10
8
Max
25
25
25
13
15
10
12
Min
25
25
25
15
15
8
Max
45
45
45
21
25
12
12
Min
Max
85
85
45
21
25
15
18
Input capacitance (A0 ~ A11)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE)
Input capacitance (CLK)
Input capacitance (CS)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
45
45
25
15
15
10
13
pF
pF
pF
pF
pF
pF
pF
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
9
9
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
9.0 DC CHARACTERISTICS
9.1 M366S1654HUS (16M x 64,128MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
mA
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
360
1
ICC2P
ICC2PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
8
8
Precharge standby current
in power-down mode
mA
ICC2N
80
Precharge standby current
in non power-down mode
mA
ICC2NS
40
ICC3P
ICC3PS
25
25
Active standby current in
power-down mode
mA
mA
mA
ICC3N
100
Active standby current in
non power-down mode
(One bank active)
ICC3NS
100
IO = 0 mA
Page burst
Operating current
(Burst mode)
ICC4
520
mA
1
2
4Banks activated
tCCD = 2CLKs
Refresh current
Self refresh current
ICC5
ICC6
tRC ≥ tRC(min)
720
12
mA
mA
CKE ≤ 0.2V
9.2 M366S3253HUS (32M x 64, 256MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
mA
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
640
1
ICC2P
ICC2PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
16
16
Precharge standby current
in power-down mode
mA
ICC2N
160
Precharge standby current
in non power-down mode
mA
ICC2NS
80
ICC3P
ICC3PS
50
50
Active standby current in
power-down mode
mA
mA
mA
ICC3N
200
Active standby current in
non power-down mode
(One bank active)
ICC3NS
200
IO = 0 mA
Page burst
Operating current
(Burst mode)
ICC4
800
mA
1
2
4Banks activated
tCCD = 2CLKs
Refresh current
Self refresh current
ICC5
ICC6
tRC ≥ tRC(min)
1,440
24
mA
mA
CKE ≤ 0.2V
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
9.3 M366S6453HUS (64M x 64, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
mA
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
840
1
ICC2P
ICC2PS
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
32
32
Precharge standby current
in power-down mode
mA
ICC2N
320
Precharge standby current
in non power-down mode
mA
ICC2NS
160
ICC3P
ICC3PS
96
96
Active standby current in
power-down mode
mA
mA
mA
ICC3N
400
Active standby current in
non power-down mode
(One bank active)
ICC3NS
400
IO = 0 mA
Page burst
Operating current
(Burst mode)
ICC4
1,000
mA
1
2
4Banks activated
tCCD = 2CLKs
Refresh current
Self refresh current
ICC5
ICC6
tRC ≥ tRC(min)
1,620
48
mA
mA
CKE ≤ 0.2V
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
10.0 AC Operating Conditions
Parameter
Value
2.4/0.4
1.4
Unit
V
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
50pF
50pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
(AC operating conditions unless otherwise noted)
11.0 OPERATING AC PARAMETER
Version
Parameter
Symbol
Unit
Note
7A
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
15
ns
ns
1
1
1
1
20
Row precharge time
20
ns
tRAS(min)
tRAS(max)
tRC(min)
45
ns
Row active time
100
us
Row cycle time
65
ns
1
2,5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + tRP
1
1
1
2
1
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off
to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
(AC operating conditions unless otherwise noted)
12.0 AC CHARACTERISTICS
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
7A
Parameter
Symbol
Unit
ns
Note
1
Min
7.5
10
Max
CAS latency=3
CLK cycle
time
tCC
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
5.4
6
CLK to valid
output delay
tSAC
ns
1,2
2
3
Output data
hold time
tOH
ns
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
13.0 SIMPLIFIED TRUTH TABLE
A0 ~ A9,
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
A11, A12
Register
Refresh
Mode register set
H
X
H
L
L
L
L
L
X
OP code
1,2
3
Auto refresh
H
L
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
Column
address
L
L
H
H
L
L
H
L
Write &
column address
Column
address
H
X
X
V
H
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
14.0 Physical Dimensions
14.1 16M x 64 (M366S1654HUS)
Units : Inches (Millimeters)
5.250
(133.350)
5.014
(127.350)
0.118
(3.000)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.100 Max
(2.54 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ±0.006
(0.200 ±0.150)
0.123 ± 0.005
(3.125 ± 0.125)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail C
Detail A
Detail B
Tolerances : ± .005(.13) unless otherwise specified
The used device is 16Mx16 SDRAM, TSOPII
SDRAM Part No. : K4S561632H
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
14.2 32Mx64 (M366S3253HUS)
Units : Inches (Millimeters)
5.250
(133.350)
0.089
(2.26)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.100 Max
(2.54 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ±0.006
(0.200 ±0.150)
0.123 ± 0.005
(3.125 ± 0.125)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail C
Detail A
Detail B
Tolerances : ± .005(.13) unless otherwise specified
The used device is 32Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S560832G
Rev. 1.0 November 2005
128MB, 256MB, 512MB Unbuffered DIMM
SDRAM
14.3 64Mx64 (M366S6453HUS)
Units : Inches (Millimeters)
5.250
(133.350)
5.014
(127.350)
0.118
(3.000)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
B
C
A
.118DIA +0.004/-0.000
(3.000DIA +0.100/-0.000)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
(6.350)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ± 0.006
(0.200 ± 0.150)
0.123 ± 0.005
(3.125 ± 0.125)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail C
Detail A
Detail B
Tolerances : ± .005(.13) unless otherwise specified
The used device is 32Mx8 SDRAM, TSOPII
SDRAM Part No. : K4S560832H
Rev. 1.0 November 2005
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