M366S3323CT0-C1L_技术文档

SERIAL PRESENCE DETECT

PC100 Unbuffered DIMM

PC100 Unbuffered DIMM(168pin)

SPD Specification(128Mb C-die base)

Rev. 0.1

Apr. 2000

Rev 0.1 Apr. 2000

SERIAL PRESENCE DETECT

PC100 Unbuffered DIMM

M366S1724CT0-C1H/C1L

• Organization : 16Mx64

• Composition : 8Mx16 *8

• Used component part # : K4S281632C-TC1H/C1L

• # of rows in module : 2 Rows

• # of banks in component : 4 banks

• Feature : 1,375mil height & double sided component

• Refresh : 4K/64ms

• Contents ;

Function Supported

-1H -1L

Hex value

Byte #

Function Described

Note

-1H

-1L

0

1

# of bytes written into serial memory at module manufacturer

Total # of bytes of SPD memory device

Fundamental memory type

128bytes

80h

08h

04h

0Ch

09h

02h

40h

00h

01h

256bytes (2K-bit)

2

SDRAM

12

3

# of row address on this assembly

1

4

# of column address on this assembly

# of module Rows on this assembly

Data width of this assembly

9

5

2 Rows

64 bits

-

6

7

...... Data width of this assembly

8

Voltage interface standard of this assembly

SDRAM cycle time @CAS latency of 3

SDRAM access time from clock @CAS latency of 3

DIMM configuration type

LVTTL

9

10ns

6ns

10ns

6ns

A0h

60h

A0h

60h

2

10

11

12

13

14

15

16

17

18

19

20

Non parity

00h

80h

10h

00h

01h

8Fh

04h

06h

01h

Refresh rate & type

15.625us, support self refresh

Primary SDRAM width

x16

None

Error checking SDRAM width

Minimum clock delay for back-to-back random column address

SDRAM device attributes : Burst lengths supported

SDRAM device attributes : # of banks on SDRAM device

SDRAM device attributes : CAS latency

SDRAM device attributes : CS latency

SDRAM device attributes : Write latency

tCCD = 1CLK

1, 2, 4, 8 & full page

4 banks

2 & 3

0 CLK

Non-buffered, non-registered

& redundant addressing

21

SDRAM module attributes

00h

+/- 10% voltage tolerance,

Burst Read Single bit Write

precharge all, auto precharge

22

SDRAM device attributes : General

0Eh

23

24

25

26

27

28

29

30

31

32

33

34

SDRAM cycle time @CAS latency of 2

SDRAM access time from clock @CAS latency of 2

SDRAM cycle time @CAS latency of 1

SDRAM access time from clock @CAS latency of 1

Minimum row precharge time (=tRP)

10ns

6ns

-

12ns

7ns

-

A0h

60h

00h

14h

32h

C0h

70h

00h

14h

32h

2

-

20ns

50ns

20ns

50ns

Minimum row active to row active delay (tRRD)

Minimum RAS to CAS delay (=tRCD)

Minimum activate precharge time (=tRAS)

Module Row density

10h

2 Rows of 64MB

Command and address signal input setup time

Command and address signal input hold time

Data signal input setup time

2ns

1ns

2ns

1ns

2ns

20h

10h

20h

10h

20h

Rev 0.1 Apr. 2000

SERIAL PRESENCE DETECT

PC100 Unbuffered DIMM

Function Supported

Hex value

Byte #

Function Described

Note

-1H

-1L

-1H

-1L

35

Data signal input hold time

1ns

10h

36~61 Superset information (maybe used in future)

-

00h

12h

62

63

64

SPD data revision code

PC100 SPD Spec. Ver. 1.2A

Checksum for bytes 0 ~ 62

Manufacturer JEDEC ID code

-

0Eh

3Eh

Samsung

CEh

00h

01h

4Dh

33h

20h

36h

53h

31h

37h

32h

34h

43h

54h

30h

2Dh

43h

65~71 ...... Manufacturer JEDEC ID code

Samsung

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Manufacturing location

Onyang Korea

Manufacturer part # (Memory module)

Manufacturer part # (DIMM configuration)

Manufacturer part # (Data bits)

M

3

Blank

6

...... Manufacturer part # (Data bits)

Manufacturer part # (Mode & operating voltage)

Manufacturer part # (Module depth)

...... Manufacturer part # (Module depth)

Manufacturer part # (Refresh, # of banks in Comp. & interface)

Manufacturer part # (Composition component)

Manufacturer part # (Component revision)

Manufacturer part # (Package type)

Manufacturer part # (PCB revision & type)

Manufacturer part # (Hyphen)

6

S

1

7

2

4

C

T

0

" - "

C

Manufacturer part # (Power)

Manufacturer part # (Minimum cycle time)

Manufacturer part # (TBD)

1

L

31h

48h

31h

4Ch

H

Blank

0

20h

Manufacturer revision code (For PCB)

...... Manufacturer revision code (For component)

Manufacturing date (Week)

30h

C-die (4th Gen.)

43h

-

3

4

5

Manufacturing date (Year)

-

95~98 Assembly serial #

-

Undefined

-

99~125 Manufacturer specific data (may be used in future)

126

127

System frequency for 100MHz

PC100 specification details

Unused storage locations

100MHz

64h

Detailed 100MHz Information

Undefined

FFh

FDh

128+

-

5

Note :

1. The bank select address is excluded in counting the total # of addresses.

2. This value is based on the component specification.

3. These bytes are programmed by code of Date Week & Date Year with BCD format.

4. These bytes are programmed by Samsung ¢s own Assembly Serial # system. All modules may have different unique serial #.

5. These bytes are Undefined and can be used for Samsung ¢s own purpose.

Rev 0.1 Apr. 2000

SERIAL PRESENCE DETECT

PC100 Unbuffered DIMM

M366S3323CT0-C1H/C1L

• Organization : 32Mx64

• Composition : 16Mx8 *16

• Used component part # : K4S280832C-TC1H/C1L

• # of rows in module : 2 Rows

• # of banks in component : 4 banks

• Feature : 1,375mil height & double sided component

• Refresh : 4K/64ms

• Contents ;

Function Supported

-1H -1L

Hex value

Byte #

Function Described

Note

-1H

-1L

0

1

# of bytes written into serial memory at module manufacturer

Total # of bytes of SPD memory device

Fundamental memory type

128bytes

80h

08h

04h

0Ch

0Ah

02h

40h

00h

01h

256bytes (2K-bit)

2

SDRAM

12

3

# of row address on this assembly

1

4

# of column address on this assembly

# of module Rows on this assembly

Data width of this assembly

10

5

2 Rows

64 bits

-

6

7

...... Data width of this assembly

8

Voltage interface standard of this assembly

SDRAM cycle time @CAS latency of 3

SDRAM access time from clock @CAS latency of 3

DIMM configuration type

LVTTL

9

10ns

6ns

10ns

6ns

A0h

60h

A0h

60h

2

10

11

12

13

14

15

16

17

18

19

20

Non parity

00h

80h

08h

00h

01h

8Fh

04h

06h

01h

Refresh rate & type

15.625us, support self refresh

Primary SDRAM width

x8

None

Error checking SDRAM width

Minimum clock delay for back-to-back random column address

SDRAM device attributes : Burst lengths supported

SDRAM device attributes : # of banks on SDRAM device

SDRAM device attributes : CAS latency

SDRAM device attributes : CS latency

SDRAM device attributes : Write latency

tCCD = 1CLK

1, 2, 4, 8 & full page

4 banks

2 & 3

0 CLK

Non-buffered, non-registered

& redundant addressing

21

SDRAM module attributes

00h

+/- 10% voltage tolerance,

Burst Read Single bit Write

precharge all, auto precharge

22

SDRAM device attributes : General

0Eh

23

24

25

26

27

28

29

30

31

32

33

34

SDRAM cycle time @CAS latency of 2

SDRAM access time from clock@CAS latency of 2

SDRAM cycle time @CAS latency of 1

SDRAM access time from clock@CAS latency of 1

Minimum row precharge time (=tRP)

10ns

6ns

-

12ns

7ns

-

A0h

60h

00h

14h

32h

C0h

70h

00h

14h

32h

2

-

20ns

50ns

20ns

50ns

Minimum row active to row active delay (tRRD)

Minimum RAS to CAS delay (=tRCD)

Minimum activate precharge time (=tRAS)

20h

Module Row density

2 Rows of 128MB

Command and address signal input setup time

Command and address signal input hold time

Data signal input setup time

2ns

1ns

2ns

1ns

2ns

20h

10h

20h

10h

20h

Rev 0.1 Apr. 2000

SERIAL PRESENCE DETECT

PC100 Unbuffered DIMM

Function Supported

Hex value

Byte #

Function Described

Note

-1H

-1L

-1H

-1L

35

Data signal input hold time

1ns

10h

36~61 Superset information (maybe used in future)

-

00h

12h

62

63

64

SPD data revision code

PC100 SPD Spec. Ver. 1.2A

Checksum for bytes 0 ~ 62

Manufacturer JEDEC ID code

-

17h

47h

Samsung

CEh

00h

01h

4Dh

33h

20h

36h

53h

33h

32h

33h

43h

54h

30h

2Dh

43h

65~71 ...... Manufacturer JEDEC ID code

Samsung

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Manufacturing location

Onyang Korea

Manufacturer part # (Memory module)

Manufacturer part # (DIMM configuration)

Manufacturer part # (Data bits)

M

3

Blank

6

...... Manufacturer part # (Data bits)

Manufacturer part # (Mode & operating voltage)

Manufacturer part # (Module depth)

...... Manufacturer part # (Module depth)

Manufacturer part # (Refresh, # of banks in Comp. & interface)

Manufacturer part # (Composition component)

Manufacturer part # (Component revision)

Manufacturer part # (Package type)

Manufacturer part # (PCB revision & type)

Manufacturer part # (Hyphen)

6

S

3

2

3

C

T

0

" - "

C

Manufacturer part # (Power)

Manufacturer part # (Minimum cycle time)

Manufacturer part # (TBD)

1

L

31h

48h

31h

4Ch

H

Blank

0

20h

Manufacturer revision code (For PCB)

...... Manufacturer revision code (For component)

Manufacturing date (Week)

30h

C-die (4th Gen.)

43h

-

3

4

5

Manufacturing date (Year)

-

95~98 Assembly serial #

-

Undefined

-

99~125 Manufacturer specific data (may be used in future)

126

127

System frequency for 100MHz

PC100 specification details

Unused storage locations

100MHz

64h

Detailed 100MHz Information

Undefined

FFh

FDh

128+

-

5

Note :

1. The bank select address is excluded in counting the total # of addresses.

2. This value is based on the component specification.

3. These bytes are programmed by code of Date Week & Date Year with BCD format.

4. These bytes are programmed by Samsung ¢s own Assembly Serial # system. All modules may have different unique serial #.

5. These bytes are Undefined and can be used for Samsung ¢s own purpose.

Rev 0.1 Apr. 2000

SERIAL PRESENCE DETECT

PC100 Unbuffered DIMM

M374S3323CT0-C1H/C1L

• Organization : 32Mx72

• Composition : 16Mx8 *18

• Used component part # : K4S280832C-TC1H/C1L

• # of rows in module : 2 Rows

• # of banks in component : 4 banks

• Feature : 1,375mil height & double sided component

• Refresh : 4K/64ms

• Contents ;

Function Supported

-1H -1L

Hex value

Byte #

Function Described

Note

-1H

-1L

0

1

# of bytes written into serial memory at module manufacturer

Total # of bytes of SPD memory device

Fundamental memory type

128bytes

80h

08h

04h

0Ch

0Ah

02h

48h

00h

01h

256bytes (2K-bit)

2

SDRAM

12

3

# of row address on this assembly

1

4

# of column address on this assembly

# of module Rows on this assembly

Data width of this assembly

10

5

2 Rows

72 bits

-

6

7

...... Data width of this assembly

8

Voltage interface standard of this assembly

SDRAM cycle time @CAS latency of 3

SDRAM access time from clock @CAS latency of 3

DIMM configuration type

LVTTL

9

10ns

6ns

10ns

6ns

A0h

60h

A0h

60h

2

10

11

12

13

14

15

16

17

18

19

20

ECC

02h

80h

08h

01h

8Fh

04h

06h

01h

Refresh rate & type

15.625us, support self refresh

Primary SDRAM width

x8

Error checking SDRAM width

Minimum clock delay for back-to-back random column address

SDRAM device attributes : Burst lengths supported

SDRAM device attributes : # of banks on SDRAM device

SDRAM device attributes : CAS latency

SDRAM device attributes : CS latency

SDRAM device attributes : Write latency

tCCD = 1CLK

1, 2, 4, 8 & full page

4 banks

2 & 3

0 CLK

Non-buffered, non-registered

& redundant addressing

21

SDRAM module attributes

00h

+/- 10% voltage tolerance,

Burst Read Single bit Write

precharge all, auto precharge

22

SDRAM device attributes : General

0Eh

23

24

25

26

27

28

29

30

31

32

33

34

SDRAM cycle time @CAS latency of 2

10ns

6ns

-

12ns

7ns

-

A0h

60h

00h

14h

32h

C0h

70h

00h

14h

32h

2

SDRAM access time from clock @CAS latency of 2

SDRAM cycle time @CAS latency of 1

SDRAM access time from clock @CAS latency of 1

Minimum row precharge time (=tRP)

-

20ns

50ns

20ns

50ns

Minimum row active to row active delay (tRRD)

Minimum RAS to CAS delay (=tRCD)

Minimum activate precharge time (=tRAS)

20h

Module Row density

2 Rows of 128MB

Command and address signal input setup time

Command and address signal input hold time

Data signal input setup time

2ns

1ns

2ns

1ns

2ns

20h

10h

20h

10h

20h

Rev 0.1 Apr. 2000

SERIAL PRESENCE DETECT

PC100 Unbuffered DIMM

Function Supported

Hex value

Byte #

Function Described

Note

-1H

-1L

-1H

-1L

35

Data signal input hold time

1ns

10h

36~61 Superset information (maybe used in future)

-

00h

12h

62

63

64

SPD data revision code

PC100 SPD Spec. Ver. 1.2A

Checksum for bytes 0 ~ 62

Manufacturer JEDEC ID code

-

29h

59h

Samsung

CEh

00h

01h

4Dh

33h

20h

37h

34h

53h

33h

32h

33h

43h

54h

30h

2Dh

43h

65~71 ...... Manufacturer JEDEC ID code

Samsung

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Manufacturing location

Onyang Korea

Manufacturer part # (Memory module)

Manufacturer part # (DIMM configuration)

Manufacturer part # (Data bits)

M

3

Blank

7

...... Manufacturer part # (Data bits)

Manufacturer part # (Mode & operating voltage)

Manufacturer part # (Module depth)

...... Manufacturer part # (Module depth)

Manufacturer part # (Refresh, # of banks in Comp. & interface)

Manufacturer part # (Composition component)

Manufacturer part # (Component revision)

Manufacturer part # (Package type)

Manufacturer part # (PCB revision & type)

Manufacturer part # (Hyphen)

4

S

3

2

3

C

T

0

" - "

C

Manufacturer part # (Power)

Manufacturer part # (Minimum cycle time)

Manufacturer part # (TBD)

1

L

31h

48h

31h

4Ch

H

Blank

0

20h

Manufacturer revision code (For PCB)

...... Manufacturer revision code (For component)

Manufacturing date (Week)

30h

C-die (4th Gen.)

43h

-

3

4

5

Manufacturing date (Year)

-

95~98 Assembly serial #

-

Undefined

-

99~125 Manufacturer specific data (may be used in future)

126

127

System frequency for 100MHz

PC100 specification details

Unused storage locations

100MHz

64h

Detailed 100MHz Information

Undefined

FFh

FDh

128+

-

5

Note :

1. The bank select address is excluded in counting the total # of addresses.

2. This value is based on the component specification.

3. These bytes are programmed by code of Date Week & Date Year with BCD format.

4. These bytes are programmed by Samsung ¢s own Assembly Serial # system. All modules may have different unique serial #.

5. These bytes are Undefined and can be used for Samsung ¢s own purpose.

Rev 0.1 Apr. 2000


型号：	M366S3323CT0-C1L
厂家：	SAMSUNG
描述：	PC100 Unbuffered DIMM PC100无缓冲DIMM 内存集成电路动态存储器 PC
文件：	总7页 (文件大小：60K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M366S3323CT0-C1L [SAMSUNG]

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