M366S3323MT0-C1H [SAMSUNG]
Synchronous DRAM Module, 32MX64, 6ns, CMOS, DIMM-168;
| 型号： | M366S3323MT0-C1H |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM Module, 32MX64, 6ns, CMOS, DIMM-168 动态存储器 |
| 文件： | 总9页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PC100 Unbuffered DIMM
M366S3323MT0
M366S3323MT0 SDRAM DIMM
32Mx64 SDRAM DIMM based on 16Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
FEATURE
The Samsung M366S3323MT0 is a 32M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M366S3323MT0 consists of sixteen CMOS 16M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM.
• Performance range
Part No.
Max Freq. (Speed)
125MHz (8ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
M366S3323MT0-C80
M366S3323MT0-C1H
M366S3323MT0-C1L
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
The M366S3323MT0 is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,375mil), double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin
Pin Front Pin Front
Front Pin Back Pin Back Pin Back
Pin Name
A0 ~ A11
Function
Address input (Multiplexed)
Select bank
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
1
2
3
4
5
6
7
8
9
VSS
29 DQM1
DQ18 85
DQ19 86 DQ32 114 CS1 142 DQ51
87 DQ33 115 RAS 143 VDD
DQ20 88 DQ34 116 VSS 144 DQ52
VSS 113 DQM5 141 DQ50
BA0 ~ BA1
DQ0 30
DQ1 31
DQ2 32
DQ3 33
CS0
DU
VSS
A0
DQ0 ~ DQ63 Data input/output
CLK0 ~ CLK3 Clock input
VDD
NC
*VREF 90
CKE1 91 DQ36 119
92 DQ37 120
DQ21 93 DQ38 121
89 DQ35 117
A1
A3
A5
A7
A9
145 NC
146 *VREF
147 NC
148 VSS
149 DQ53
CKE0 ~ CKE1 Clock enable input
VDD
34
A2
VDD 118
CS0 ~ CS3
RAS
Chip select input
Row address strobe
Column address strobe
Write enable
DQ4 35
DQ5 36
DQ6 37
A4
A6
A8
VSS
CAS
10 DQ7 38 A10/AP
DQ22 94 DQ39 122 BA0 150 DQ54
DQ23 95 DQ40 123 A11 151 DQ55
WE
11 DQ8 39
12 40
13 DQ9 41
BA1
VDD
VDD
DQM0 ~ 7
VDD
DQM
VSS
VSS
96
VSS 124 VDD 152 VSS
DQ24 97 DQ41 125 CLK1 153 DQ56
DQ25 98 DQ42 126 *A12 154 DQ57
DQ26 99 DQ43 127 VSS 155 DQ58
Power supply (3.3V)
Ground
14 DQ10 42 CLK0
VSS
15 DQ11 43
16 DQ12 44
17 DQ13 45
VSS
DU
CS2
*VREF
SDA
Power supply for reference
Serial data I/O
Serial clock
72 DQ27 100 DQ44 128 CKE0 156 DQ59
73
74
75
76
VDD 101 DQ45 129 CS3 157 VDD
DQ28 102 VDD 130 DQM6 158 DQ60
DQ29 103 DQ46 131 DQM7 159 DQ61
DQ30 104 DQ47 132 *A13 160 DQ62
18
VDD
46 DQM2
SCL
19 DQ14 47 DQM3
SA0 ~ 2
WP
Address in EEPROM
Write protection
Don¢t use
20 DQ15 48
21 *CB0 49
22 *CB1 50
DU
VDD
NC
NC
77 DQ31 105 *CB4 133 VDD 161 DQ63
78
79
80
81
82
83
84
VSS 106 *CB5 134 NC 162 VSS
CLK2 107 VSS 135 NC 163 CLK3
NC 108 NC 136 *CB6 164 NC
WP 109 NC 137 *CB7 165 **SA0
**SDA 110 VDD 138 VSS 166 **SA1
**SCL 111 CAS 139 DQ48 167 **SA2
VDD 112 DQM4 140 DQ49 168 VDD
DU
23
24
25
26
27
VSS
NC
NC
VDD
WE
51
NC
No connection
52 *CB2
53 *CB3
54
*
These pins are not used in this module.
** These pins should be NC in the system
VSS
55 DQ16
which does not support SPD.
28 DQM0 56 DQ17
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 Aug. 1999
PC100 Unbuffered DIMM
M366S3323MT0
PIN CONFIGURATION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9
A0 ~ A11
BA0 ~ BA1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
DQ0 ~ 63
Data input/output mask
Data input/output
Data inputs/outputs are multiplexed on the same pins.
WP pin is connected to VSS through 47KW Resistor.
When WP is "high", EEPROM Programming will be inhibited and the entire memory will
be write-protected.
WP
Write protection
VDD/VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
Rev. 0.0 Aug. 1999
PC100 Unbuffered DIMM
M366S3323MT0
FUNCTIONAL BLOCK DIAGRAM
CS1
CS0
DQM0
·
·
·
·
DQM4
DQM CS
DQM CS
DQM CS
DQM CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U4
U12
U0
U8
·
·
DQM1
DQM5
DQM CS
DQM CS
DQM CS
DQM CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U5
U13
U1
U9
CS3
CS2
DQM2
·
·
·
DQM6
·
DQM CS
DQM CS
DQM CS
DQM CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U6
U14
U2
U10
·
DQM3
·
DQM7
DQM CS
DQM CS
DQM CS
DQM CS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
U11
U7
U15
Serial PD
A0 ~ An, BA0 & 1
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U7
SDA
WP
VDD
SCL
RAS
CAS
WE
·
A0 A1 A2
47KW
10KW
SA0 SA1 SA2
·
CKE0
CKE1
SDRAM U8 ~ U15
U0/U1/U2/U3
10W
·
10W
DQn
U4/U5/U6/U7
Every DQpin of SDRAM
·
CLK0/1/2/3
U8/U9/U10/U11
U12/U13/U14/U15
·
·
VDD
Vss
·
·
·
·
Two 0.1uF Capacitors
per each SDRAM
To all SDRAMs
3.3pF
Rev. 0.0 Aug. 1999
PC100 Unbuffered DIMM
M366S3323MT0
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
16
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
VDD, VDDQ
3.3
3.6
Input logic high voltage
VIH
VIL
VOH
VOL
IIL
3.0
VDDQ+0.3
V
1
Input logic low voltage
0
-
0.8
-
V
2
IOH = -2mA
IOL = 2mA
3
Output logic high voltage
Output logic low voltage
Input leakage current (Inputs)
Input leakage current (I/O pins)
V
-
0.4
16
3
V
-16
-3
-
uA
uA
IIL
-
3,4
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V £ VOUT £ VDDQ.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Pin
Symbol
Min
Max
Unit
Address (A0 ~ A11, BA0 ~ BA1)
RAS, CAS, WE
CADD
CIN
60
60
35
25
25
15
10
90
90
55
35
35
25
20
pF
pF
pF
pF
pF
pF
pF
CKE (CKE0 ~ CKE1)
Clock (CLK0 ~ CLK3)
CS (CS0 ~ CS3)
CCKE
CCLK
CCS
DQM (DQM0 ~ DQM7)
DQ (DQ0 ~ DQ63)
CDQM
COUT
Rev. 0.0 Aug. 1999
PC100 Unbuffered DIMM
M366S3323MT0
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
CAS
Latency
Parameter
Symbol
Test Condition
Burst length = 1
tRC ³ tRC(min)
IOL = 0 mA
Unit Note
-80
-1H
-1L
Operating current
(One bank active)
ICC1
1,200
1,120
1,120
mA
mA
1
ICC2P
CKE £ VIL(max), tCC = 15ns
16
16
Precharge standby current in
power-down mode
ICC2PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC2N
240
112
Precharge standby current in
non power-down mode
mA
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC2NS
ICC3P
CKE £ VIL(max), tCC = 15ns
80
80
Active standby current in
power-down mode
ICC3PS CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
ICC3N
480
320
mA
mA
Active standby current in
non power-down mode
(One bank active)
Input signals are changed one time during 30ns
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
ICC3NS
Input signals are stable
IOL = 0 mA
Page burst
2Banks activated
tCCD = 2CLKs
3
1,440
1,160
1,240
1,240
1,240
1,160
Operating current
(Burst mode)
ICC4
mA
1
2
2
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
CKE £ 0.2V
3,200
24
mA
mA
Self refresh current
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
Rev. 0.0 Aug. 1999
PC100 Unbuffered DIMM
M366S3323MT0
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
·
·
·
·
Output
Output
Z0 = 50W
50pF
50pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
-1L
Note
-80
16
20
20
48
-1H
20
20
20
50
100
70
1
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
20
20
20
50
ns
ns
1
1
1
1
Row precharge time
ns
tRAS(min)
tRAS(max)
tRC(min)
ns
Row active time
us
Row cycle time
68
70
ns
1
2
2
2
3
Last data in to row precharge
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tCDL(min)
tBDL(min)
tCCD(min)
CLK
CLK
CLK
CLK
1
1
Col. address to col. address delay
1
CAS latency=3
CAS latency=2
2
Number of valid output data
ea
4
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 0.0 Aug. 1999
PC100 Unbuffered DIMM
M366S3323MT0
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
-80
-1H
-1L
Parameter
Symbol
Unit
ns
Note
1
Min
8
Max
Min
10
Max
Min
10
Max
CAS latency=3
CLK cycle time
tCC
1000
1000
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
12
10
12
6
6
6
6
6
7
CLK to valid
output delay
tSAC
ns
1,2
2
3
3
3
3
2
1
1
3
3
3
3
2
1
1
3
3
3
3
2
1
1
Output data
hold time
tOH
ns
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
6
6
6
6
6
7
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.0 Aug. 1999
PC100 Unbuffered DIMM
M366S3323MT0
SIMPLIFIED TRUTH TABLE
A11,
A9 ~ A0
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Register
Refresh
Mode register set
Auto refresh
H
H
X
H
L
L
L
L
L
X
OP code
1,2
3
L
L
L
H
X
X
X
X
Entry
3
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
refresh
Exit
L
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Column
address
(A0 ~ A9)
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
Read &
column address
L
L
H
H
L
L
H
L
Column
address
(A0 ~ A9)
Write &
column address
H
X
X
V
H
X
L
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
Bank selection
All banks
V
X
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.0 Aug. 1999
PC100 Unbuffered DIMM
M366S3323MT0
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.250
(133.350)
0.089
R 0.050+0.04
(2.26)
5.014
0.118
(3.000)
(R 1.27+0.1/-0.0)
R 0.079
(127.350)
0.125
0.374
(3.18)
(R 2.000)
(9.505)
0.157 ± 0.004
0.096
(2.44)
(4.000 ± 0.100)
B
C
A
.118DIA ± 0.004
(3.000DIA ± 0.100)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
0.250
0.039 ± 0.002
(1.000 ± 0.050)
(6.350)
(6.350)
0.123 ± 0.005
0.123 ± 0.005
0.008 ±0.006
(3.125 ± 0.125)
(3.125 ± 0.125)
(0.200 ±0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail C
Detail A
Detail B
Tolerances : ± .005(.13) unless otherwise specified
The used device is 16Mx8 SDRAM, TSOP
SDRAM Part No. : K4S280832M
Rev. 0.0 Aug. 1999
相关型号：
M366S3354BTS
SDRAM Unbuffered Module 168pin Unbuffered Module based on 512Mb B-die 62/72-bit Non ECC/ECC
SAMSUNG
M366S3354BTS-C7A
SDRAM Unbuffered Module 168pin Unbuffered Module based on 512Mb B-die 62/72-bit Non ECC/ECC
SAMSUNG
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