M368L1714BT1-CA0 [SAMSUNG]
DDR DRAM Module, 16MX64, 0.8ns, CMOS, DIMM-184;
| 型号： | M368L1714BT1-CA0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 16MX64, 0.8ns, CMOS, DIMM-184 动态存储器 双倍数据速率 |
| 文件： | 总17页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
128MB DDR SDRAM MODULE
(16Mx64(8Mx16*2Bank) based on 8Mx16 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.9
June. 2001
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
Revision History
Revision 0 (Aug 1998)
1. First release for internal usage
Revision 0.1 (May. 1999)
1. Changed die revision from B-die to C-die
2. Changed DC/AC characteristics item from old version
Revision 0.2 (Aug. 1999)
1. Changed die revision from C-die to B-die
2. Modified binning policy
From
To
-Z (133Mhz)
-8 (125Mhz)
-0 (100Mhz)
-Z (133Mhz/266Mbps@CL=2)
-Y (133Mhz/266Mbps@CL=2.5)
-0 (100Mhz/200Mbps@CL=2)
3.Modified the following AC spec values
From.
-Z
To.
-0
-Z
-Y
-0
tAC
+/- 0.75ns
+/- 0.75ns
+/- 1ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
+/- 0.75ns
+/- 0.75ns
+/- 0.5ns
0.5 ns
+/- 0.8ns
+/- 0.8ns
+/- 0.6ns
0.6 ns
tDQSCK
tDQSQ
tDS/tDH
+/- 1ns
+/- 0.5ns
+/- 0.75ns
0.75 ns
0.5 ns
tCDLR*1
tPRE*1
tRPST*1
tHZQ*1
2.5tCK-tDQSS
1tCK +/- 0.75ns
tCK/2 +/- 0.75ns
tCK/2 +/- 0.75ns
2.5tCK-tDQSS
1tCK +/- 1ns
tCK/2 +/- 1ns
tCK/2 +/- 1ns
1tCK
1tCK
1tCK
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
0.9/1.1 tCK
0.4/0.6 tCK
+/- 0.75ns
0.9/1.1 tCK
0.4/0.6 tCK
+/-0.8ns
*1 : Changed description method for the same functionality. This means no difference from the previous version.
4.Changed the following AC parameter symbol From tDQCK To tAC
Output data access time from CK/CK
Revision 0.3 (Sept. 1999)
1. Changed the ordering information.
1-1. Exclude KM mark.
From
To
KMM368...
M368.....
1-2. PCB Revison
From
To
- Blank: 1st generation
- 0: 1st gernation
- 1: 2nd generation
- 2: 3nd generation
M368L1714BT1
- A
- B
: 2nd generation
: 2nd generation
Example:KMM368L1714BT
1-3. Modified binning policy
From
To
- 0 (100Mhz/200Mbps@CL=2)
- Z (133Mhz/266Mbps@CL=2)
- Y (133Mhz/266Mbps@CL=2.5)
- A0 (100Mhz/200Mbps@CL=2)
- A2 (133Mhz/266Mbps@CL=2)
- B0 (133Mhz/266Mbps@CL=2.5)
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
Revision 0.4 (December. 1999)
1. Changed from 3.3V to 2.5V in VDDSPD power.
Revision 0.5 (April. 2000)
< Page 3 >
1. Changed pin 90 from WP to NC in pin configuration table.
2. Changed in pin configuration table as followings.
pin 16 : CK0 -> CK1
pin 17 : CK0 -> /CK1
pin 137 : CK1 -> CK0
pin 138 : CK1 -> /CK0
3. Removed WP in pin description.
< Page 4>
4. Changed Clock wiring as followings.
CK0 / CK0 2SDRAMs -> NC
CK1 / CK1 NC
-> 2 SDRAMs
5. Changed bypassing to reflect common Vdd/Vddq plane.
6. Added A13, BA1.
7. Removed WP from serial PD.
< Page 5>
8. Changed Power & DC operating condition.
From
To
Parameter
I/O Reference voltage
Symbol
Min
Max
1.35
Min
0.49*VDDQ
VREF+0.15
-0.3
Max
0.51*VDDQ
VDDQ+0.3
VREF-0.15
2
VREF
VIH(DC)
VIL(DC)
II
1.15
Input logic high voltage
Input logic low voltage
Input leakage current
Output High Current (V
VREF+0.18
-0.3
VDDQ+0.3
VREF-0.18
5
-5
-2
= 1.95V)
= 0.35V)
IOH
-15.2
15.2
-16.8
OUT
OUT
Output Low Current (V
IOL
16.8
< Page 6 >
9. Added Overshoot/Undershoot spec
. Vih(max) = 4.2V, the overshoot voltage duration is £ 3ns at VDD.
. Vil(min) =- 1.5V, the overshoot voltage duration is £ 3ns at VSS.
< Page 6,7 >
10. Changed AC operating conditions as follows.
From
To
Parameter/Condition
Symbol
Min
Max
Min
Max
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.35
Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC)
VREF + 0.31
0.62
VREF - 0.35
VDDQ+0.6
VREF - 0.31
VDDQ+0.6
Input Differential Voltage, CK and CK inputs
VID(AC) 0.7
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
< Page 7 >
11. Changed Input/Output capacitance as follows.
From
To
Parameter
Symbol
Min
Max
Min
Max
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS, WE )
Input capacitance(CKE0)
CIN1
CIN2
CIN3
CIN4
-
50
29
34
-
-
-
35
32
42
29
26
30
34
30
32
Input capacitance( CS0 )
Input capacitance( CLK1, CLK2)
Data & DQS input/output capacitance(DQ0~DQ63)
Input capacitance(DM0~DM8)
COUT
CIN5
-
-
16
16
8
8
9
9
< page 8, 9>
12. Changed AC parameters as follows.
Parameter
tDQSQ
tDV
from
to
Comments
Removed
+/- 0.5(PC266), +/- 0.6(PC200)
+/- 0.35tCK
+0.5(PC266), +0.6(PC200)
-
13. Added AC parameters as follows
-A2(PC266@CL=2) -B0(PC266@CL=2.5) -A0(PC200@CL=2)
Parameter
Symbol
Min
Max
Min
Max
Min
Max
tHPmin
-0.75ns
tHPmin
-0.75ns
tHPmin
-1.0ns
Output DQS valid window
Clock half period
tQH
-
-
-
tCLmin
or
tCLmin
or
tCLmin
or
tHP
-
-
-
tCHmin
tCHmin
tCHmin
QFC setup to first DQS edge on reads
QFC hold after last DQS edge on reads
Write command to QFC delay on write
Write burst end to QFC delay on write
tQCS
0.9
0.4
0.9
0.4
0.9
0.4
1.1
0.6
1.1
0.6
1.1
0.6
tDQCH
tQCSW
tQCHW
4.0
4.0
4.0
1.25ns
1.25ns
0.5tCK
1.25ns
1.25ns
0.5tCK
1.25ns
1.25ns
0.5tCK
Write burst end to QFC delay on write
interrupted by Precharge
tQCHWI
1.5tCK
1.5tCK
1.5tCK
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
Revision 0.7 (October. 2000)
1.Added DC target spec values.
2.Deleted tDAL in AC parameter X.
Revision 0.8 (November. 2000)
1.Changed component placement on module PCB in package dimesions.
Revision 0.9 (June. 2001)
1. Changed module current speificaton
2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).
3. Changed AC parameter table.
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
M368L1714BT1 DDR SDRAM 184pin DIMM
16Mx64 DDR SDRAM 184pin DIMM based on 8Mx16
FEATURE
GENERAL DESCRIPTION
• Performance range
The Samsung M368L1714BT1 is 16M bit x 64 Double Data
Rate SDRAM high density memory modules based on first gen
of 128Mb DDR SDRAM respectively.
Part No.
Max Freq.
Interface
M368L1714BT1-C(L)A2 133MHz(7.5ns@CL=2)
M368L1714BT1-C(L)B0 133MHz(7.5ns@CL=2.5)
SSTL_2
The Samsung M368L1714BT1 consists of eight CMOS 8M x
16 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 184pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M368L1714BT1 is Dual In-line Memory Modules and
intended for mounting into 184pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
100MHz(10ns@CL=2)
M368L1714BT1-C(L)A0
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
• Serial presence detect with EEPROM
• PCB:Height1450(mil),double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN DESCRIPTION
Pin Front Pin Front Pin Front Pin
Back
Pin Back Pin
Back
Pin Name
A0 ~ A11
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
1
2
3
4
5
VREF 32
DQ0 33 DQ24 63
VSS 34 VSS 64 DQ41 95
DQ1 35 DQ25 65 /CAS
DQS0 36 DQS3 66 VSS
DQ2 37 A4 67 DQS5 98
A5
62 VDDQ 93
VSS
DQ4
DQ5
124
125
VSS
A6
154
155
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
/WE 94
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0,CK0 , CK2, CK2
CKE0,CKE1
/CS0, /CS1
RAS
126 DQ28 156
96 VDDQ 127 DQ29 157
97
Data Strobe input/output
Clock input
DM0
DQ6
DQ7
VSS
NC
128 VDDQ 158
6
129
130
DM3
A3
159
160
7
8
VDD 38 VDD 68 DQ42 99
DQ3 39 DQ26 69 DQ43 100
VSS
Clock enable input
Chip select input
131 DQ30 161
132 VSS 162
133 DQ31 163
134 *CB4 164
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
NC
9
10
NC
NC
40 DQ27 70
41 A2 71 */CS2 102
VDD 101
Row address strobe
Column address strobe
Write enable
NC
*A13
11 VSS 42 VSS 72 DQ48 103
12 DQ8 43 A1
CAS
73 DQ49 104 VDDQ 135 *CB5 165
WE
13 DQ9 44 *CB0 74
14 DQS1 45 *CB1 75
15 VDDQ 46 VDD 76
VSS 105 DQ12 136 VDDQ 166
/CK2 106 DQ13 137 *CK0 167
DM0 ~ DM7
VDD
Data - in mask
CK2
107
DM1
VDD
138 */CK0 168
139 VSS 169
VDD
DM6
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
16 CK1
47 *DQS8 77 VDDQ 108
VDDQ
17 /CK1 48
A0
78 DQS6 109 DQ14 140 *DM8 170
A10 171
19 DQ10 50 VSS 80 DQ51 111 CKE1 142 *CB6 172
20 DQ11 51 *CB3 81 VSS 112 VDDQ 143 VDDQ 173
21 CKE0 52 BA1 82 VDDID 113 *BA2
KEY
23 DQ16 53 DQ32 84 DQ57 115
24 DQ17 54 VDDQ 85 VDD 116
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
VSS
18 VSS 49 *CB2 79 DQ50 110 DQ15 141
VREF
Power supply for reference
VDDSPD
Serial EEPROM Power
Supply (2.3V to 3.6V)
144 *CB7 174
KEY
22 VDDQ
83 DQ56 114 DQ20
175
SDA
Serial data I/O
*A12
VSS
145
VSS
176
146 DQ36 177
DM7
SCL
Serial clock
25 DQS2 55 DQ33 86 DQS7 117 DQ21 147 DQ37 178
DQ62
DQ63
VDDQ
SA0
SA1
SA2
SA0 ~ 2
VDDID
NC
Address in EEPROM
VDD identification flag
No connection
26 VSS 56 DQS4 87 DQ58 118
27 A9 57 DQ34 88 DQ59 119
28 DQ18 58 VSS 89 VSS 120
29 A7 59 BA0 90 NC
SDA 122
SCL
A11
DM2
VDD
148
149
VDD
DM4
179
180
150 DQ38 181
*
These pins are not used in this module.
121 DQ22 151 DQ39 182
A8 152 VSS 183
123 DQ23 153 DQ44 184 VDDSPD
30 VDDQ 60 DQ35 91
31 DQ19 61 DQ40 92
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
Functional Block Diagram
CS1
CS0
DQS1
DM1
LDQS
LDM
CS
CS
D4
CS
D2
CS
D6
UDQS
UDM
UDQS
UDM
LDQS
LDM
DQS5
DM5
DQ8
DQ9
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 9
I/O 11
I/O 14
I/O 12
I/O 13
I/O 15
I/O 10
I/O 8
LDQS
LDM
I/O 7
I/O 5
I/O 0
I/O 2
I/O 3
I/O 1
I/O 4
I/O 6
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
I/O 9
I/O 11
I/O 14
I/O 12
I/O 13
I/O 15
D0
DQ10
DQ11
DQ12
DQ13
DQ14
I/O 5
I/O 10
I/O 8
LDQS
DQ15
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQS0
DM0
DQS4
DM4
LDM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 5
I/O 0
I/O 2
I/O 3
I/O 1
I/O 4
I/O 6
CS
D5
CS
D1
DQS3
DM3
UDQS
UDM
LDQS
LDM
DQS7
DM7
CS
D3
CS
D7
LDQS
LDM
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
UDQS
UDM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 9
I/O 6
I/O 4
I/O 1
I/O 3
I/O 2
I/O 0
I/O 5
I/O 7
UDQS
UDM
I/O 8
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 11
I/O 14
I/O 12
I/O 13
I/O 15
I/O 10
I/O 8
I/O 9
I/O 11
I/O 14
I/O 12
I/O 13
I/O 15
I/O 10
I/O 8
DQS2
DM2
I/O 7
LDQS
LDM
DQS6
DM6
UDQS
UDM
I/O 8
LDQS
LDM
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 7
I/O 5
I/O 0
I/O 2
I/O 3
I/O 1
I/O 4
I/O 6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 10
I/O 15
I/O 13
I/O 12
I/O 14
I/O 11
I/O 9
I/O 5
I/O 0
I/O 2
I/O 3
I/O 1
I/O 4
I/O 6
*Clock Net Wiring
clock Wining
SDRAM
Dram1
clock input
CK0/CK0
CK1/CK1
CK2/CK2
NC
4 SDRAMs
4 SDRAMs
Dram2
Cap.
R=120W
Card
Edge
Cap.
BA0 - BAN
A0 - AN
RAS
BA0-BAN: DDR SDRAMs D0 - D7
A0-AN: DDR SDRAMs D0 - D7
RAS: SDRAMs D0 - D7
Dram5
Dram6
CAS
CAS: SDRAMs D0 - D7
Serial PD
CKE0
CKE1
WE
CKE0: SDRAMs D0 - D3
CKE1: SDRAMs D4 - D7
WE: SDRAMs D0 - D7
SCL
WP
SDA
A0
A1
A2
SA0 SA1 SA2
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
V
DDSPD
/V
SPD
V
DD DDQ
D0 - D7
D0 - D7
VREF
4. VDDID strap connections
D0 - D7
D0 - D7
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ¹ VDDQ.
V
SS
V
DDID
Strap: see Note 4
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
8
Unit
V
V
V
VDDQ
TSTG
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V)
I/O Supply voltage
Symbol
VDD
Min
2.3
Max
2.7
Unit
Note
VDDQ
VREF
2.3
2.7
V
V
I/O Reference voltage
VDDQ/2-50mV VDDQ/2+50mV
1
2
4
4
I/O Termination voltage(system)
Input logic high voltage
V
VREF-0.04
VREF+0.04
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.35
V
TT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
II
VREF+0.15
-0.3
-0.3
0.3
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
V
V
3
5
1.15
-2
V
2
uA
uA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver)
IOH
IOL
IOH
-16.8
16.8
-9
mA
mA
mA
mA
;V
= V + 0.84V
OUT
TT
Output High Current(Normal strengh driver)
;V = V - 0.84V
OUT
TT
Output High Current(Half strengh driver)
;V = V + 0.45V
OUT
TT
Output High Current(Half strengh driver)
;V = V - 0.45V
IOL
9
OUT
TT
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.
2.V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to
TT
TT
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
DDR SDRAM SPEC Items and Test Conditions
Recommended operating conditions Unless Otherwise Noted, TA=0 to 70°C)
Conditions
Symbol
IDD0
Typical
Worst
Operating current - One bank Active-Precharge;
-
-
tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
IDD1
-
-
-
-
Percharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD2P
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
IDD2F
IDD2Q
-
-
-
-
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD3P
IDD3N
-
-
-
-
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once
per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst;
One bank active; address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =
133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A
IDD4R
IDD4W
-
-
-
-
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,
CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh
IDD5
-
-
-
-
-
-
Self refresh current; CKE =< 0.2V; External clock should be on;
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B
IDD6
Orerating current - Four bank operation ; Four bank interleaving with BL=4
IDD7A
-Refer to the following page for detailed test condition
Typical case: VDD = 2.5V, T = 25’C
Worst case : VDD = 2.7V, T = 10’C
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
DDR SDRAM I spec table
DD
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
Symbol
Unit
Notes
typical
620
720
320
420
380
360
440
940
980
980
16
worst
680
800
340
460
400
380
480
1060
1120
1080
16
typical
620
720
320
420
380
360
440
940
980
980
16
worst
680
800
340
460
400
380
480
1060
1120
1080
16
typical
540
640
260
360
320
300
360
780
820
900
16
worst
580
720
280
380
340
320
400
920
980
980
16
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
Normal
Low power
IDD7A
8
8
8
8
8
8
Optional
1600
1820
1600
1820
1300
1500
* Module I
was calculated on the basis of component I
DD
and can be differently measured according to DQ loading cap.
DD
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
IDD7A : Operating current: Four bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
AC Operating Conditions
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC) VREF + 0.31
VIL(AC)
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
VID(AC) 0.7
Input Crossing Point Voltage, CK and CK inputs
VIX(AC) 0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
Input Levels(VIH/VIL)
1.5
VREF+0.31/VREF-0.31
VREF
V
V
V
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Vtt
See Load Circuit
Vtt=0.5*VDDQ
RT=50W
Output
Z0=50W
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
CIN1
Min
36
29
26
33
8
Max
Unit
pF
pF
pF
pF
pF
pF
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS, WE )
Input capacitance(CKE0 , CKE1)
45
34
30
38
9
CIN2
Input capacitance( CS0, CS1)
CIN3
Input capacitance( CLK1, CLK1,CLK2,CLK2)
Data & DQS input/output capacitance(DQ0~DQ63)
Input capacitance(DM0~DM8)
CIN4
COUT
CIN5
8
9
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)
-TCA2(DDR266A) -TCB0(DDR266B) -TCA0 (DDR200)
Parameter
Symbol
Unit
Note
Min
65
Max
Min
65
Max
Min
70
80
48
20
20
15
2
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
Refresh row cycle time
Row active time
75
75
45
120K
45
120K
120K
ns
RAS to CAS delay
20
20
ns
Row precharge time
20
20
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
15
15
ns
2
2
tCK
tCK
tCK
ns
Last data in to Read command
Col. address to Col. address delay
tCDLR
tCCD
1
1
1
1
1
1
CL=2.0
CL=2.5
7.5
7.5
0.45
0.45
-0.75
-0.75
-
12
12
10
12
12
10
12
5
5
Clock cycle time
tCK
7.5
0.45
0.45
-0.75
-0.75
-
12
ns
Clock high level width
tCH
tCL
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.45
0.45
-0.8
-0.8
-
0.55
0.55
+0.8
+0.8
+0.6
1.1
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
tDQSCK
tAC
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tDSS
ns
5
2
0.9
0.4
0.75
0
0.9
0.4
0.75
0
0.9
0.4
0.75
0
tCK
tCK
tCK
ns
Read Postamble
0.6
0.6
0.6
CK to valid DQS-in
1.25
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.25
0.2
0.2
0.35
0.25
0.2
0.2
0.35
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tDSH
tDQSH
DQS-in low level width
tDQSL
tDSC
tIS
0.35
0.9
0.9
0.9
0.35
0.9
0.35
0.9
1.1
1.1
DQS-in cycle time
1.1
1.1
1.1
Address and Control Input setup time
Address and Control Input hold time
Data-out high impedence time from CK/CK
0.9
6
6
tIH
0.9
ns
tHZ
tACmin- tACmax tACmin tACmax tACmin tACmax
400ps - 400ps - 400ps - 400ps - 400ps - 400ps
ps
ps
Data-out low impedence time from CK/CK
tLZ
tACmin- tACmax tACmin tACmax tACmin tACmax
400ps
- 400ps - 400ps - 400ps - 400ps - 400ps
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
tSL(I)
tSL(IO)
tSL(O)
0.5
0.5
0.5
1.0
0.7
0.5
0.5
1.0
0.7
V/ns
V/ns
V/ns
V/ns
6
7
0.5
1.0
4.5
5
4.5
5
4.5
5
10
10
Output Slew Rate(x16)
tSL
0.7
(O)
Output Slew Rate Matching Ratio(rise to fall)
t
0.67
1.5
0.67
1.5
0.67
1.5
SLMR
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
-TCA2(DDR266A)
-TCB0(DDR266B)
-TCA0 (DDR200)
Parameter
Symbol
Unit Note
Min
15
Max
Min
15
Max
Min
16
Max
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tMRD
tDS
ns
0.5
0.5
1.75
10
0.5
0.5
1.75
10
0.6
0.6
2
ns
ns
7,8,9
7,8,9
tDH
DQ & DM input pulse width
tDIPW
tPDEX
tXSW
tXSA
ns
ns
Power down exit time
10
Exit self refresh to write command
Exit self refresh to bank active command
Exit self refresh to read command
95
116
80
ns
75
75
200
15.6
7.8
ns
4
tXSR
tREF
200
15.6
7.8
200
15.6
7.8
Cycle
us
64Mb, 128Mb
Refresh interval time
256Mb
1
1
us
tHPmin
-tQHS
tHPmin
-tQHS
tHPmin
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
ns
ns
5
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
Data hold skew factor
tQHS
0.75
0.75
0.8
ns
DQS write postamble time
tWPST
0.25
0.25
0.25
tCK
3
Note : 1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DINNs, tCL and tCH are ³ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half
period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
DtIS
(ps)
0
DtIH
(ps)
0
(V/ns)
0.5
0.4
+50
+100
+50
+100
0.3
This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
IS IH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
DtDS
(ps)
0
DtDH
(ps)
0
(V/ns)
0.5
0.4
+75
+150
+75
+150
0.3
This derating table is used to increase t /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
DS DH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
8. I/O Setup/Hold Plateau Derating
I/O Input Level
(mV)
DtDS
(ps)
DtDH
(ps)
± 280
+50
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
DtDS
(ps)
0
DtDH
(ps)
0
(ns/V)
0
±0.25
±0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
Command Truth Table
COMMAND
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
A11
A9 ~ A0
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Column
Address
(A0~A8)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
L
H
L
H
Column
Address
(A0~A8)
Write &
Column Address
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.9 June. 2001
184pin Unbuffered DDR SDRAM MODULE
M368L1714BT1
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.006
(133.350 ± 0.15)
0.118
(3.00)
5.077
(128.950)
1.45 ± 0.006
(36.83 ± 0.15)
0.78
(19.80)
A
B
2.500
0.10 M
C
B
A
0.145 Max
(3.67 Max)
1.95
(49.53)
2.55
(64.77)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118
(3.00)
0.250
(6.350)
0.157
(4.00)
0.039 ± 0.002
(1.000 ± 0.050)
0.26
(6.62)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575
(4.00)
0.10
Detail A
M
C
A
B
M
Detail B
Tolerances : ±0.005(.13) unless otherwise specified
The used device is 8Mx16 SDRAM, TSOP
SDRAM Part NO : K4H281638B-TC
Rev. 0.9 June. 2001
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