M368L3223DTL-CB0 [SAMSUNG]
DDR DRAM Module, 32MX64, 0.75ns, CMOS, DIMM-184;
| 型号： | M368L3223DTL-CB0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 32MX64, 0.75ns, CMOS, DIMM-184 动态存储器 双倍数据速率 |
| 文件： | 总12页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
256MB DDR SDRAM MODULE
(32Mx64 based on 32Mx8 DDR SDRAM)
Unbuffered 184pin DIMM
64-bit Non-ECC/Parity
Revision 0.2
May. 2002
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
Revision History
Revision 0 (Dec, 2001)
1. First release for internal usage
Revision 0.1 (Jan, 2002)
1. Changed to final version
2. Added tRAP(Active to Read w/ autoprecharge command)
Revision 0.2 (May, 2002)
1. Change pin location of A13 from pin 103 to pin 167
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
M368L3223DTL DDR SDRAM 184pin DIMM
32Mx64 DDR SDRAM 184pin DIMM based on 32Mx8
GENERAL DESCRIPTION
FEATURE
• Performance range
The Samsung M368L3223DTL is 32M bit x 64 Double Data
Rate SDRAM high density memory modules. The Samsung
M368L3223DTL consists of eight CMOS 32M x 8 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The M368L3223DTL
is Dual In-line Memory Modules and inten-ded for mounting
into 184pin edge connector sockets.
Part No.
Max Freq.
Interface
M368L3223DTL-C(L)B3 167MHz(6.0ns@CL=2.5)
M368L3223DTL-C(L)A2 133MHz(7.5ns@CL=2)
M368L3223DTL-C(L)B0 133MHz(7.5ns@CL=2.5)
SSTL_2
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1250 mil, double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN DESCRIPTION
Pin Front Pin Front Pin Front Pin Back Pin
Back Pin
Back
Pin Name
A0 ~ A12
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
VREF
DQ0
VSS
32
33 DQ24 63
34 VSS 64
35 DQ25 65
A5
62
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
/CK2
CK2
VDDQ 108
DQS6 109
DQ50
DQ51
VSS
93
94
95
96
97
98
99
100
101
102
103
VSS
DQ4
DQ5
124
125
126
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
*CB4
*CB5
VDDQ
CK0
/CK0
VSS
*DM8
A10
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
/RAS
DQ45
VDDQ
/CS0
*/CS1
DM5
Address input (Multiplexed)
Bank Select Address
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
Data input/output
DQ1
VDDQ 127
Data Strobe input/output
DQS0 36 DQS3 66
DM0
DQ6
DQ7
VSS
NC
128
129
130
131
132
133
134
DQ2
VDD
DQ3
NC
37
38
A4
VDD
67
68
CK0,CK0 ~ CK2, CK2 Clock input
VSS
CKE0
CS0
Clock enable input
39 DQ26 69
40 DQ27 70
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
VDD
Chip select input
RAS
Row address strobe
Column address strobe
Write enable
NC
41
42
43
44
A2
VSS
A1
*CB0
*CB1
VDD
71
72
73
74
75
76
NC
NC
VSS
DQ8
DQ9
CAS
104 VDDQ 135
WE
105
106
107
DQ12
DQ13
DM1
VDD
DQ14
DQ15
136
137
138
139
140
141
DM0 ~ DM7
VDD
Data - in mask
14 DQS1 45
15 VDDQ 46
16
17
18
19 DQ10
20 DQ11
21 CKE0
22 VDDQ
23 DQ16
24 DQ17
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
CK1
/CK1
VSS
47 *DQS8 77
DM6
VDDQ
VSS
48
49
50
51
52
A0
78
79
80
81
82
83
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
*CB2
VSS
*CB3
BA1
110
VREF
VDDSPD
Power supply for reference
111 *CKE1 142
112 VDDQ 143
*CB6
VDDQ
*CB7
Serial EEPROM Power
Supply (2.3V to 3.6V)
VDDID 113
*BA2
DQ20
A12
VSS
DQ21
A11
144
DQ56
DQ57
VDD
114
115
116
KEY
KEY
SDA
Serial data I/O
53 DQ32 84
54 VDDQ 85
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
SCL
Serial clock
DM7
25 DQS2 55 DQ33 86
DQS7 117
DQ62
DQ63
VDDQ
SA0
SA1
SA2
SA0 ~ 2
VDDID
NC
Address in EEPROM
VDD identification flag
No connection
26
27
VSS
A9
56 DQS4 87
57 DQ34 88
DQ58
DQ59
VSS
NC
SDA
SCL
118
119
120
121
122
123
DM2
VDD
DQ22
A8
DM4
28 DQ18
29 A7
30 VDDQ 60 DQ35 91
31 DQ19 61 DQ40 92
58
59
VSS
BA0
89
90
DQ38
DQ39
VSS
*
These pins are not used in this module.
DQ23
DQ44
184 VDDSPD
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
Functional Block Diagram
CS0
DQS0
DM0
DQS4
DM4
DM
I/O 7
I/O 6
I/O 1
I/O 0
CS DQS
D4
CS DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 5
I/O 4
I/O 3
I/O 2
DQS5
DM5
DQS1
DM1
DM
CS DQS
D5
CS DQS
D1
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
DQ8
DQ9
DQ10
DQ11
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 5
I/O 4
I/O 3
I/O 2
DQ12
DQ13
DQ14
DQ15
DQS6
DM6
DQS2
DM2
DM
CS DQS
D6
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D 2
DQ48
DQ49
DQ50
DQ51
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
* Clock Wiring
SDRAMs
Clock
Input
DQ52
DQ53
DQ54
DQ55
CK0/CK0
CK1/CK1
CK2/CK2
2 SDRAMs
3 SDRAMs
3 SDRAMs
DQS3
DM3
DQS7
DM7
CS
DM
DQS
CS
D3
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DQ56
DQ57
DQ58
DQ59
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ24
DQ25
DQ26
DQ27
D 7
*Clock Net Wiring
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
Dram1
Cap
R=120W
Dram3
*(Cap)
Serial PD
Card
Edge
BA0 - BA1
BA0-BA1: SDRAMs D0 - D7
A0-A13: SDRAMs D0 - D7
Cap
SCL
WP
A0 - A13
SDA
Dram5
A0
A1
A2
RAS
RAS : SDRAMs D0 - D7
Cap
CAS
CKE0
WE
CAS : SDRAMs D0 - D7
CKE: SDRAMs D0 - D7
WE: SDRAMs D0 - D7
SA0 SA1 SA2
*If two DRAMs are loaded,
Cap will replace DRAM3
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships
must be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
VDDSPD
SPD
VDD/VDDQ
D0 - D7
D0 - D7
VREF
VSS
D0 - D7
D0 - D7
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
12
Unit
V
V
V
VDDQ
TSTG
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V)
I/O Supply voltage
Symbol
VDD
Min
2.3
Max
2.7
Unit
Note
VDDQ
2.3
2.7
V
V
I/O Reference voltage
VREF
VDDQ/2-50mV VDDQ/2+50mV
1
2
4
4
I/O Termination voltage(system)
Input logic high voltage
V
VREF-0.04
VREF+0.04
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.35
V
TT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
II
VREF+0.15
V
Input logic low voltage
-0.3
-0.3
0.3
1.15
-2
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
V
V
3
5
V
2
uA
uA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver)
IOH
IOL
IOH
-16.8
16.8
-9
mA
mA
mA
;V
= V + 0.84V
TT
OUT
Output High Current(Normal strengh driver)
;V = V - 0.84V
OUT
TT
Output High Current(Half strengh driver)
;V = V + 0.45V
OUT
TT
Output High Current(Half strengh driver)
;V = V - 0.45V
IOL
9
mA
OUT
TT
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.
2.V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to
TT
TT
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
DDR SDRAM IDD spec table
Symbol
IDD0
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
720
960
24
640
880
24
640
880
24
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
200
160
280
440
1360
1360
1440
24
160
144
240
360
1120
1120
1320
24
160
144
240
360
1120
1120
1320
24
Normal
Low power
IDD7A
IDD6
12
12
12
Optional
2600
2240
2240
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
AC OPERATING CONDITIONS
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
0.7
Input Crossing Point Voltage, CK and CK inputs
0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
Input Levels(VIH/VIL)
1.5
VREF+0.31/VREF-0.31
VREF
V
V
V
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Vtt
See Load Circuit
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
Vtt=0.5*VDDQ
RT=50W
Output
Z0=50W
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE )
CIN1
49
57
pF
Input capacitance(CKE0)
CIN2
CIN3
CIN4
42
42
22
50
50
25
pF
pF
pF
Input capacitance( CS0)
Input capacitance( CLK0, CLK1,CLK2 )
Data & DQS input/output capacitance(DQ0~DQ63)
Input capacitance(DM0~DM8)
COUT
CIN5
6
6
8
8
pF
pF
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)
-TCB3
(DDR333)
-TCA2
(DDR266A)
-TCB0
(DDR266B)
Parameter
Symbol
Unit Note
Min
Max
Min
Max
Min
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
60
72
65
75
65
75
ns
ns
Refresh row cycle time
Row active time
42
70K
45
120K
45
120K
ns
RAS to CAS delay
18
20
20
ns
Row precharge time
18
20
20
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
12
15
15
ns
15
15
15
ns
Last data in to Read command
Col. address to Col. address delay
tWTR
tCCD
1
1
1
tCK
tCK
1
1
1
CL=2.0
CL=2.5
7.5
6
12
7.5
7.5
0.45
0.45
-0.75
-0.75
-
12
12
10
12
12
ns
ns
5
5
Clock cycle time
tCK
12
7.5
0.45
0.45
-0.75
-0.75
-
Clock high level width
tCH
tCL
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.55
0.55
+0.75
+0.75
0.5
0.55
0.55
+0.75
+0.75
0.5
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
tDQSCK
tAC
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
ns
5
2
0.9
0.4
0.75
0
0.9
0.4
0.75
0
1.1
0.9
0.4
0.75
0
1.1
tCK
tCK
tCK
ns
Read Postamble
0.6
0.6
0.6
CK to valid DQS-in
1.25
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.35
0.9
0.75
0.75
0.8
0.8
-0.7
-0.7
0.5
0.5
1.0
0.67
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
-0.75
-0.75
0.5
0.5
1.0
0.67
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
-0.75
-0.75
0.5
0.5
1.0
0.67
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
1.1
1.1
1.1
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
6
6
6
6
tIH
ns
tIS
ns
tIH
ns
tHZ
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
ns
tLZ
ns
tSL(I)
tSL(IO)
tSL(O)
V/ns
V/ns
V/ns
6
7
4.5
1.5
4.5
1.5
4.5
1.5
10
Output Slew Rate Matching Ratio(rise to fall) tSLMR
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
-TCB3
(DDR333)
-TCA2
(DDR266A)
-TCB0
(DDR266B)
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Min
Max
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tMRD
tDS
12
15
15
ns
ns
ns
0.45
0.5
0.5
7,8,9
7,8,9
tDH
0.45
0.5
0.5
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
tIPW
2.2
1.75
6
2.2
1.75
7.5
75
2.2
1.75
7.5
ns
ns
tDIPW
tPDEX
ns
Exit self refresh to non-Read command tXSNR
75
75
ns
4
Exit self refresh to read command
Refresh interval time
tXSRD
tREFI
200
7.8
200
7.8
200
7.8
tCK
us
1
5
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
-
-
-
ns
ns
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
Data hold skew factor
tQHS
0.55
0.6
0.75
0.6
0.75
0.6
ns
DQS write postamble time
tWPST
0.4
20
0.4
20
0.4
20
tCK
3
Active to Read with Auto precharge
command
tRAP
tDAL
Autoprecharge write recovery +
Precharge time
(tWR/tCK)
+
(tWR/tCK)
+
(tWR/tCK)
+
tCK
11
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are ³ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period
jitter due to crosstalk (tJIT(crosstalk) ) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
DtIS
(ps)
0
DtIH
(ps)
0
(V/ns)
0.5
0.4
+50
+100
+50
+100
0.3
This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
IS IH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
DtDS
(ps)
0
DtDH
(V/ns)
0.5
(ps)
0
0.4
+75
+150
+75
0.3
+150
This derating table is used to increase t /t
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
DS DH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
8. I/O Setup/Hold Plateau Derating
I/O Input Level
(mV)
DtDS
(ps)
+50
DtDH
(ps)
± 280
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
DtDS
(ps)
0
DtDH
(ps)
0
(ns/V)
0
±0.25
±0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
<Reference>
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
CK slew rate
DtIH/tIS
DtDSS/tDSH
DtAC/tDQSCK
DtLZ(min)
DtHZ(max)
(Single ended)
(ps)
(ps)
(ps)
(ps)
(ps)
1.0V/ns
0.75V/ns
0.5V/ns
0
0
0
0
0
+50
+100
+50
+100
+50
+100
-50
-100
+50
+100
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
Command Truth Table
A11, A12
A9 ~ A0
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
X
X
3
Bank Active & Row Addr.
H
H
V
V
Row Address
Column
Address
(A0~A9)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
L
H
L
H
Column
Address
(A0~A9)
Write &
Column Address
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
DM
H
H
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
X
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.2 May. 2002
M368L3223DTL
184pin Unbuffered DDR SDRAM MODULE
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118
(3.00)
5.077
(128.950)
1.25 ± 0.006
±0.15)
(31.75
A
B
2.500
0.10 M
C
B
A
2.55
(64.77)
1.95
(49.53)
0.07 Max
(1.20 Max)
0.050± 0.0039
(1.270 ± 0.10)
0.118
(3.00)
0.250
0.157
(4.00)
0.039 ± 0.002
(1.000 ± 0.050)
(6.350)
0.26
(6.62)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575
(4.00)
0.10
Detail A
M
C
A
B
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 32Mx8 DDR SDRAM, TSOP.
SDRAM Part NO : K4H560838D.
Rev. 0.2 May. 2002
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