M368L6423EUM-CC4 [SAMSUNG]
DDR DRAM Module, 64MX64, 0.65ns, CMOS, DIMM-184;
| 型号： | M368L6423EUM-CC4 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 64MX64, 0.65ns, CMOS, DIMM-184 动态存储器 双倍数据速率 |
| 文件： | 总19页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256MB, 512MB Unbuffered DIMM
DDR SDRAM
DDR SDRAM Unbuffered Module
(DDR400 Module)
184pin Unbuffered Module based on 256Mb E-die
64/72-bit ECC/Non ECC
66 TSOP(II) with Pb-Free
(RoHS compliant)
Revision 1.0
Oct. 2004
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
Revision History
Revision 1.0 (October, 2004)
- First release
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
184Pin Unbuffered DIMM based on 256Mb E-die (x8)
Ordering Information
Part Number
Density
256MB
512MB
256MB
512MB
Organization
32M x 64
64M x 64
32M x 72
64M x 72
Component Composition
Height
1,250mil
1,250mil
1,250mil
1,250mil
M368L3223EUM-C(L)CC/C4
M368L6423EUM-C(L)CC/C4
M381L3223EUM-C(L)CC/C4
M381L6423EUM-C(L)CC/C4
32Mx8( K4H560838E) * 8EA
32Mx8( K4H560838E) * 16EA
32Mx8( K4H560838E) * 9EA
32Mx8( K4H560838E) * 18EA
Operating Frequencies
CC(DDR400@CL=3)
200MHz
C4(DDR400@CL=3)
Speed @CL3
CL-tRCD-tRP
200MHz
3-4-4
3-3-3
Feature
• Power supply : Vdd: 2.6V ± 0.1V, Vddq: 2.6V ± 0.1V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil), single (256MB) and double(512MB) sided
• SSTL_2 Interface Pb-Free
• RoHS compliant
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
Pin Configuration (Front side/back side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
93
94
95
96
97
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
A6
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
98
99
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
9
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NC
VSS
VSS
A1
DQ8
DQ9
DQS1
VDDQ
CK1
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
/CK2
CK2
VDD
DM6
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
/CK1
VSS
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
CB6
VDDQ
CB7
KEY
KEY
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
DM4
DQ38
DQ39
VSS
NC
SDA
SCL
DQ23
DQ44
VDDSPD
Note :
1. * : These pins are not used in this module.
2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module, and are not used on x64 module.
3. Pins 111, 158 are NC for 1 Row Module[M368(81)L3223EUM] & used for 2 Row Moduel[M368(81)L6423EUM]
Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A12
Address input (Multiplexed) DM0 ~ 7, 8(for ECC) Data - in mask
BA0 ~ BA1
Bank Select Address
Data input/output
Data Strobe input/output
Clock input
VDD
Power supply (2.6V)
DQ0 ~ DQ63
VDDQ
VSS
Power Supply for DQS(2.6V)
Ground
DQS0 ~ DQS8
CK0,CK0 ~ CK2, CK2
VREF
VDDSPD
SDA
Power supply for reference
CKE0, CKE1(for double banks) Clock enable input
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
CS0, CS1(for double banks)
Chip select input
RAS
Row address strobe
Column address strobe
Write enable
SCL
Serial clock
CAS
SA0 ~ 2
NC
Address in EEPROM
No connection
WE
CB0 ~ CB7 (for x72 module)
Check bit(Data-in/data-out)
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
256MB, 32M x 64 Non ECC Module (M368L3223EUM) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS0
DQS0
DM0
DQS4
DM4
DM
I/O 7
CS DQS
D4
DQS
CS
D0
DM
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Serial PD
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
SCL
WP
SDA
A0
A1
A2
SA0 SA1 SA2
DQS5
DM5
DQS1
DM1
DQS
DM
CS
D5
DQS
CS
D1
DM
VDDSPD
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ8
DQ9
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
SPD
VDD/VDDQ
D0 - D7
D0 - D7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VREF
VSS
D0 - D7
D0 - D7
DQS6
DM6
DQS2
DM2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
CS DQS
D2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
*Clock Net Wiring
D3/D0/D6
Cap/Cap/Cap
D4/D1/D7
DQS7
DM7
DQS3
DM3
R=120
Ω
CK0/1/2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
Card
Edge
Cap/Cap/Cap
D5/D2/Cap
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
*If two DRAMs are loaded,
Cap will replace DRAM
Cap/Cap/Cap
Notes :
BA0 - BA1
BA0-BA1 : DDR SDRAMs D0 - D7
A0-A12 : DDR SDRAMs D0 - D7
RAS : DDR SDRAMs D0 - D7
CAS : DDR SDRAMs D0 - D7
CKE : DDR SDRAMs D0 - D7
WE : DDR SDRAMs D0 - D7
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
Clock Wiring
A0 - A12
RAS
Clock
Input
SDRAMs
3 SDRAMs
3 SDRAMs
2 SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
CAS
CKE0
WE
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
256MB, 32M x 72 ECC Module (M381L3223EUM) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS0
DQS0
DM0
DQS4
DM4
DM
I/O 7
CS DQS
D4
DQS
CS
D0
DM
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Serial PD
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
SCL
WP
SDA
A0
A1
A2
SA0 SA1 SA2
DQS5
DM5
DQS1
DM1
DQS
DM
CS
D5
DQS
CS
D1
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ8
DQ9
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VDDSPD
SPD
VDD/VDDQ
D0 - D8
D0 - D8
VREF
VSS
D0 - D8
D0 - D8
DQS6
DM6
DQS2
DM2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D3/D0/D6
Cap/Cap/Cap
D4/D1/D7
DQS7
DM7
DQS3
DM3
R=120Ω
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
CK0/1/2
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Card
Edge
Cap/Cap/Cap
D5/D2/D8
Cap/Cap/Cap
DQS8
DM8
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D8
DQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
Notes :
BA0 - BA1
A0 - A12
RAS
BA0-BA1 : DDR SDRAMs D0 - D8
A0-A12 : DDR SDRAMs D0 - D8
RAS : DDR SDRAMs D0 - D8
CAS : DDR SDRAMs D0 - D8
CKE : DDR SDRAMs D0 - D8
WE : DDR SDRAMs D0 - D8
Clock Wiring
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
Clock
Input
SDRAMs
3 SDRAMs
3 SDRAMs
3 SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
CAS
CKE0
WE
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
512MB, 64M x 64 Non ECC Module (M368L6423EUM) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS1
CS0
DQS4
DM4
DQS0
DM0
DQS
DM
I/O 7
CS
D4
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DM
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D0
CS DQS
D8
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D12
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS5
DM5
DQS1
DM1
DM
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D5
CS
DQS
DM
DQS
DQS
CS
CS
D1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ8
DQ9
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D13
D9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS6
DM6
DQS2
DM2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D14
DM
DQS
CS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D10
DQS7
DM7
DQS3
DM3
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D11
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
Serial PD
BA0 - BA1
A0 - A12
RAS
BA0-BA1 : DDR SDRAMs D0 - D15
A0-A12 : DDR SDRAMs D0 - D15
RAS : DDR SDRAMs D0 - D15
CAS : DDR SDRAMs D0 - D15
CKE : DDR SDRAMs D8 - D15
CKE : DDR SDRAMs D0 - D7
Clock Wiring
SCL
WP
Clock
SDA
SDRAMs
Input
A0
A1
A2
4 SDRAMs
6 SDRAMs
6 SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
CAS
SA0 SA1 SA2
CKE1
CKE0
*Clock Net Wiring
D3/D0/D5
WE
WE : DDR SDRAMs D0 - D15
D4/D1/D6
Notes :
VDDSPD
SPD
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 3.0 Ohms +
5%
R=120
Ω
*
Cap/D2/D7
VDD/VDDQ
D0 - D15
D0 - D15
CK0/1/2
Card
Edge
*
Cap/D8/D13
VREF
VSS
D0 - D15
D0 - D15
D11/D9/D14
*If four DRAMs are loaded,
Cap will replace DRAM
D12/D10/D15
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
512MB, 64M x 72 ECC Module (M381L6423EUM) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS1
CS0
DQS4
DM4
DQS0
DM0
DQS
DM
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D4
CS
DM
I/O 7
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D0
CS DQS
D9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D13
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS5
DM5
DQS1
DM1
DM
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
D5
CS DQS
D14
DM
DQS
DQS
CS
CS
D1
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D10
DQS6
DM6
DQS2
DM2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D15
DM
DQS
CS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D11
DQS7
DM7
DQS3
DM3
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D12
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DM8
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D8
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D17
DQS
Serial PD
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
SCL
WP
SDA
A0
A1
A2
SA0 SA1 SA2
D3/D0/D5
BA0 - BA1
BA0-BA1 : DDR SDRAMs D0 - D17
A0-A12 : DDR SDRAMs D0 - D17
RAS : DDR SDRAMs D0 - D17
CAS : DDR SDRAMs D0 - D17
CKE : DDR SDRAMs D9 - D17
CKE : DDR SDRAMs D0 - D8
* Clock Wiring
A0 - A12
RAS
D4/D1/D6
D8/D2/D7
Clock
Input
SDRAMs
R=120
Ω
6 SDRAMs
6 SDRAMs
6 SDRAMs
CK0/CK0
CK1/CK1
CK2/CK2
CAS
CK0/1/2
Card
Edge
D17/D9/D14
CKE1
CKE0
D12/D10/D15
WE
WE : DDR SDRAMs D0 - D17
*D8, D17 is assigned for ECC Comp.
D13/D11/D16
VDDSPD
Notes :
SPD
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 3.0 Ohms +
5%
VDD/VDDQ
D0 - D17
D0 - D17
VREF
VSS
D0 - D17
D0 - D17
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
VDD, VDDQ
TSTG
PD
-1.0 ~ 3.6
-55 ~ +150
V
°C
W
Power dissipation
1.5 * # of component
50
Short circuit current
IOS
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
2.7
Unit
V
Note
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.5
5
5
1
2
I/O Supply voltage
VDDQ
VREF
VTT
2.5
2.7
V
I/O Reference voltage
I/O Termination voltage(system)
0.49*VDDQ
VREF-0.04
0.51*VDDQ
VREF+0.04
V
V
Input logic high voltage
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VI(Ratio)
II
VREF+0.15
-0.3
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.4
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
-0.3
V
0.36
0.71
-2
V
3
4
-
2
uA
uA
mA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOH
-16.8
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
IOH
IOL
16.8
-9
mA
mA
mA
9
Note :
1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.
Peak-to peak noise on VREF may not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
5. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at the DRAM
generated from any source other than the DRAM itself may not exceed the DC voltage range of 2.6V +/-100mV.
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
DDR SDRAM IDD spec table
(VDD=2.7V, T = 10°C)
M368L3223EUM
Symbol
M381L3223EUM
Unit
Notes
CC(DDR400@CL=3) C4(DDR400@CL=3) CC(DDR400@CL=3) C4(DDR400@CL=3)
IDD0
IDD1
840
1040
35
800
1040
35
950
1170
40
900
1170
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
240
200
440
600
1480
1520
1440
24
240
200
440
600
1480
1520
1440
24
270
230
500
680
1670
1710
1620
27
270
230
500
680
1670
1710
1620
27
IDD6
Normal
Low power
IDD7A
12
12
14
14
Optional
2480
2320
2790
2610
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
(VDD=2.7V, T = 10°C)
M368L6423EUM
M381L6423EUM
Symbol
Unit
Notes
CC(DDR400@CL=3) C4(DDR400@CL=3) CC(DDR400@CL=3) C4(DDR400@CL=3)
IDD0
IDD1
1440
1640
65
1400
1640
65
1620
1850
75
1580
1850
75
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
480
480
540
450
990
1350
2340
2390
2300
54
540
400
400
450
880
880
990
1200
2080
2120
2040
48
1200
2080
2120
2040
48
1350
2340
2390
2300
54
IDD6
Normal
Low power
IDD7A
24
24
27
27
Optional
3080
2920
3470
3290
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
AC Operating Conditions
Max
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VREF + 0.31
VREF - 0.31
VDDQ+0.6
V
0.7
V
1
2
Input Crossing Point Voltage, CK and CK inputs
0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD=2.6V, VDDQ=2.6V, TA= 25°C, f=1MHz)
M368L3223EUM
M381L3223EUM
Parameter
Symbol
Unit
Min
49
42
42
25
6
Max
57
50
50
30
7
Min
51
44
44
25
6
Max
60
53
53
30
7
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
Input capacitance( CS0)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
6
7
6
7
-
-
6
7
M368L6423EUM
M381L6423EUM
Parameter
Symbol
Unit
Min
65
42
42
28
10
10
-
Max
81
50
50
34
12
12
-
Min
69
44
44
28
10
10
10
Max
87
53
53
34
12
12
12
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
AC Timing Parameters and Specifications
CC(DDR400@CL=3)
C4(DDR400@CL=3)
Parameter
Symbol
Unit
Note
Min
55
Max
Min
60
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
Refresh row cycle time
Row active time
70
70
40
70K
40
70K
ns
RAS to CAS delay
15
18
ns
Row precharge time
15
18
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
10
10
ns
15
15
ns
Internal write to read command delay
tWTR
2
2
tCK
ns
CL=3.0
CL=2.5
5
10
12
5
10
12
Clock cycle time
tCK
16
13
6
6
ns
Clock high level width
Clock low level width
tCH
tCL
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
tCK
tCK
ns
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tWPST
tDSS
ns
0.9
0.4
0.72
0
1.1
0.9
0.4
0.72
0
1.1
tCK
tCK
tCK
ps
Read Postamble
0.6
0.6
CK to valid DQS-in
1.28
1.28
Write preamble setup time
Write preamble
5
4
0.25
0.4
0.2
0.2
0.35
0.25
0.4
0.2
0.2
0.35
tCK
tCK
tCK
tCK
tCK
tCK
ns
Write postamble
0.6
0.6
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tDSH
tDQSH
DQS-in low level width
tDQSL
tIS
0.35
0.6
0.35
0.6
Address and Control Input setup time
Address and Control Input hold time
h,7~10
h,7~10
tIH
0.6
0.6
ns
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
tHZ
tLZ
-
tAC max
tAC max
-
tAC max
tAC max
ns
3
3
tAC min
2
tAC min
2
ns
tMRD
tDS
tCK
ns
DQ & DM setup time to DQS, slew rate 0.5V/ns
DQ & DM hold time to DQS, slew rate 0.5V/ns
DQ & DM input pulse width
0.4
0.4
i, j
i, j
9
tDH
0.4
0.4
ns
tDIPW
tIPW
1.75
2.2
1.75
2.2
ns
Control & Address input pulse width for each input
ns
9
Up to 128Mb
Refresh interval time
15.6
7.8
15.6
7.8
us
tREFI
6
256Mb, 512Mb, 1Gb
us
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
-
ns
ns
12
min
tCH/tCL
min
tCH/tCL
11, 12
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
CC(DDR400@CL=3)
C4(DDR400@CL=3)
Parameter
Data hold skew factor
Symbol
Unit
Note
Min
Max
0.5
-
Min
Max
0.5
-
tQHS
tDAL
ns
ns
12
14
15
Auto Precharge write recovery + precharge time
Exit self refresh to non-READ command
Exit self refresh to READ command
-
-
tXSNR
tXSRD
75
75
ns
200
-
200
-
tCK
Component Notes
1.VID is the magnitude of the difference between the input level on CK and the input level on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
3. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a
specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).
4. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
5. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
6. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
7. For command/address input slew rate ≥ 0.5 V/ns
8. For CK & CK slew rate ≥ 0.5 V/ns
9. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
10. Slew Rate is measured between VOH(ac) and VOL(ac).
11. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
12. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
13. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
14. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR400(CC) at CL=3 and
tCK=5ns tDAL = (15 ns / 5 ns) + (15 ns/ 5ns) = (3) + (3)
tDAL = 6 clocks
15. In all circumstances, tXSNR can be satisfied using tXSNR=tRFCmin+1*tCK
16. The only time that the clock frequency is allowed to change is during self-refresh mode.
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR400 devices to ensure proper system perfor-
mance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR400
PARAMETER
SYMBOL
DCSLEW
MIN
0.5
MAX
4.0
Units
V/ns
Notes
a, k
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tIS
0
tIH
0
Units
ps
Notes
h
h
h
0.4 V/ns
+50
+100
0
ps
0.3 V/ns
0
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tDS
0
tDH
0
Units
ps
Notes
j
j
j
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
+/- 0.0 V/ns
tDS
0
tDH
0
Units
ps
Notes
i
i
i
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X8 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g
b,c,d,f,g
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g
b,c,d,f,g
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS DDR400
PARAMETER
Output Slew Rate Matching Ratio (Pullup to Pulldown)
MIN
-
MAX
-
Notes
e,k
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
Test point
Output
50Ω
VSSQ
Figure 1 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
VDDQ
50Ω
Output
Test point
Figure 2 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
For Maximum slew rate, only one DQ is switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.6V, typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.5V, slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
i. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotony.
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
A0 ~ A9
Note
COMMAND
CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP
A11, A12
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
X
3
Bank Active & Row Addr.
H
V
Row Address
(A0~A9, A11, A12)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
4
4
Column
Address
H
X
L
H
L
H
V
V
H
Write &
Column Address
L
4
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
H
L
Entry
H
Precharge Power Down Mode
X
H
L
Exit
L
H
H
H
X
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
Physical Dimensions : 32M x 64 (M368L3223EUM), 32M x 72 (M381L3223EUM)
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.006
(133.350 ± 0.15)
0.118
(3.00)
5.077
(128.950)
1.25 ± 0.006
±0.15)
(31.75
N/A
(for x64)
ECC
(for x72)
A
B
N/A
(for x64)
2.500
0.10 M
C
B
A
ECC
(for x72)
1.95
(49.53)
2.55
(64.77)
0.07 Max
(1.20 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118
(3.00)
0.250
(6.350)
0.157
(4.00)
0.039 ± 0.002
(1.000 ± 0.050)
0.26
(6.62)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575
(4.00)
0.10
Detail A
M
C
A
B
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 32Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part NO : K4H560838E.
Revision 1.0 Oct. 2004
256MB, 512MB Unbuffered DIMM
DDR SDRAM
Physical Dimensions : 64M x 64 (M368L6423EUM), 64M x 72 (M381L6423EUM)
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.006
(133.350 ± 0.15)
0.118
(3.00)
5.077
(128.950)
1.25 ± 0.006
±0.15)
(31.75
N/A
(for x64)
ECC
(for x72)
A
B
2.500
0.10 M
C
B
A
0.145 Max
(3.67 Max)
1.95
(49.53)
2.55
(64.77)
N/A
(for x64)
ECC
(for x72)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118
(3.00)
0.250
(6.350)
0.157
(4.00)
0.039 ± 0.002
(1.000 ± 0.050)
0.26
(6.62)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575
(4.00)
0.10
Detail A
M
C
A
B
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 32Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part NO : K4H560838E
Revision 1.0 Oct. 2004
相关型号：
M368L6423FTN-CB3B0
184pin Unbuffered Module based on 256Mb F-die with 64/72-bit Non-ECC / ECC
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