M377S0823ET3-C1H [SAMSUNG]
Synchronous DRAM Module, 8MX72, 6ns, CMOS, DIMM-168;
| 型号： | M377S0823ET3-C1H |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM Module, 8MX72, 6ns, CMOS, DIMM-168 时钟 动态存储器 内存集成电路 |
| 文件： | 总13页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PC100 Registered DIMM
M377S0823ET3
Revision History
Revision 0.1 (January 15, 2001)
- Drive IC is changed from ALVC162835 to ALVCF162835 and PLL is also changed from CDC2509 to CDCF2509.
Revision 0.2 (Sep., 2001)
•
Changed the Notes in Operating AC Parameter.
< Before >
5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
< After >
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
M377S0823ET3 SDRAM DIMM (Intel 1.2 ver. Base)
8Mx72 SDRAM DIMM with PLL & Register based on 8Mx8, 4Banks 4K Ref., 3.3V Synchronous DRAMs with SPD
FEATURE
GENERAL DESCRIPTION
• Performance range
The Samsung M377S0823ET3 is a 8M bit x 72 Synchronous
Dynamic RAM high density memory module. The Samsung
M377S0823ET3 consists of nine CMOS 8Mx8 bit Synchronous
DRAMs in TSOP-II 400mil packages, two 18-bits Drive ICs for
input control signal, one PLL in 24-pin TSSOP package for
clock and one 2K EEPROM in 8-pin TSSOP package for Serial
Presence Detect on a 168pin glass-epoxy substrate. Two
0.22uF and one 0.0022uF decoupling capacitors are mounted
on the printed circuit board in parallel for each SDRAM. The
M377S0823ET3 is a Dual In-line Memory Module and is
intented for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable latencies
allows the same device to be useful for a variety of high band-
width, high performance memory system applications.
Part No.
Max Freq. (Speed)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
M377S0823ET3-C1H
M377S0823ET3-C1L
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,500mil) , double sided component
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin
Pin Front Pin Front
Front Pin Back Pin Back Pin Back
Pin Name
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
CLK0
Function
Address input (Multiplexed)
Select bank
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
1
2
3
4
5
VSS
29 DQM1
DQ18 85
VSS
113 DQM5 141 DQ50
DQ0 30
DQ1 31
DQ2 32
DQ3 33
CS0
DU
VSS
A0
DQ19 86 DQ32 114 *CS1 142 DQ51
Data input/output
Check bit (Data-in/data-out)
Clock input
VDD
87 DQ33 115 RAS 143
VDD
DQ20 88 DQ34 116
NC 89 DQ35 117
*VREF 90 118
*CKE1 91 DQ36 119
92 DQ37 120
DQ21 93 DQ38 121
VSS
A1
A3
A5
A7
A9
144 DQ52
145
NC
6
VDD
34
A2
VDD
146 *VREF
147 REGE
CKE0
Clock enable input
Chip select input
Row address strobe
Colume address strobe
Write enable
7
8
9
DQ4 35
DQ5 36
DQ6 37
A4
A6
A8
VSS
148
VSS
CS0, CS2
RAS
149 DQ53
10
11
12
13
DQ7 38 A10/AP
DQ22 94 DQ39 122 BA0 150 DQ54
CAS
DQ8 39
40
DQ9 41
BA1
VDD
VDD
DQ23 95 DQ40 123
96 124
A11
VDD
151 DQ55
152
WE
VSS
VSS
VSS
VSS
DQ24 97 DQ41 125 *CLK1 153 DQ56
DQ25 98 DQ42 126 *A12 154 DQ57
DQM0 ~ 7
VDD
DQM
14 DQ10 42 CLK0
Power supply (3.3V)
Ground
15 DQ11 43
16 DQ12 44
17 DQ13 45
VSS
DU
CS2
DQ26 99 DQ43 127
VSS
155 DQ58
VSS
72 DQ27 100 DQ44 128 CKE0 156 DQ59
73
74
75
76
77
78
79
80
81
82
VDD 101 DQ45 129 *CS3 157
VDD
*VREF
Power supply for reference
Register enable
Serial data I/O
18
VDD
46 DQM2
DQ28 102 130 DQM6 158 DQ60
VDD
REGE
SDA
19 DQ14 47 DQM3
DQ29 103 DQ46 131 DQM7 159 DQ61
DQ30 104 DQ47 132 *A13 160 DQ62
20 DQ15 48
DU
VDD
NC
SCL
Serial clock
21
22
23
24
25
26
27
CB0
CB1
VSS
NC
NC
VDD
WE
49
50
51
52
53
54
DQ31 105 CB4 133
VDD
NC
NC
161 DQ63
162
163 *CLK3
NC
137 CB7 165 **SA0
138 166 **SA1
VSS
106 CB5 134
VSS
SA0 ~ 2
DU
Address in EEPROM
Don¢t use
NC
*CLK2 107
VSS
NC
NC
135
CB2
CB3
VSS
NC
NC
108
109
136 CB6 164
NC
No connection
**SDA 110
VDD
VSS
*
These pins are not used in this module.
** These pins should be NC in the system
55 DQ16 83 **SCL 111 CAS 139 DQ48 167 **SA2
84
28 DQM0 56 DQ17
VDD 112 DQM4 140 DQ49 168
VDD
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
PIN CONFIGURATION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tss prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
A0 ~ A11
BA0 ~ BA1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data input/output mask
The device operates in the transparent mode when REGE is low. When REGE is high,
the device operates in the registered mode. In registered mode, the Address and con-
trol inputs are latched if CLK is held at a high or low logic level. the inputs are stored in
the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm
Resistor on PCB. So if REGE of module is floating, this module will be operated as reg-
istered mode.
REGE
Register enable
DQ0 ~ 63
CB0 ~ 7
VDD/VSS
Data input/output
Check bit
Data inputs/outputs are multiplexed on the same pins.
Check bits for ECC.
Power supply/ground
Power and ground for the input buffers and the core logic.
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
FUNCTIONAL BLOCK DIAGRAM
PCLK0
BCS0
BCKE0
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
·
·
D0
·
·
·
·
·
·
·
B0A0~B0A11,BBA0~1,BRAS,BCAS,BWE
BDQM0
DQ0~7
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D1
D2
D3
DQ8~15
10W
PCLK1
·
·
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM1
·
CB0~7
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BCS2
·
·
BDQM2
DQ16~23
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
·
PCLK3
D4
D5
·
·
BDQM3
DQ24~31
DQ32~39
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
·
BDQM4
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
D6
D7
D8
·
BDQM5
DQ40~47
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
·
·
·
BDQM6
DQ48~55
DQ56~63
10W
CLK
CS
CKE
Add,CTL
DQM
DQ0~7
BDQM7
10W
Notes : Address/Control Signals are connected to D2 through 100 ohms resistor.
VSS
B0A0~B0A9
A0~A9
V
DD
SN74ALVCF162835
BRAS,BCAS,BWE
BDQM0,1,4,5
BCS0
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
RAS,CAS,WE
DQM0,1,4,5
CS0
PCLK0
PCLK1
PCLK2
PCLK3
CDCF2509
CLK
LE
REGE
10
W
OE
PCLK2
CLK0
FBOU
12pF
10kW
*2
Cb
V
DD
* Note
1. Unused clock termination : 10
2. The actual values of Cb will depend upon the PLL chosen.
SN74ALVCF162835
W
and 12pF
A10,A11,BA0~1
CS2
B0A10,B0A11,BBA0~1
BCS2
CKE0
BCKE0
DQM2,3,6,7
BDQM2,3,6,7
Serial PD
SCL
SDA
WP
LE
A0 A1 A2
47KW
OE
SA0 SA1 SA2
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
*2
REG
*1
DOUT
Control Signal(RAS,CAS,WE)
*3
*1. Register Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
RAS
CAS
WE
*2. Register Output
RAS
td
tr
td
tr
CAS
WE
*3. SDRAM
CAS latency(refer to *1)
=2CLK+1CLK
1CLK
tSAC
tRAC(refer to *1)
tRAC(refer to *2)
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
DQ
CAS latency(refer to *2)
=2CLK
tRDL
Row Active
Precharge
Command
Write
Command
Row Active
Read
Command
Precharge
Command
td, tr = Delay of register (74ALVC162835)
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal
because of the buffering in register (74ALVC162835). Therefore, Input/Output signals of read/write function should be
issued 1CLK earlier as compared to Unbuffered DIMMs.
2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Don¢t care
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
9
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended Operating Conditions (Voltage Referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input high voltage
Input low voltage
3.0
VDDQ+0.3
V
1
VIL
0
-
0.8
-
V
2
Output high voltage
Output low voltage
Input leakage current
VOH
VOL
ILI
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
Notes :
1. VIH (max) = 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A11)
CIN1
CIN2
-
-
-
-
-
-
-
-
-
12
12
12
12
12
12
12
12
12
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0)
CIN3
Input capacitance (CLK0)
CIN4
Input capacitance (CS0, CS2)
CIN5
Input capacitance (DQM0 ~ DQM7)
Input capacitance (BA0 ~ BA1)
Data input/output capacitance (DQ0 ~ DQ63)
Data input/output capacitance (CB0 ~ CB7)
CIN6
CIN7
COUT
COUT1
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
Parameter
Symbol
Test Condition
Unit Note
-1H
-1L
Burst length = 1
tRC ³ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
1,130
mA
mA
1
3
ICC2P
CKE £ VIL(max), tCC = 10ns
359
11
Precharge standby current in
power-down mode
ICC2PS
CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2N
485
56
Precharge standby current in
non power-down mode
mA
mA
3
3
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC2NS
ICC3P
CKE £ VIL(max), tCC = 10ns
377
29
Active standby current in
power-down mode
ICC3PS
CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3N
575
137
mA
mA
3
3
Active standby current in non
power-down mode
CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥
Input signals are stable
ICC3NS
IO = 0mA
Operating current
(Burst mode)
Page burst
4Banks activated
tCCD=2CLK
ICC4
1,355
mA
1
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
CKE £ 0.2V
1,625
359
mA
mA
2
3
Self refresh current
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Measured with 1 PLL & 2 Drive ICs.
4. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50W
50pF
50pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-1H
20
20
20
50
-1L
20
20
20
50
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
ns
ns
1
1
1
1
Row precharge time
ns
tRAS(min)
tRAS(max)
tRC(min)
ns
Row active time
100
2
us
Row cycle time
70
70
ns
1
2,5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
CLK
-
2 CLK + 20 ns
1
1
1
2
1
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
-1H
-1L
Parameter
Symbol
Unit
ns
Note
1
Min
10
Max
Min
10
Max
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CLK cycle time
tCC
1000
1000
10
12
6
6
6
7
CLK to valid
output delay
tSAC
ns
1,2
1,2
3
3
3
3
2
1
1
3
3
3
3
2
1
1
Output data
hold time
tOH
ns
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
tSH
tSLZ
Input hold time
CLK to output in Low-Z
CAS latency=3
CAS latency=2
6
6
6
7
CLK to output
in Hi-Z
tSHZ
ns
1
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
SIMPLIFIEDTRUTHTABLE
A11,
A9 ~ A0
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
Register
Refresh
Mode register set
Auto refresh
H
X
H
L
L
L
L
L
X
OP code
1,2
3
H
L
L
L
L
H
X
X
X
X
Entry
3
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
refresh
Exit
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Column
address
(A0 ~ A8)
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
L
L
H
H
L
L
H
L
Column
address
(A0 ~ A8)
Write &
column address
H
X
X
V
H
X
L
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
Bank selection
All banks
V
X
X
H
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
No operation command
( V=Valid, X=Don¢t care, H=Logic high, L=Logic low)
Notes : 1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.250
(133.350)
0.054
(1.372)
5.014
0.118
(3.000)
(127.350)
R 0.079
(R 2.000)
0.157 ± 0.004
(4.000 ± 0.100)
PLL
B
C
A
.118DIA ± 0.004
(3.000DIA ± 0.100)
0.250
(6.350)
0.250
(6.350)
0.350
(8.890)
1.450
(36.830)
2.150
(54.61)
.450
(11.430)
4.550
(115.57)
0.150 Max
(3.81 Max)
REG
REG
0.050 ± 0.0039
(1.270 ± 0.10)
0.250
0.250
0.039 ± 0.002
(1.000 ± 0.050)
(6.350)
(6.350)
0.123 ± 0.005
(3.125 ± 0.125)
0.123 ± 0.005
(3.125 ± 0.125)
0.008 ±0.006
(0.200 ±0.150)
0.050
(1.270)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Detail A
Detail B
Detail C
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 8Mx8 SDRAM, TSOP
SDRAM Part No. : K4S640832E
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
M377S0823ET3-C1H/C1L(1.2ver)
•Organization : 8MX72
•Composition : 8MX8 *9
•Used component part # : K4S640832E-TC1H/C1L
•# of rows in module : 1 row
•# of banks in component : 4 banks
•Feature : 1,500 mil height & double sided component
•Refresh : 4K/64ms
•Contents :
Function Supported
-1H -1L
Hex value
Byte #
Function described
Note
-1H
-1L
0
1
# of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
128bytes
80h
08h
04h
0Ch
09h
01h
48h
00h
01h
256bytes (2K-bit)
2
SDRAM
12
3
# of row address on this assembly
1
1
4
# of column address on this assembly
# of module Rows on this assembly
9
5
1 Row
72 bits
-
6
Data width of this assembly
7
...... Data width of this assembly
8
Voltage interface standard of this assembly
SDRAM cycle time from clock @CAS latency of 3
SDRAM access time from clock @CAS latency of 3
DIMM configuration type
LVTTL
9
10ns
6ns
10ns
6ns
A0h
60h
A0h
60h
2
2
10
11
12
13
14
15
16
17
18
19
20
ECC
02h
80h
08h
08h
01h
8Fh
04h
06h
01h
01h
Refresh rate & type
15.625us, support self refresh
Primary SDRAM width
x8
x8
Error checking SDRAM width
Minimum clock delay for back-to-back random column address
SDRAM device attributes : Burst lengths supported
SDRAM device attributes : # of banks on SDRAM device
SDRAM device attributes : CAS latency
SDRAM device attributes : CS latency
SDRAM device attributes : Write latency
tCCD = 1CLK
1, 2, 4, 8 & full page
4 banks
2 & 3
0 CLK
0 CLK
Registered/Buffered DQM,
address & control inputs
21
SDRAM module attributes
1Fh
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
22
SDRAM device attributes : General
0Eh
23
24
25
26
27
28
29
30
31
32
33
34
SDRAM cycle time @CAS latency of 2
SDRAM access time @CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time @CAS latency of 1
Minimum row precharge time (=tRP)
Minimum row active to row active delay (=tRRD)
Minimum RAS to CAS delay (=tRCD)
Minimum activate precharge time (=tRAS)
Module Row density
10ns
6ns
-
12ns
7ns
-
A0h
60h
00h
00h
14h
14h
14h
32h
C0h
70h
00h
00h
14h
14h
14h
32h
2
2
2
2
-
-
20ns
20ns
20ns
50ns
20ns
20ns
20ns
50ns
1 Row of 64MB
10h
20h
10h
20h
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
2ns
1ns
2ns
Rev.02 Sept. 2001
PC100 Registered DIMM
M377S0823ET3
SERIAL PRESENCE DETECT INFORMATION
Function Supported
-1H -1L
Hex value
Byte #
Function described
Note
-1H
-1L
35
Data signal input hold time
1ns
-
10h
00h
12h
36~61 Superset information (maybe used in future)
62
63
64
SPD data revision code
Current release Intel spd 1.2A
Checksum for bytes 0 ~ 62
Manufacturer JEDEC ID code
-
36h
66h
Samsung
CEh
00h
01h
4Dh
33h
20h
37h
37h
53h
30h
38h
32h
33h
45h
54h
33h
2Dh
43h
65~71 ...... Manufacturer JEDEC ID code
Samsung
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
Manufacturing location
Onyang Korea
Manufacturer part # (Memory module)
Manufacturer part # (DIMM configuration)
Manufacturer part # (Data bits)
M
3
Blank
...... Manufacturer part # (Data bits)
...... Manufacturer part # (Data bits)
Manufacturer part # (Mode & operating voltage)
Manufacturer part # (Module depth)
...... Manufacturer part # (Module depth)
Manufacturer part # (Refresh, # of banks in Comp. & inter-
Manufacturer part # (Composition component)
Manufacturer part # (Component revision)
Manufacturer part # (Package type)
Manufacturer part # (PCB revision & type)
Manufacturer part # (Hyphen)
7
7
S
0
8
2
3
E
T
3
" - "
C
Manufacturer part # (Power)
Manufacturer part # (Minimum cycle time)
Manufacturer part # (Minimum cycle time)
Manufacturer part # (TBD)
1
1
L
31h
48h
31h
4Ch
H
Blank
20h
Manufacturer revision code (For PCB)
...... Manufacturer revision code (For component)
Manufacturing date (Year)
3
33h
E ( 6th Gen.)
45h
-
-
3
3
4
5
Manufacturing date (Week)
-
-
95~98 Assembly serial #
-
-
-
99~125 Manufacturer specific data (may be used in future)
Undefined
100MHz
126
127
System frequency for 100MHz
Intel Specification details
Unused storage locations
64h
Detailed 100MHz Information
Undefined
8Fh
8Dh
128+
-
5
Note :
1. The bank select address is excluded in counting the total # of addresses.
2. This value is based on the component specification.
3. These bytes are programmed by code of Date Week & Date Year with BCD format.
4. These bytes are programmed by Samsung ¢s own Assembly Serial # system. All modules may have different unique serial #.
5. These bytes are Undefined and can be used for Samsung ¢s own purpose.
Rev.02 Sept. 2001
相关型号：
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