M378T2953BG0-LD5_技术文档

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

DDR2 Unbuffered SDRAM MODULE

240pin Unbuffered Module based on 512Mb B-die

64/72-bit Non-ECC/ECC

Revision 0.6

October 2003

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Revision History

Revision 0.3 (Sep. 2003)

- Initial Release

Revision 0.4 (Sep. 2003)

- Removed x16 base ECC UDIMM product

Revision 0.5 (Oct. 2003)

- Removed D4 speed bin(400 4-4-4)

Revision 0.6 (Oct. 2003)

- Added operation temperature condition

- Changed setup/hold time values(tlS/tDS, tIH/tDH)

- Added notes for setup/hold time(tIS/tDS, tIH/tDH)

- Added tREFI values by T_CASE(85°C/95°C)

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

DDR2 Unbuffered DIMM Ordering Information

Number of

Rank

Part Number

Density Organization

Component Composition

Height

x64 Non ECC

M378T3354BG0-CE6/D5/CC

M378T3354BG0-LE6/D5/CC

M378T6553BG0-CE6/D5/CC

M378T6553BG0-LE6/D5/CC

M378T2953BG0-CE6/D5/CC

M378T2953BG0-LE6/D5/CC

256MB

512MB

1GB

32Mx64

64Mx64

128Mx64

32Mx16(K4T51163QB)*4

64Mx8(K4T51083QB)*8

64Mx8(K4T51083QB)*16

1

2

30.00mm

1GB

x72 ECC

M391T6553BG0-CE6/D5/CC

M391T6553BG0-LE6/D5/CC

M391T2953BG0-CE6/D5/CC

M391T2953BG0-LE6/D5/CC

512MB

1GB

64Mx72

128Mx72

64Mx8(K4T51083QB)*9

64Mx8(K4T51083QB)*18

1

2

30.00mm

1GB

Note:

1. Speed bin is in order of CL-tRCD-tRP

Features

•

Performance range

E6(DDR2-667)

D5(DDR2-533)

CC(DDR2-400)

Unit

Speed@CL3

Speed@CL4

Speed@CL5

Speed@CL6

CL-tRCD-tRP

400

533

400

533

-

400

-

Mbps

CK

533

667

-

4-4-4

3-3-3

•

JEDEC standard 1.8V ± 0.1V Power Supply

VDDQ = 1.8V ± 0.1V

200 MHz f_CKfor 400Mb/sec/pin, 267MHz f_CKfor 533Mb/sec/pin, 333MHz f_CKfor 667Mb/sec/pin

•

4 Bank

Posted CAS

Programmable CAS Latency: 3, 4, 5

Programmable Additive Latency: 0, 1 , 2 , 3 and 4

Write Latency(WL) = Read Latency(RL) -1

Burst Length: 4 , 8(Interleave/nibble sequential)

Programmable Sequential / Interleave Burst Mode

Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

Off-Chip Driver(OCD) Impedance Adjustment

On Die Termination

Average Refesh Period 7.8us at lower then T_CASE85×C, 3.9us at 85×C < T_CASE< 95 ×C

•

Serial presence detect with EEPROM

DDR2 SDRAM Package: 60ball FBGA - 64Mx8, 84ball FBGA - 32Mx16

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Address Configuration

Organization

Row Address

Column Address

Bank Address

Auto Precharge

64Mx8(512Mb) based

Module

A0-A13

A0-A9

BA0-BA1

A10

32Mx16(512Mb)based

Module

A0-A12

A0-A9

BA0-BA1

A10

x64 DIMM Pin Configurations (Front side/Back side)

Front

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

Back

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

Front

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Back

Front

A4

Back

91

Front

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Back

DM5

NC

V

1

DQ19

61

181

182

183

184

REF

SS

DDQ

SS

V

2

DQ4

DQ5

DQ28

DQ29

62

A3

A1

92

DQS5

SS

DDQ

V

3

DQ0

DQ1

DQ24

DQ25

63

A2

93

SS

V

4

64

94

DQ46

DQ47

SS

DD

SS

V

5

DM0

NC

DM3

NC

KEY

95

DQ42

DQ43

SS

V

6

DQS0

DQS3

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

CK0

96

SS

V

7

97

DQ52

DQ53

SS

V

8

DQ6

DQ7

DQ30

DQ31

98

DQ48

DQ49

SS

DD

V

9

DQ2

DQ3

DQ26

DQ27

NC

A0

99

SS

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

CK2

SS

DD

SS

V

DQ12

DQ13

NC

A10/AP

BA0

BA1

SA2

SS

2

V

DQ8

DQ9

NC

NC, TEST

DDQ

SS

V

RAS

S0

DM6

NC

SS

DDQ

SS

V

DM1

NC

WE

DQS6

SS

V

DQS1

NC

CAS

DDQ

SS

V

ODT0

DQ54

DQ55

SS

DDQ

SS

1

V

CK1

NC

S1

DQ50

DQ51

A13

SS

V

NC

ODT1

DD

SS

V

DQ60

DQ61

SS

DDQ

SS

V

DQ14

DQ15

DQ36

DQ37

DQ56

DQ57

SS

DDQ

SS

V

DQ10

DQ11

CKE1

DQ32

DQ33

DDQ

SS

V

CKE0

DM7

NC

SS

DD

SS

V

DQ20

DQ21

DM4

NC

DQS7

SS

DD

NC

SS

V

DQ16

DQ17

NC

DQS4

SS

V

DQ62

DQ63

SS

DDQ

SS

V

DM2

NC

A12

A9

DQ38

DQ39

DQ58

DQ59

SS

DDQ

SS

V

DQS2

A11

A7

DQ34

DQ35

SS

V

VDDSPD

SA0

SS

DD

SS

V

DQ22

DQ23

A8

A6

DQ44

DQ45

SDA

SCL

SS

DD

SS

DQ18

A5

DQ40

DQ41

SA1

V

SS

NC = No Connect, RFU = Reserved for Future Use

1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.

2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

x72 DIMM Pin Configurations (Front side/Back side)

Front

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

Back

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

Front

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

Back

Front

181

182

183

184

Back

91

Front

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

Back

DM5

NC

V

1

DQ19

61

A4

REF

SS

DDQ

SS

V

2

DQ4

DQ5

DQ28

DQ29

62

A3

A1

92

DQS5

SS

DDQ

V

3

DQ0

DQ1

DQ24

DQ25

63

A2

93

SS

V

4

64

94

DQ46

DQ47

SS

DD

SS

V

5

DM0

NC

DM3

NC

KEY

95

DQ42

DQ43

SS

V

6

DQS0

DQS3

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

CK0

96

SS

V

7

97

DQ52

DQ53

SS

V

8

DQ6

DQ7

DQ30

DQ31

98

DQ48

DQ49

SS

DD

V

9

DQ2

DQ3

DQ26

DQ27

NC

A0

99

SS

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

CK2

SS

DD

SS

V

DQ12

DQ13

CB4

CB5

A10/AP

BA0

BA1

SA2

SS

2

V

DQ8

DQ9

CB0

CB1

DDQ

NC, TEST

SS

V

RAS

S0

DM6

NC

SS

DDQ

SS

V

DM1

NC

DM8

NC

WE

DQS6

SS

V

DQS1

DQS8

CAS

DDQ

SS

V

ODT0

A13

DQ54

DQ55

SS

DDQ

SS

V

CK1

CB6

CB7

S1

DQ50

DQ51

SS

V

NC

CB2

CB3

ODT1

DD

SS

V

DQ60

DQ61

SS

DDQ

SS

V

DQ14

DQ15

DQ36

DQ37

DQ56

DQ57

SS

DDQ

SS

V

DQ10

DQ11

CKE1

DQ32

DQ33

DDQ

SS

V

CKE0

DM7

NC

SS

DD

SS

V

DQ20

DQ21

NC

DM4

NC

DQS7

SS

DD

SS

V

DQ16

DQ17

NC

DQS4

SS

V

DQ62

DQ63

SS

DDQ

SS

V

DM2

NC

A12

A9

DQ38

DQ39

DQ58

DQ59

SS

DDQ

SS

V

DQS2

A11

A7

DQ34

DQ35

SS

V

VDDSPD

SA0

SS

DD

SS

V

DQ22

DQ23

A8

A6

DQ44

DQ45

SDA

SCL

SS

DD

SS

DQ18

A5

DQ40

DQ41

SA1

V

SS

NC = No Connect, RFU = Reserved for Future Use

1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.

2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Pin Description

Pin Name

Description

Pin Name

Description

A0-A13

BA0, BA1

RAS

DDR2 SDRAM address bus

CK0, CK1, CK2

SCL

DDR2 SDRAM clocks (positive line of differential pair)

DDR2 SDRAM clocks (negative line of differential pair)

DDR2 SDRAM bank select

2

DDR2 SDRAM row address strobe

DDR2 SDRAM column address strobe

DDR2 SDRAM wirte enable

DIMM Rank Select Lines

I C serial bus clock for EEPROM

2

CAS

WE

SDA

I C serial bus data line for EEPROM

2

SA0-SA2

I C serial address select for EEPROM

V

*

S0, S1

DDR2 SDRAM core power supply

DDR2 SDRAM I/O Driver power supply

DDR2 SDRAM I/O reference supply

Power supply return (ground)

DD

V

*

CKE0,CKE1

ODT0, ODT1

DQ0 - DQ63

DDR2 SDRAM clock enable lines

On-die termination control lines

DIMM memory data bus

DDQ

V

REF

V

SS

V

SPD

CB0 - CB7

DQS0 - DQS8

DM(0-8)

DIMM ECC check bits

Serial EEPROM positive power supply

Spare Pins(no connect)

DD

DDR2 SDRAM data strobes

DDR2 SDRAM data masks

NC

RESET

TEST

Not used on UDIMM

Used by memory bus analysis tools (unused on memory

DIMMs)

DQS0-DQS8

DDR2 SDRAM differential data strobes

*The VDD and VDDQ pins are tied to the single power-plane on PCB.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Input/Output Functional Description

Symbol

Type

Polarity

Function

CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the

crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to

the crossing of CK and CK (Both directions of crossing)

CK0-CK2

Differential

crossing

SSTL_1.8

Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By

deactivating the clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode

CKE0-CKE1

S0-S1

Active High

Enables the associated SDRAM command decoder when low and disables the command

decoder when high. When the command decoder is disbled, new command are ignored but

previous operations continue. This signal provides for external rank selection on systems

with multiple ranks

SSTL_1.8 Active Low

RAS, CAS, WE SSTL_1.8

-

TBD

-

RAS, CAS, and WE (ALONG WITH CS) define the command being entered.

When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the

function is enabled in the Extended Mode Register Set (EMRS).

ODT0-ODT1

SSTL_1.8

Supply

V

Reference voltage for SSTL 18 inputs.

REF

Power supply for the DDR II SDRAM output buffers to provide improved noise immunity.

For all current DDR2 unbuffered DIMM designs, VDDQ shares the same power plane as

VDD pins.

V

Supply

-

DDQ

BA0-BA1

A0-A13

SSTL_1.8

Selects which SDRAM BANK of four is activated.

During a Bank Activate command cycle, Address input defines the row address (RA0-

RA13)

During a Read or Write command cycle, Address input defines the colum address, In addi-

tion to the column address, AP is used to invoke autoprecharge operation at the end of the

burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the

bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge com-

mand cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge.

If AP is high, all banks will be precharged regardless of the state of BA0, BA1. If AP is low,

BA0, BA1are used to define which bank to precharge.

SSTL_1.8

-

DQ0-DQ63

CB0-CB7

SSTL_1.8

-

Data and Check Bit Input/Output pins.

DM is an input mask signal for write data. Input data is masked when DM is sampled High

coincident with that input data during a write access. DM is sampled on both edges of DQS.

Although DM pins are input only, the DM loading matches the DQ and DQS loading.

DM0-DM8

SSTL_1.8 Active High

Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins

V

,V

Supply

-

DD SS

are tied to V /V

planes on these modules.

DD DDQ

DQS0-DQS8

Differential Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7

SSTL_1.8

crossing

connect to the LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM

These signals and tied at the system planar to either V or V

SS

SPD EERPOM address range.

to configure the serial

DD

SA0-SA2

SDA

-

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to VDD to act as a pullup on the system board.

-

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-

nected from the SCL bus time to VDD to act as a pullup onthe system board.

SCL

-

Power supply for SPD EEPROM. This supply is separate from the V /V

EEPROM supply is operable from 1.7V to 3.6V.

power plane.

DD DDQ

V

SPD

Supply

DD

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Functional Block Diagram: 512MB, 64Mx64 Module(Populated as 1 rank of x8 DDR2 SDRAMs)

(M378T6553BG0)

S0

DQS0

DM0

DQS4

DM4

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

D0

D4

DQS1

DM1

DQS5

DM5

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D6

DQS3

DM3

DQS7

DM7

DM

NU/ CS DQS DQS

DM

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D7

V

Serial PD

DDSPD

Serial PD

SCL

* Clock Wiring

/V

D0 - D7

DD DDQ

SDA

WP

Clock

Input

DDR2 SDRAMs

VREF

A0

A1

A2

*CK0/CK0

*CK1/CK1

*CK2/CK2

2 DDR2 SDRAMs

3 DDR2 SDRAMs

V

SA0 SA1 SA2

SS

BA0 - BA1

A0 - A13

RAS

BA0-BA1 : DDR2 SDRAMs D0 - D7

A0-A13 : DDR2 SDRAMs D0 - D7

RAS : DDR2 SDRAMs D0 - D7

CAS : DDR2 SDRAMs D0 - D7

CKE : DDR2 SDRAMs D0 - D7

WE : DDR2 SDRAMs D0 - D7

ODT : DDR2 SDRAMs D0 - D7

*Wire per Clock Loading

Table/Wiring Diagrams

CAS

Notes :

CKE0

WE

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.

ODT0

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Functional Block Diagram: 512MB, 64Mx72 ECC Module(Populated as 1 rank of x8 DDR2 SDRAMs)

(M391T6553BG0)

S0

DQS0

DM0

DQS4

DM4

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

D0

D4

DQS1

DM1

DQS5

DM5

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D6

DQS3

DM3

DQS7

DM7

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D7

DQS8

DM8

Serial PD

SCL

WP

DM

CS DQS DQS

SDA

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A0

A1

A2

D8

SA0 SA1 SA2

* Clock Wiring

V

Serial PD

D0 - D8

DDSPD

Clock

Input

DDR2 SDRAMs

/V

DD DDQ

*CK0/CK0

*CK1/CK1

*CK2/CK2

3 DDR2 SDRAMs

VREF

BA0 - BA1

A0 - A13

RAS

BA0-BA1 : DDR2 SDRAMs D0 - D8

A0-A13 : DDR2 SDRAMs D0 - D8

RAS : DDR2 SDRAMs D0 - D8

CAS : DDR2 SDRAMs D0 - D8

CKE : DDR2 SDRAMs D0 - D8

WE : DDR2 SDRAMs D0 - D8

ODT : DDR2 SDRAMs D0 - D8

V

SS

*Wire per Clock Loading

Table/Wiring Diagrams

CAS

Notes :

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.

CKE0

WE

ODT0

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Functional Block Diagram: 1GB, 128Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs)

(M378T2953BG0)

S1

S0

DQS0

DM0

DQS4

DM4

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

D0

D8

D4

D12

DQS1

DM1

DQS5

DM5

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D9

D5

D13

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D10

D6

D14

DQS3

DM3

DQS7

DM7

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D11

D7

D15

V

Serial PD

DDSPD

Serial PD

/V

D0 - D15

DD DDQ

SCL

WP

SDA

VREF

A0

A1

A2

V

* Clock Wiring

SS

SA0 SA1 SA2

Clock

Input

DDR2 SDRAMs

BA0 - BA1

A0 - A13

CKE0

BA0-BA1 : DDR2 SDRAMs D0 - D15

A0-A13 : DDR2 SDRAMs D0 - D15

CKE : DDR2 SDRAMs D0 - D7

*CK0/CK0

*CK1/CK1

*CK2/CK2

4 DDR2 SDRAMs

6 DDR2 SDRAMs

CKE1

RAS

CAS

CKE : DDR2 SDRAMs D8 - D15

RAS : DDR2 SDRAMs D0 - D15

CAS : DDR2 SDRAMs D0 - D15

*Wire per Clock Loading

Table/Wiring Diagrams

Notes :

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.

WE

ODT0

ODT1

WE : DDR2 SDRAMs D0 - D15

ODT : DDR2 SDRAMs D0 - D7

ODT : DDR2 SDRAMs D8 - D15

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Functional Block Diagram: 1GB, 128Mx72 ECC Module(Populated as 2 ranks of x8 DDR2 SDRAMs)

(M391T2953BG0)

S1

S0

DQS0

DM0

DQS4

DM4

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

D0

D9

D4

D13

DQS1

DM1

DQS5

DM5

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D10

D5

D14

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D2

D11

D6

D15

DQS3

DM3

DQS7

DM7

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DM

CS DQS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D3

D12

D7

D16

DQS8

DM8

Serial PD

SCL

WP

DM

CS DQS DQS

DM

CS DQS DQS

SDA

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

A0

A1

A2

D8

D17

SA0 SA1 SA2

* Clock Wiring

Clock

Input

DDR2 SDRAMs

V

Serial PD

DDSPD

BA0 - BA1

A0 - A13

CKE0

BA0-BA1 : DDR2 SDRAMs D0 - D17

A0-A13 : DDR2 SDRAMs D0 - D17

CKE : DDR2 SDRAMs D0 - D8

*CK0/CK0

*CK1/CK1

*CK2/CK2

6 DDR2 SDRAMs

V

/V

D0 - D17

DD DDQ

VREF

CKE1

RAS

CAS

CKE : DDR2 SDRAMs D9 - D17

RAS : DDR2 SDRAMs D0 - D17

CAS : DDR2 SDRAMs D0 - D17

*Wire per Clock Loading

Table/Wiring Diagrams

V

SS

Notes :

WE

ODT0

ODT1

WE : DDR2 SDRAMs D0 - D17

ODT : DDR2 SDRAMs D0 - D8

ODT : DDR2 SDRAMs D9 - D17

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Functional Block Diagram: 256MB, 32Mx64 Module(Populated as 1 rank of x16 DDR2 SDRAMs)

(M378T3354BG0)

S0

CS

DQS1

DM1

DQS5

DM5

LDQS

LDOS

LDM

LDQS

LDOS

LDM

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D0

D2

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS0

DM0

DQS4

DM4

UDQS

UDOS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDOS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

CS

DQS3

DM3

DQS7

DM7

LDQS

LDOS

LDM

LDQS

LDOS

LDM

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

D1

D3

DQS2

DM2

DQS6

DM6

UDQS

UDOS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

UDQS

UDOS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

* Clock Wiring

V

Serial PD

DDSPD

Clock

Input

DDR2 SDRAMs

V

/V

D0 - D3

DD DDQ

Serial PD

*CK0/CK0

*CK1/CK1

*CK2/CK2

NC

SCL

WP

VREF

2 DDR2 SDRAMs

SDA

V

A0

A1

A2

SS

*Wire per Clock Loading

Table/Wiring Diagrams

SA0 SA1 SA2

BA0 - BA1

A0 - A12

CKE0

BA0-BA1 : DDR2 SDRAMs D0 - D3

A0-A12 : DDR2 SDRAMs D0 - D3

CKE : DDR2 SDRAMs D0 - D3

RAS : DDR2 SDRAMs D0 - D3

CAS : DDR2 SDRAMs D0 - D3

Notes :

RAS

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

4. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.

CAS

WE

WE : DDR2 SDRAMs D0 - D3

ODT : DDR2 SDRAMs D0 - D3

ODT0

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Absolute Maximum DC Ratings

Symbol

VDD

Parameter

Voltage on VDD pin relative to Vss

Voltage on VDDQ pin relative to Vss

Voltage on VDDL pin relative to Vss

Voltage on any pin relative to Vss

Storage Temperature

Rating

Units

Notes

1

- 1.0 V ~ 2.3 V

V

VDDQ

VDDL

- 0.5 V ~ 2.3 V

-55 to +100

1

V

V_INV_OUT

,

V

T_STG

°C

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.

AC & DC Operating Conditions

Recommended DC Operating Conditions (SSTL - 1.8)

Rating

Symbol

Parameter

Units

Notes

Min.

1.7

Typ.

1.8

Max.

1.9

VDD

VDDL

VDDQ

VREF

VTT

V

Supply Voltage

1.7

1.8

1.9

4

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.7

1.9

V

0.49*VDDQ

VREF-0.04

0.50*VDDQ

VREF

0.51*VDDQ

VREF+0.04

mV

V

1.2

3

There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must

be less than or equal to VDD.

1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is

expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.

2. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).

3. VTT of transmitting device must track VREF of receiving device.

4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Operating Temperature Condition

SYMBOL

TOPER

PARAMETER

RATING

0 to 95

UNITS

NOTES

1, 2

Operating Temperature

°C

Note :

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM.

2. The operation temperature range are the temperature where all DRAM specification will be supported.

Input DC Logic Level

Symbol

V_IH(dc)

Parameter

dc input logic high

dc input logic low

Min.

Max.

Units

V

Notes

VREF + 0.125

VDDQ + 0.3

V_IL(dc)

- 0.3

VREF - 0.125

V

Input AC Logic Level

Symbol

V_IH(ac)

Parameter

Min.

Max.

-

Units

V

Notes

VREF + 0.250

ac input logic high

ac input logic low

V_IL(ac)

-

VREF - 0.250

V

AC Input Test Conditions

Symbol

Condition

Input reference voltage

Value

Units

Notes

V

0.5 * V

1.0

V

1

REF

DDQ

Input signal maximum peak to peak swing

Input signal minimum slew rate

SWING(MAX)

SLEW

1.0

V/ns

2, 3

Note :

1. Setup (tIS & tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vih(dc)min and the first cross-

ing of Vih(ac)min. Setup (tIS & tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vil(dc)max

and the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘dc to ac region’,

use nominal slew rate for derating value (see Fig a.) If the actual signal is later than the nominal slew rate line anywhere between shaded

‘dc to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Fig b.)

2. Hold (tIH & tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vil(dc)max and the first crossing

of Vref. Hold (tIH & tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)min and the first

crossing of Vref. If the actual signal is always later than the nominal slew rate line between shaded ‘dc to Vref region’, use nominal slew rate

for derating value (see Fig a.) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to Vref region’, the

slew rate of a tangent line to the actual signal from the dc level to Vref level is used for derating value (see Fig b.)Input waveform timing is

referenced to the input signal crossing through the V

level applied to the device under test.

REF

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

DQS

CK

Hold

Time

Hold

Setup

Time Time

Setup

Time

Hold

Time

Hold

Time

Setup

Time

Setup

Time

V_DDQ

V

DDQ

V_IH(ac)min

V_IH(dc)min

V

min

IH(ac)

IH(dc)

dc to ac

region

dc to ac

region

min

V_REF

V

REF

V

max

V_IL(dc)max

IL(dc)

IL(ac)

dc to ac

region

dc to ac

region

V

_IL(ac)max

Setup

Delta TR

V

V_SS

SS

Hold

Delta TR

Hold

Delta TF

Hold

Delta TF

Setup

Delta TF

Hold

Delta TR

Setup

Delta TR

Setup

Delta TF

tangent line[Vih(ac)min - Vih(dc)min]

Setup Delta TR

Setup Slew Rate

Rising Signal

Vil(dc)max - Vil(ac)max

Setup Delta TF

Setup Slew Rate

Falling Signal

=

Setup Slew Rate

Rising Signal

Vih(ac)min - Vih(dc)min

Setup Delta TR

tangent line[Vil(dc)max - Vil(ac)max]

Setup Delta TF

Setup Slew Rate

Falling Signal

=

Vref - Vil(dc)max

Hold Delta TR

Hold Slew Rate

Rising Signal

tangent line [ Vref - Vil(dc)max ]

Hold Delta TR

Hold Slew Rate

Rising Signal

Vih(dc)min - Vref

Hold Delta TF

tangent line [ Vih(dc)min - Vref ]

Hold Delta TF

Hold Slew Rate

Falling Signal

Hold Slew Rate

Falling Signal

=

<Figure. a>

<Figure. b>

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Differential input AC logic Level

Symbol

V_ID(ac)

Parameter

Min.

0.5

Max.

Units

V

Notes

1

VDDQ + 0.6

ac differential input voltage

ac differential cross point voltage

V_IX(ac)

0.5 * VDDQ - 0.175 0.5 * VDDQ + 0.175

V

2

1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and UDQS.

2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS or

UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V IL(DC).

V

DDQ

V

TR

Crossing point

V

ID

V

IX or OX

V

CP

V

SSQ

< Differential signal levels >

Notes:

1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or

UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC) - V IL(AC).

2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ

. VIX(AC) indicates the voltage at which differential input signals must cross.

Differential AC output parameters

Symbol

V_OX(ac)

Parameter

Min.

Max.

Units

V

Notes

1

0.5 * VDDQ - 0.125 0.5 * VDDQ + 0.125

ac differential cross point voltage

Notes:

1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations in

VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Output Buffer Levels (@ Component)

Output AC Test Conditions

Symbol

V_OH

Parameter

Class II

V + 0.603

TT

Units

V

Notes

Minimum Required Output Pull-up under AC Test Load

Maximum Required Output Pull-down under AC Test Load

Output Timing Measurement Reference Level

V_OL

V

- 0.603

V

TT

V_OTR

0.5 * V

V

1

DDQ

1. The VDDQ of the device under test is referenced.

Output DC Current Drive

Symbol

I_OH(dc)

I_OL(dc)

Parameter

Output Minimum Source DC Current

Output Minimum Sink DC Current

Class II

- 13.4

13.4

Units

mA

Notes

1, 3, 4

2, 3, 4

mA

1.

2.

V

= 1.7 V; V

= 1420 mV. (V

- V

)/I must be less than 21 ohm for values of V

between V

and V

- 280

DDQ

OUT

DDQ OH

OUT

DDQ

mV.

V

= 1.7 V; V

= 280 mV. V

/I must be less than 21 ohm for values of V

between 0 V and 280 mV.

DDQ

OUT

OUT OL

OUT

3. The dc value of V

applied to the receiving device is set to V

TT

REF

4. The values of I

and I

are based on the conditions given in Notes 1 and 2. They are used to test device drive current

OH(dc)

OL(dc)

capability to ensure V min plus a noise margin and V max minus a noise margin are delivered to an SSTL_18 receiver. The

IH

IL

actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define

a convenient driver current for measurement.

OCD default characteristics

Description

Parameter

Min

12.6

Nom

18

Max

23.4

Unit

Notes

Output impedance

ohms 1,2

Output impedance step

size for OCD calibration

0

1.5

ohms

6

Pull-up and pull-down

mismatch

0

4

ohms 1,2,3

V/ns 1,4,5

Output slew rate

tbd

Note 1: Absolute Specifications (0°C ≤ T_CASE≤ +tbd°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)

Note 2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;

(VOUT-

Impedance mea-

must be less than 23.4 ohms

VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.

surement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol

for values of VOUT between 0V and 280mV.

Note 3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and

Note 4: Slew rate measured from vil(ac) to vih(ac).

Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew

measured from AC to AC. This is guaranteed by design and characterization.

voltage.

rate as

Note 6 : This represents the step size when the OCD is near 18 ohms at nominal conditions across all

process and represents only the DRAM uncertainty. A 0 ohm value (no calibration) can only be achieved if the OCD imped-

ance is 18 ohms +/- 0.75 ohms under nominal conditions.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Output slew rate load :

VTT

25 ohms

Output

(VOUT)

Reference

Point

Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25^oC, f=1MHz)

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Units

Non-ECC

M470T6554BG0

M470T6553BG0

M470T3354BG0

CCK0

CCK1

-

TBD

-

TBD

-

TBD

Input capacitance, CK and CK

Input capacitance, CKE and CS

CI

1

pF

Input capacitance, Addr, RAS, CAS, WE

CI

-

TBD

-

TBD

-

TBD

2

Input/output capacitance, DQ, DM, DQS, DQS

CIO

Non-ECC

TBD

CCK0

CCK1

CCK2

-

TBD

Input capacitance, CK and CK

pF

Input capacitance, CKE and CS

CI

1

2

Input capacitance, Addr, RAS, CAS, WE

Input/output capacitance, DQ, DM, DQS, DQS

-

TBD

CIO

-

Note: DM is internally loaded to match DQ and DQS identically.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

IDD Specification Parameters Definition

(IDD values are for full operating range of Voltage and Temperature)

Symbol

Proposed Conditions

Units

Notes

IDD0

Operating one bank active-precharge current;

t

mA

CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid com-

mands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD1

Operating one bank active-read-precharge current;

t

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD

mA

t

= RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address businputs are SWITCHING;

Data pattern is same as IDD4W

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

Precharge power-down current;

t

mA

t

All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus

inputs are FLOATING

Precharge quiet standby current;

t

All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputsare STA-

BLE; Data bus inputs are FLOATING

Precharge standby current;

t

All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

Active power-down current;

mA

Fast PDN Exit MRS(12) = 0mA

Slow PDN Exit MRS(12) = 1mA

t

All banks open; CK = CK(IDD); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING

Active standby current;

t

mA

All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH

between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

IDD4W

IDD4R

IDD5B

Operating burst write current;

t

All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-

t

max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are

SWITCHING; Data bus inputs are SWITCHING

Operating burst read current;

t

mA

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS

t

= RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus

inputs are SWITCHING; Data pattern is same as IDD4W

Burst auto refresh current;

t

CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid

commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

mA

IDD6

IDD7

Self refresh current;

CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs

are FLOATING; Data bus inputs are FLOATING

Normal

mA

Low Power

Operating bank interleave read current;

t

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK =

mA

t

CK(IDD), RC = RC(IDD), RRD = RRD(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between

valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R;

Refer to the following page for detailed timing conditions

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Operating Current Table(1-1) (TA=0^oC, VDD= 1.9V)

M378T6553BG0 : 512MB(64Mx8 *8) Module

E6

D5

CC

Symbol

Unit

Notes

(DDR2-667@CL=5) (DDR2-533@CL=4) (DDR2-400@CL=3)

IDD0

IDD1

TBD

mA

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

Normal

Low power

IDD7

IDD6

Optional

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M378T2953BG0 : 1GB(64Mx8 *16) Module

E6

D5

CC

Symbol

Unit

Notes

(DDR2-667@CL=5) (DDR2-533@CL=4) (DDR2-400@CL=3)

IDD0

IDD1

TBD

mA

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

Normal

Low power

IDD7

IDD6

Optional

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Operating Current Table(1-2) (TA=0^oC, VDD= 1.9V)

M378T3354BG0 : 256MB(32Mx16 *4) Module

E6

D5

CC

Symbol

Unit

Notes

(DDR2-667@CL=5) (DDR2-533@CL=4) (DDR2-400@CL=3)

IDD0

IDD1

TBD

mA

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

Normal

Low power

IDD7

IDD6

Optional

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M391T6553BG0 : 512MB(64Mx8 *9) ECC Module

E6

D5

CC

Symbol

Unit

Notes

(DDR2-667@CL=5) (DDR2-533@CL=4) (DDR2-400@CL=3)

IDD0

IDD1

TBD

mA

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

Normal

Low power

IDD7

IDD6

Optional

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Operating Current Table(1-3) (TA=0^oC, VDD= 1.9V)

M391T2953BG0 : 1GB(64Mx8 *18) ECC Module

E6

D5

CC

Symbol

Unit

Notes

(DDR2-667@CL=5) (DDR2-533@CL=4) (DDR2-400@CL=3)

IDD0

IDD1

TBD

mA

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

Normal

Low power

IDD7

IDD6

Optional

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Electrical Characteristics & AC Timing for DDR2-667/533/400

(0 °C < T_CASE< 95 °C; V_DDQ= 1.8V + 0.1V; V_DD= 1.8V + 0.1V)

Refresh Parameters by Device Density

Parameter

Symbol

256Mb

512Mb

1Gb

2Gb

4Gb

Units

Refresh to active/Refresh command time

tRFC

tREFI

75

105

127.5

195

tbd

ns

0 °C ≤ T

≤ 85°C

≤ 95°C

7.8

3.9

7.8

3.9

7.8

3.9

7.8

3.9

7.8

3.9

µs

CASE

Average periodic refresh interval

85 °C < T

CASE

Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Speed

Bin (CL - tRCD - tRP)

Parameter

tCK, CL=3

tCK, CL=4

tCK, CL=5

tRCD

DDR2-667(E6)

DDR2-533(D5)

DDR2-400(CC)

Units

5 - 5- 5

4 - 4 - 4

3 - 3 - 3

min

5

max

8

min

5

max

min

5

max

8

-

8

-

ns

3.75

3

8

3.75

-

5

8

-

15

55

40

15

55

40

15

55

40

tRP

tRC

70000

tRAS

Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the bottom)

Symbol

Units

Notes

Parameter

DDR2-667

DDR2-533

min max

DDR2-400

min

max

min

max

DQ output access time from

CK/CK

tAC

-450

+450

-500

+500

-600

+600

ps

DQS output access time from

CK/CK

tDQSCK

-400

+400

-450

+450

-500

+500

CK high-level width

CK low-level width

CK half period

tCH

tCL

tHP

0.45

0.55

x

0.45

0.55

x

0.45

0.55

x

tCK

ps

min(tCL,

tCH)

min(tCL,

tCH)

min(tCL,

tCH)

19,20

23

Clock cycle time, CL=x

tCK

tDH

3000

tbd

8000

x

3750

225

8000

x

5000

275

8000

x

ps

DQ and DM input hold time

14,15,

16

DQ and DM input setup time

tDS

tbd

0.6

x

100

0.6

x

150

0.6

x

ps

14,15,

16

Control & Address input

pulse width for each input

tIPW

tCK

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

DQ and DM input pulse width

for each input

tDIPW

0.35

x

0.35

x

0.35

x

tCK

Data-out high-impedance

time from CK/CK

tHZ

x

tAC max

tbd

x

tAC max

300

x

tAC max

350

ps

Data-out low-impedance time

from CK/CK

tLZ

tAC min

x

tAC min

ps

DQS-DQ skew for DQS and

associated DQ signals

tDQSQ

x

ps

21

20

DQ hold skew factor

tQHS

tQH

tbd

x

400

x

450

x

ps

DQ/DQS output hold time

from DQS

tHP -

tQHS

tHP - tQHS

tHP -

tQHS

Write command to first DQS

latching transition

tDQSS

WL - 0.25

WL +

0.25

WL - 0.25

WL +

0.25

WL - 0.25

WL +

0.25

tCK

DQS input high pulse width

DQS input low pulse width

tDQSH

tDQSL

tDSS

0.35

0.2

x

0.35

0.2

x

0.35

0.2

x

tCK

DQS falling edge to CK setup

time

DQS falling edge hold time from

CK

tDSH

tMRD

0.2

2

x

0.2

2

x

0.2

2

x

tCK

Mode register set command

cycle time

Write preamble setup time

Write postamble

tWPRES

tWPST

tWPRE

tIH

0

x

0.6

x

0

x

0.6

x

0

x

0.6

x

ps

tCK

ps

0.4

tbd

0.4

375

0.4

475

18

Write preamble

Address and control input

hold time

x

13,15,

17

Address and control input

setup time

tIS

tbd

x

250

x

350

x

ps

13,15,

17

Read preamble

Read postamble

tRPRE

tRPST

tRRD

0.9

0.4

7.5

1.1

0.6

x

0.9

0.4

7.5

1.1

0.6

x

0.9

0.4

7.5

1.1

0.6

x

tCK

ns

Active to active command

period for 1KB page size

products

12

Active to active command

period for 2KB page size

products

tRRD

10

x

10

x

10

x

ns

CAS to CAS command delay

Write recovery time

tCCD

tWR

2

15

2

15

2

tCK

ns

x

15

x

Auto precharge write

recovery + precharge time

tDAL

tWR+tRP*

tWR+tRP

*

tCK

22

11

Internal write to read

command delay

tWTR

tRTP

7.5

x

7.5

x

10

x

ns

Internal read to precharge

command delay

7.5

Exit self refresh to a non-

read command

tXSNR

tRFC + 10

tRFC +

10

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Exit self refresh to a read

command

tXSRD

200

2

tCK

Exit precharge power down

to any non-read command

tXP

2

x

2

x

tCK

Exit active power down to

read command

tXARD

tXARDS

2

x

2

tCK

9

Exit active power down to read

command

6 - AL

9, 10

(Slow exit, Lower power)

^tCKE

CKE minimum pulse width

(high and low pulse width)

3

tCK

3

^tAOND

^tAON

ODT turn-on delay

ODT turn-on

2

tCK

ns

tAC(min)

tAC(max)

+0.7

tAC(min)

tAC(max)

+1

tAC(min)

tAC(max)

+1

13, 24

^tAONPD

ODT turn-on(Power-Down

mode)

tAC(min)+

2

2tCK+tAC

(max)+1

tAC(min)+

2

2tCK+tAC

(max)+1

tAC(min)

+2

2tCK+tA

C(max)+1

ns

^tAOFD

^tAOF

ODT turn-off delay

ODT turn-off

2.5

tCK

ns

tAC(min)

tAC(max)+

0.6

tAC(max)+

0.6

tAC(min)

tAC(max)

+ 0.6

tAC(min)

25

^tAOFPD

ODT turn-off (Power-Down

mode)

tAC(min)+

2

2.5tCK+tA

C(max)+1

tAC(min)+

2

2.5tCK+

tAC(max)

+1

tAC(min)

+2

2.5tCK+

tAC(max)

+1

ns

ODT to power down entry latency

ODT power down exit latency

tANPD

tAXPD

tOIT

3

8

0

3

8

0

3

8

0

tCK

ns

OCD drive mode output

delay

12

Minimum time clocks

remains ON after CKE

asynchronously drops LOW

tDelay

tIS+tCK+tI

H

tIS+tCK+tI

H

tIS+tCK+t

IH

ns

23

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Physical Dimensions: 64Mbx8 based 64Mx64/x72 Module(1 Rank)

(M378/91T6553BG0)

Units : Millimeters

133.35

131.35

128.95

N/A

(for x64)

SPD

ECC

(for x72)

30.00

(2)

2.50

B

A

2.7

63.00

55.00

1.270 ± 0.10

3.00

5.00

4.00

0.80±0.05

0.20

4.00

3.80

4.00

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 64M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QB-GC/L##.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Physical Dimensions: 64Mbx8 based 128Mx64/x72 Module(2 Ranks)

(M378/91T2953BG0)

Units : Millimeters

133.35

131.35

128.95

N/A

(for x64)

SPD

ECC

30.00

(for x72)

(2)

2.50

B

A

4.00

63.00

55.00

N/A

(for x64)

ECC

(for x72)

1.270 ± 0.10

3.00

5.00

4.00

0.80±0.05

0.20

4.00

3.80

4.00

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 64M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51083QB-GC/L##.

Rev. 0.6 Oct. 2003

Preliminary

DDR2 SDRAM

256MB,512MB,1GB Unbuffered DIMMs

Physical Dimensions: 32Mbx16 based 32Mx64/x72 Module(1 Rank)

(M378T3354BG0)

Units : Millimeters

133.35

131.35

128.95

SPD

30.00

(2)

2.50

B

A

2.7

63.00

55.00

1.270 ± 0.10

3.00

5.00

4.00

0.80±0.05

0.20

4.00

3.80

4.00

2.50

1.00

1.50±0.10

Detail A

Detail B

The used device is 32M x16 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T51163QB-GC/L##.

Rev. 0.6 Oct. 2003


型号：	M378T2953BG0-LD5
厂家：	SAMSUNG
描述：	DDR DRAM Module, 128MX64, 0.5ns, CMOS, DIMM-240 动态存储器双倍数据速率内存集成电路
文件：	总27页 (文件大小：420K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M378T2953BG0-LD5 [SAMSUNG]

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