M378T3253FZ0-CE6 [SAMSUNG]
DDR2 Unbuffered SDRAM MODULE; 无缓冲DDR2 SDRAM模块
| 型号： | M378T3253FZ0-CE6 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR2 Unbuffered SDRAM MODULE |
| 文件： | 总20页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
DDR2 Unbuffered SDRAM MODULE
240pin Unbuffered Module based on 256Mb F-die
64/72-bit Non-ECC/ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
DDR2 Unbuffered DIMM Ordering Information
Part Number
Density
Organization
Component Composition
Number of Rank
Height
x64 Non ECC
M378T3253FG(Z)3-CE6/D5/CC
M378T3253FG(Z)0-CE6/D5/CC
M378T6453FG(Z)3-CE6/D5/CC
M378T6453FG(Z)0-CE6/D5/CC
256MB
256MB
512MB
512MB
32Mx64
32Mx64
64Mx64
64Mx64
32Mx8(K4T56083QF)*8
32Mx8(K4T56083QF)*8
32Mx8(K4T56083QF)*16
32Mx8(K4T56083QF)*16
1
1
2
2
30mm
30mm
30mm
30mm
x72 ECC
M391T3253FG(Z)3-CE6/D5/CC
M391T3253FG(Z)0-CE6/D5/CC
M391T6453FG(Z)3-CE6/D5/CC
M391T6453FG(Z)0-CE6/D5/CC
256MB
256MB
512MB
512MB
32Mx72
32Mx72
64Mx72
64Mx72
32Mx8(K4T56083QF)*9
32Mx8(K4T56083QF)*9
32Mx8(K4T56083QF)*18
32Mx8(K4T56083QF)*18
1
1
2
2
30mm
30mm
30mm
30mm
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Features
•
Performance range
E6(DDR2-667)
D5(DDR2-533)
CC(DDR2-400)
Unit
Mbps
Mbps
Mbps
CK
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
400
533
-
400
400
-
667
5-5-5
4-4-4
3-3-3
•
•
JEDEC standard 1.8V ± 0.1V Power Supply
= 1.8V ± 0.1V
V
DDQ
•
200 MHz f for 400Mb/sec/pin, 267MHz f for 533Mb/sec/pin, 333MHz f for 667Mb/sec/pin
CK CK CK
•
•
•
•
•
•
•
•
•
•
•
4 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5
Programmable Additive Latency: 0, 1 , 2 , 3 and 4
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination
Average Refresh Period 7.8us at lower than a T
85°C, 3.9us at 85°C < T
< 95 °C
CASE
CASE
- support High Temperature Self-Refresh rate enable feature
•
•
Package: 60ball FBGA - 32Mx8
All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Address Configuration
Organization
Row Address
Column Address
Bank Address
Auto Precharge
32Mx8(256Mb) based Module
A0-A12
A0-A9
BA0-BA1
A10
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
x64 DIMM Pin Configurations (Front side/Back side)
Pin
1
Front
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
Pin
61
Front
Pin
181
182
183
184
Back
Pin
91
92
93
94
95
96
97
98
Front
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5
NC
V
V
V
V
V
V
DQ19
A4
REF
SS
SS
DDQ
SS
V
V
2
3
4
5
6
7
8
9
DQ4
DQ5
V
DQ28
DQ29
V
62
63
64
A3
A1
DQS5
DQS5
SS
SS
DDQ
V
DQ0
DQ1
V
DQ24
DQ25
A2
SS
V
V
V
DQ46
DQ47
SS
SS
DD
DD
SS
V
DM0
NC
V
DM3
NC
V
KEY
DQ42
DQ43
SS
SS
V
V
DQS0
DQS0
V
DQS3
DQS3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
CK0
CK0
SS
SS
V
V
DQ52
DQ53
SS
SS
SS
SS
V
V
V
DQ6
DQ7
V
DQ30
DQ31
V
DQ48
DQ49
SS
SS
DD
DD
V
DQ2
DQ3
V
DQ26
DQ27
NC
A0
99
SS
V
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
CK2
SS
SS
DD
DD
SS
V
DQ12
DQ13
V
NC
NC
V
A10/AP
BA0
BA1
SA2
SS
SS
2
V
V
DQ8
DQ9
V
NC
NC
NC, TEST
DDQ
SS
V
V
RAS
S0
DM6
NC
SS
SS
DDQ
SS
V
DM1
NC
V
NC
NC
V
WE
CAS
DQS6
DQS6
SS
SS
V
V
DQS1
DQS1
V
NC
NC
DDQ
SS
V
V
ODT0
DQ54
DQ55
SS
SS
DDQ
SS
V
CK1
CK1
V
NC
NC
V
S1
ODT1
DQ50
DQ51
SS
SS
NC
V
V
NC
NC
V
NC
NC
DD
SS
V
V
V
DQ60
DQ61
SS
SS
DDQ
SS
SS
V
V
V
DQ14
DQ15
V
DQ36
DQ37
DQ56
DQ57
SS
SS
DDQ
SS
V
V
DQ10
DQ11
V
CKE1
DQ32
DQ33
DDQ
SS
V
V
V
CKE0
DM7
NC
SS
DD
SS
SS
V
V
DQ20
DQ21
V
DM4
NC
DQS7
DQS7
SS
DD
NC
NC
SS
V
DQ16
DQ17
V
NC
NC
DQS4
DQS4
SS
V
V
V
DQ62
DQ63
SS
DDQ
SS
SS
V
V
DM2
NC
V
A12
A9
DQ38
DQ39
DQ58
DQ59
SS
DDQ
SS
V
DQS2
DQS2
V
A11
A7
DQ34
DQ35
SS
V
V
V
VDDSPD
SA0
SA1
SS
DD
SS
SS
V
V
DQ22
DQ23
A8
A6
DQ44
DQ45
SDA
SCL
SS
DD
SS
DQ18
A5
DQ40
DQ41
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. Pin173 Pin174 are reserved for 2Gb/4Gb comp. base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
x72 DIMM Pin Configurations (Front side/Back side)
Pin
1
Front
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Front
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Back
Pin
61
Front
Pin
181
182
183
184
Back
DDQ
Pin
91
92
93
94
95
96
97
98
Front
SS
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Back
DM5
NC
V
V
V
V
V
V
DQ19
A4
REF
SS
SS
V
V
2
3
4
5
6
7
8
9
DQ4
DQ5
V
DQ28
DQ29
62
63
64
A3
A1
DQS5
DQS5
SS
SS
DDQ
V
DQ0
DQ1
V
DQ24
DQ25
A2
SS
V
V
V
V
DQ46
DQ47
SS
SS
DD
DD
SS
V
DM0
NC
V
DM3
NC
KEY
DQ42
DQ43
SS
SS
V
V
DQS0
DQS0
V
DQS3
DQS3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
CK0
CK0
SS
SS
V
V
V
DQ52
DQ53
SS
SS
SS
SS
V
V
V
DQ6
DQ7
V
DQ30
DQ31
DQ48
DQ49
SS
SS
DD
DD
V
DQ2
DQ3
V
DQ26
DQ27
NC
A0
99
SS
V
V
V
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
CK2
CK2
SS
SS
DD
DD
SS
V
DQ12
DQ13
V
CB4
CB5
A10/AP
BA0
BA1
SA2
SS
SS
2
V
V
DQ8
DQ9
V
CB0
CB1
NC, TEST
DDQ
SS
V
V
V
RAS
S0
DM6
NC
SS
SS
DDQ
SS
V
DM1
NC
V
DM8
NC
WE
CAS
DQS6
DQS6
SS
SS
V
V
DQS1
DQS1
V
DQS8
DQS8
DDQ
SS
V
V
V
ODT0
NC
DQ54
DQ55
SS
SS
DDQ
SS
V
CK1
CK1
V
CB6
CB7
S1
ODT1
DQ50
DQ51
SS
SS
V
V
NC
NC
V
CB2
CB3
DD
SS
V
V
V
V
DQ60
DQ61
SS
SS
DDQ
SS
SS
V
V
V
DQ14
DQ15
V
DQ36
DQ37
DQ56
DQ57
SS
SS
DDQ
SS
V
V
DQ10
DQ11
V
CKE1
DQ32
DQ33
DDQ
SS
V
V
V
CKE0
DM7
NC
SS
DD
SS
SS
V
V
DQ20
DQ21
V
NC
NC
DM4
NC
DQS7
DQS7
SS
DD
SS
V
DQ16
DQ17
V
NC
NC
DQS4
DQS4
SS
V
V
V
DQ62
DQ63
SS
DDQ
SS
SS
V
V
DM2
NC
V
A12
A9
DQ38
DQ39
DQ58
DQ59
SS
DDQ
SS
V
DQS2
DQS2
V
A11
A7
DQ34
DQ35
SS
V
V
V
VDDSPD
SA0
SA1
SS
DD
SS
SS
V
V
DQ22
DQ23
A8
A6
DQ44
DQ45
SDA
SCL
SS
DD
SS
DQ18
A5
DQ40
DQ41
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. Pin173 Pin174 are reserved for 2Gb/4Gb comp. base Unbuffered DIMM.
2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)
Pin Description
Pin Name
Description
Pin Name
Description
A0-A12
DDR2 SDRAM address bus
CK0, CK1, CK2 DDR2 SDRAM clocks (positive line of differential pair)
BA0, BA1
RAS
DDR2 SDRAM bank select
DDR2 SDRAM row address strobe
DDR2 SDRAM column address strobe
DDR2 SDRAM wirte enable
DIMM Rank Select Lines
CK0, CK1, CK2 DDR2 SDRAM clocks (negative line of differential pair)
2
SCL
SDA
I C serial bus clock for EEPROM
2
CAS
I C serial bus data line for EEPROM
2
WE
SA0-SA2
I C serial address select for EEPROM
S0, S1
V
*
DDR2 SDRAM core power supply
DDR2 SDRAM I/O Driver power supply
DDR2 SDRAM I/O reference supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare Pins(no connect)
DD
CKE0,CKE1
ODT0, ODT1
DQ0 - DQ63
CB0 - CB7
DQS0 - DQS8
DM(0-8)
DDR2 SDRAM clock enable lines
On-die termination control lines
DIMM memory data bus
V
*
DDQ
V
REF
V
SS
DIMM ECC check bits
V
SPD
DD
DDR2 SDRAM data strobes
DDR2 SDRAM data masks
NC
RESET
Not used on UDIMM
Used by memory bus analysis tools (unused on memory
DIMMs)
DQS0-DQS8
DDR2 SDRAM differential data strobes
TEST
* The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Input/Output Functional Description
Symbol
Type
Function
CK0-CK2
CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge of
Input
CK0-CK2
CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing)
Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE
low initiates the Powe Down mode, or the Self-Refresh mode
CKE0-CKE1
S0-S1
Input
Input
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
command decoder is disbled, new command are ignored but previous operations continue. This signal provides for exter-
nal rank selection on systems with multiple ranks
RAS, CAS, WE
ODT0-ODT1
Input
Input
RAS, CAS, and WE (ALONG WITH CS) define the command being entered.
When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the
Extended Mode Register Set (EMRS).
V
Supply Reference voltage for SSTL 18 inputs.
REF
Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current DDR2 unbuffered
V
Supply
DDQ
DIMM designs, VDDQ shares the same power plane as VDD pins.
BA0-BA1
A0-A13
Input
Selects which SDRAM BANK of four is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP
is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge
command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0, BA1. If AP is low, BA0, BA1are used to define which bank to pre-
charge.
Input
DQ0-DQ63
CB0-CB7
In/Out
Input
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading.
DM0-DM8
Power and ground for DDR2 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to V /V
planes on
DD DDQ
V
,V
Supply
DD SS
these modules.
DQS0-DQS8
DQS0-DQS8
Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the LDQS pin of the
DRAMs and DQ8-17 connect to the UDQS pin of the DRAM
In/Out
Input
SA0-SA2
These signals and tied at the system planar to either V or V to configure the serial SPD EERPOM address range.
SS DD
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the
SDA bus line to VDD to act as a pullup on the system board.
SDA
In/Out
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to VDD to act as a pullup onthe system board.
SCL
Input
Power supply for SPD EEPROM. This supply is separate from the V /V
power plane. EEPROM supply is operable
DD DDQ
V
SPD
Supply
DD
from 1.7V to 3.6V.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 256MB, 32Mx64 Module(Populated as 1 rank of x8 DDR2 SDRAMs)
M378T3253FG(Z)3 / M378T3253FG(Z)0
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
I/O 0
CS DQS DQS
DM
I/O 0
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
NU/ CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
V
V
Serial PD
DDSPD
Serial PD
SCL
WP
* Clock Wiring
/V
D0 - D7
D0 - D7
D0 - D7
DD DDQ
SDA
Clock Input
DDR2 SDRAMs
VREF
A0
A1
A2
*CK0/CK0
*CK1/CK1
*CK2/CK2
2 DDR2 SDRAMs
3 DDR2 SDRAMs
3 DDR2 SDRAMs
V
SA0 SA1 SA2
SS
BA0 - BA1
A0 - A12
RAS
BA0-BA1 : DDR2 SDRAMs D0 - D7
A0-A12 : DDR2 SDRAMs D0 - D7
RAS : DDR2 SDRAMs D0 - D7
CAS : DDR2 SDRAMs D0 - D7
CKE : DDR2 SDRAMs D0 - D7
WE : DDR2 SDRAMs D0 - D7
ODT : DDR2 SDRAMs D0 - D7
*Wire per Clock Loading
Table/Wiring Diagrams
CAS
Notes :
CKE0
WE
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.
ODT0
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 256MB, 32Mx72 ECC Module(Populated as 1 rank of x8 DDR2 SDRAMs)
M391T3253FG(Z)3 / M391T3253FG(Z)0
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
I/O 0
CS DQS DQS
DM
I/O 0
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
DQS8
DQS8
DM8
Serial PD
SCL
WP
DM
CS DQS DQS
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0
A1
A2
D8
SA0 SA1
SA2
* Clock Wiring
V
V
Serial PD
D0 - D8
D0 - D8
D0 - D8
DDSPD
Clock Input
DDR2 SDRAMs
/V
DD DDQ
*CK0/CK0
*CK1/CK1
*CK2/CK2
3 DDR2 SDRAMs
3 DDR2 SDRAMs
3 DDR2 SDRAMs
VREF
BA0 - BA1
A0 - A12
RAS
BA0-BA1 : DDR2 SDRAMs D0 - D8
A0-A12 : DDR2 SDRAMs D0 - D8
RAS : DDR2 SDRAMs D0 - D8
CAS : DDR2 SDRAMs D0 - D8
CKE : DDR2 SDRAMs D0 - D8
WE : DDR2 SDRAMs D0 - D8
ODT : DDR2 SDRAMs D0 - D8
V
SS
*Wire per Clock Loading
Table/Wiring Diagrams
CAS
Notes :
CKE0
WE
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 5.1 Ohms ± 5%.
ODT0
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 512B, 64Mx64 Module(Populated as 2 ranks of x8 DDR2 SDRAMs)
M378T6453FG(Z)3 / M378T6453FG(Z)0
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
I/O 0
CS DQS DQS
DM
I/O 0
CS DQS DQS
DM
I/O 0
CS DQS DQS
DM
I/O 0
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D8
D4
D12
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D9
D5
D13
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D10
D6
D14
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D11
D7
D15
V
V
Serial PD
DDSPD
Serial PD
/V
D0 - D15
D0 - D15
D0 - D15
DD DDQ
SCL
WP
SDA
VREF
A0
A1
A2
SA2
* Clock Wiring
V
SS
SA0 SA1
Clock Input
DDR2 SDRAMs
BA0 - BA1
A0 - A12
CKE0
BA0-BA1 : DDR2 SDRAMs D0 - D15
A0-A12 : DDR2 SDRAMs D0 - D15
CKE : DDR2 SDRAMs D0 - D7
CKE : DDR2 SDRAMs D8 - D15
RAS : DDR2 SDRAMs D0 - D15
CAS : DDR2 SDRAMs D0 - D15
*CK0/CK0
*CK1/CK1
*CK2/CK2
4 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
CKE1
RAS
CAS
*Wire per Clock Loading
Table/Wiring Diagrams
Notes :
WE
ODT0
ODT1
WE : DDR2 SDRAMs D0 - D15
ODT : DDR2 SDRAMs D0 - D7
ODT : DDR2 SDRAMs D8 - D15
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Functional Block Diagram: 512MB, 64Mx72 ECC Module(Populated as 2 ranks of x8 DDR2 SDRAMs)
M391T6453FG(Z)3 / M391T6453FG(Z)0
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
I/O 0
CS DQS DQS
DM
I/O 0
CS DQS DQS
DM
I/O 0
CS DQS DQS
DM
I/O 0
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D9
D4
D13
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D11
D6
D15
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D12
D7
D16
DQS8
DQS8
DM8
Serial PD
SCL
WP
DM
CS DQS DQS
DM
CS DQS DQS
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
A0
A1
A2
D8
D17
SA0 SA1 SA2
* Clock Wiring
Clock Input
DDR2 SDRAMs
V
Serial PD
DDSPD
BA0 - BA1
A0 - A12
CKE0
BA0-BA1 : DDR2 SDRAMs D0 - D17
A0-A12 : DDR2 SDRAMs D0 - D17
CKE : DDR2 SDRAMs D0 - D8
CKE : DDR2 SDRAMs D9 - D17
RAS : DDR2 SDRAMs D0 - D17
CAS : DDR2 SDRAMs D0 - D17
*CK0/CK0
*CK1/CK1
*CK2/CK2
6 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
V
/V
D0 - D17
D0 - D17
D0 - D17
DD DDQ
VREF
CKE1
RAS
CAS
*Wire per Clock Loading
Table/Wiring Diagrams
V
SS
Notes :
WE
ODT0
ODT1
WE : DDR2 SDRAMs D0 - D17
ODT : DDR2 SDRAMs D0 - D8
ODT : DDR2 SDRAMs D9 - D17
1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.
2. BAx, Ax, RAS, CAS, WE resistors : 3 Ohms ± 5%.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
V
Notes
Voltage on V pin relative to V
V
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
DD
SS
DD
Voltage on V
Voltage on V
pin relative to V
V
V
DDQ
DDL
SS
SS
DDQ
pin relative to V
V
V
1
DDL
Voltage on any pin relative to V
Storage Temperature
V
V
V
1
SS
IN, OUT
T
°C
1, 2
STG
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
V
Supply Voltage
V
V
DD
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
DDL
V
1.7
1.8
1.9
V
DDQ
V
0.49*V
0.50*V
0.51*V
DDQ
mV
V
1,2
3
REF
DDQ
DDQ
V
V
-0.04
V
V
+0.04
REF
TT
REF
REF
Note : There is no specific device V supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
must be less than or equal
DDQ
DD
to V
.
DD
1. The value of V
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
is expected to be about 0.5
REF
REF
x V
of the transmitting device and V
is expected to track variations in V
.
DDQ
DDQ
REF
2. Peak to peak AC noise on V
may not exceed +/-2% V
(DC).
REF
REF
3. V of transmitting device must track V
of receiving device.
REF
TT
4. AC parameters are measured with V , V
and V
tied together.
DDL
DD
DDQ
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 0 - 85 °C, operation temperature range are the temperature which all DRAM specification will be supported.
3. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol
(DC)
Parameter
Min.
+ 0.125
Max.
V + 0.3
DDQ
Units
Notes
V
DC input logic high
DC input logic low
V
V
V
IH
REF
V (DC)
V
- 0.3
V
- 0.125
REF
IL
DDQ
Input AC Logic Level
DDR2-400, DDR2-533
DDR2-667
Min.
VREF + 0.200
Symbol
Parameter
Units
Notes
Min.
Max.
Max.
V
(AC)
(AC)
AC input logic high
AC input logic low
VREF + 0.250
-
-
V
V
IH
V
VREF - 0.250
VREF - 0.200
IL
AC Input Test Conditions
Symbol
Condition
Value
0.5 * V
Units
V
Notes
V
Input reference voltage
1
1
REF
DDQ
V
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
SWING(MAX)
SLEW
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
2. The input signal minimum slew rate is to be maintained over the range from V
max for falling edges as shown in the below figure.
(AC) level applied to the device under test.
IH/IL
REF
to V (AC) min for rising edges and the range from V
to V (AC)
IL
IH
REF
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the negative
transitions.
IL
IH
IH
IL
V
V
V
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
(DC) max
IL
IL
(AC) max
SS
delta TF
V
delta TR
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
Rising Slew =
delta TF
< AC Input Test Signal Waveform >
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol
IDD0
Proposed Conditions
Operating one bank active-precharge current;
Units
Notes
t
t
t
t
t
t
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Ad-
mA
dress bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
IDD1
mA
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as IDD4W
Precharge power-down current;
t
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0mA
mA
mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING
Slow PDN Exit MRS(12) = 1mA
Active standby current;
t
t
t
t
t
t
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
mA
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP
IDD4W
IDD4R
t
= RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus in-
puts are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
mA
mA
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as IDD4W
Burst auto refresh current;
t
t t
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;
IDD5B
IDD6
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal
mA
mA
Low Power
Operating bank interleave read current;
t
t
t
t
t
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC =
t
t
t
t
t
t
t
IDD7
RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid com-
mA
mands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following
page for detailed timing conditions
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Operating Current Table(1-1) (TA=0oC, VDD= 1.9V)
M378T3253FG(Z)3 / M378T3253FG(Z)0 : 256MB(32Mx8 *8) Module
E6
D5
CC
Symbol
Unit
Notes
(DDR2-667@CL=5)
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
840
920
64
240
280
280
120
600
1,680
1,480
1,360
40
800
880
64
200
240
240
120
560
1,400
1,280
1,320
40
760
800
64
200
240
240
120
520
1,080
1,040
1,280
40
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
Normal
IDD7
2,120
2,040
2,040
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M378T6453FG(Z)3 / M378T6453FG(Z)0 : 512MB(32Mx8 *16) Module
E6
D5
CC
Symbol
Unit
Notes
(DDR2-667@CL=5)
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
1,440
1,520
128
480
560
1,360
1,440
128
400
480
1,280
1,320
128
400
480
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
560
240
480
240
480
240
1,200
2,280
2,080
1,960
80
1,120
1,960
1,840
1,880
80
1,040
1,600
1,560
1,800
80
IDD6
Normal
IDD7
2,720
2,600
2,560
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Operating Current Table(1-2) (TA=0oC, VDD= 1.9V)
M391T3253FG(Z)3 / M391T3253FG(Z)0 : 256MB(32Mx8 *9) ECC Module
E6
D5
CC
Symbol
Unit
Notes
(DDR2-667@CL=5)
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
945
1,035
72
270
315
315
135
675
1,890
1,665
1,530
45
900
990
72
225
270
270
135
630
1,575
1,440
1,485
45
855
900
72
225
270
270
135
585
1,215
1,170
1,440
45
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
Normal
IDD7
2,385
2,295
2,295
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M391T6453FG(Z)3 / M391T6453FG(Z)0 : 512MB(32Mx8 *18) ECC Module
E6
D5
CC
Symbol
Unit
Notes
(DDR2-667@CL=5)
(DDR2-533@CL=4)
(DDR2-400@CL=3)
IDD0
IDD1
1,620
1,710
144
540
630
1,530
1,620
144
450
540
1,440
1,485
144
450
540
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
630
270
540
270
540
270
1,350
2,565
2,340
2,205
90
1,260
2,205
2,070
2,115
90
1,170
1,800
1,755
2,025
90
IDD6
Normal
IDD7
3,060
2,925
2,880
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Input/Output Capacitance(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Parameter
Min
Max
Min
Max
Symbol
Units
M378T6453FG(Z)3
M378T6453FG(Z)0
M378T3253FG(Z)3
M378T3253FG(Z)0
Non-ECC
CCK0
-
-
-
-
24
25
25
42
-
-
-
-
26
28
28
42
CCK1
Input capacitance, CK and CK
CCK2
pF
CI
CI
Input capacitance, CKE and CS
1
2
Input capacitance, Addr,RAS,CAS,WE
Input/output capacitance, DQ, DM, DQS, DQS
-
-
42
6
-
-
42
10
CIO
Symbol
M391T6453FG(Z)3
M391T6453FG(Z)0
M391T3253FG(Z)3
M391T3253FG(Z)0
ECC
Units
CCK0
CCK1
CCK2
-
-
-
-
25
25
25
44
-
-
-
-
28
28
28
44
Input capacitance, CK and CK
pF
CI
Input capacitance, CKE and CS
1
CI
Input capacitance, Addr,RAS,CAS,WE
-
-
44
6
-
-
44
10
2
Input/output capacitance, DQ, DM, DQS, DQS
CIO
* DM is internally loaded to match DQ and DQS identically.
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-667/533/400 SDRAM
(0 °C < T
< 95 °C; V
= 1.8V + 0.1V; V = 1.8V + 0.1V)
DDQ DD
CASE
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
tREFI
75
105
127.5
195
tbd
ns
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
CASE
Average periodic refresh interval
85 °C < T
CASE
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin (CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-667(E6)
DDR2-533(D5)
DDR2-400(CC)
3 - 3 - 3
5 - 5- 5
4 - 4 - 4
Units
min
max
min
max
min
max
5
3.75
3
8
8
8
5
3.75
-
8
8
-
5
5
8
8
-
ns
ns
ns
ns
ns
ns
ns
-
15
15
54
39
15
15
55
40
15
15
55
40
tRP
tRC
70000
70000
70000
tRAS
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DDR2-667
DDR2-533
DDR2-400
min max
Parameter
Symbol
Units
Notes
min
max
+450
+400
0.55
0.55
min
max
+500
+450
0.55
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-450
-400
0.45
0.45
-500
-450
0.45
0.45
-600
-500
0.45
0.45
+600
+500
0.55
0.55
ps
ps
tDQSCK
tCH
tCK
tCK
CK low-level width
tCL
min(tCL,
tCH)
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
x
x
x
ps
20,21
Clock cycle time, CL=x
tCK
3000
175
8000
3750
225
8000
5000
275
8000
ps
ps
24
DQ and DM input hold time
tDH
x
x
x
15,16,17
15,16,17
DQ and DM input setup time
tDS
50
x
100
x
150
x
ps
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
tIPW
0.6
x
0.6
x
0.6
x
x
tCK
tCK
ps
tDIPW
tHZ
0.35
x
x
0.35
x
x
0.35
x
tAC max
tAC max
tAC max
tAC max
tAC max
tAC max
tAC max
350
tLZ(DQS)
tLZ(DQ)
tDQSQ
tQHS
tQH
tAC min
tAC min
tAC min
ps
27
27
22
21
2*tAC min tAC max 2* tACmin tAC max 2* tACmin
ps
x
x
250
x
x
300
x
x
ps
350
400
450
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
tHP - tQHS
WL-0.25
0.35
x
WL+0.25
x
tHP - tQHS
WL-0.25
0.35
x
WL+0.25
x
tHP - tQHS
WL-0.25
0.35
x
ps
tDQSS
tDQSH
WL+0.25
x
tCK
tCK
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
DDR2-667
DDR2-533
DDR2-400
Parameter
Symbol
Units
Notes
min
max
x
min
max
x
min
max
x
DQS input low pulse width
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH
0.35
0.2
0.35
0.2
0.35
0.2
tCK
tCK
tCK
tCK
tCK
tCK
ps
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
x
x
x
0.2
x
0.2
x
0.2
x
2
x
2
x
2
x
0.4
0.6
x
0.4
0.6
x
0.4
0.6
x
19
Write preamble
0.35
275
200
0.9
0.35
375
250
0.9
0.35
475
350
0.9
Address and control input hold time
Address and control input setup time
Read preamble
x
x
x
14,16,18
14,16,18
28
tIS
x
x
x
ps
tRPRE
tRPST
1.1
0.6
x
1.1
0.6
x
1.1
0.6
x
tCK
tCK
ns
Read postamble
0.4
0.4
0.4
28
Active to active command period for 1KB page size products tRRD
Active to active command period for 2KB page size products tRRD
7.5
7.5
7.5
12
10
x
10
x
10
x
ns
12
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
tFAW
tFAW
tCCD
tWR
37.5
50
37.5
50
37.5
50
ns
ns
2
2
2
tCK
ns
Write recovery time
15
x
x
x
15
x
x
x
15
x
x
x
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
tWR+tRP
7.5
tWR+tRP
7.5
tWR+tRP
10
tCK
ns
23
11
tWTR
tRTP
tXSNR
tXSRD
tXP
7.5
7.5
7.5
ns
tRFC + 10
200
2
tRFC + 10
200
2
tRFC + 10
200
2
ns
tCK
tCK
tCK
Exit precharge power down to any non-read command
Exit active power down to read command
x
x
x
x
x
x
tXARD
2
2
2
9
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
6 - AL
6 - AL
tCK
9, 10
CKE minimum pulse width
(high and low pulse width)
tCKE
3
2
3
2
3
2
tCK
tCK
ns
ODT turn-on delay
tAOND
tAON
2
2
2
tAC(max)+
0.7
tAC(max)+
1
tAC(max)+
1
ODT turn-on
tAC(min)
tAC(min)
tAC(min)
13, 25
26
tAC(min)+ 2tCK+tAC( tAC(min)+ 2tCK+tAC( tAC(min)+ 2tCK+tAC
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
ns
tCK
ns
2
max)+1
2.5
2
max)+1
2.5
2
(max)+1
2.5
2.5
2.5
2.5
tAC(max)+
0.6
tAC(max)+
0.6
tAC(max)+
0.6
ODT turn-off
tAC(min)
tAC(min)
tAC(min)
2.5tCK+
tAC(max)+
1
2.5tCK+
tAC(max)+
1
tAC(min)+ 2.5tCK+tA tAC(min)+
tAC(min)+
2
ODT turn-off (Power-Down mode)
tAOFPD
ns
2
C(max)+1
2
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
tCK
tCK
ns
12
12
12
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tDelay
ns
24
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Physical Dimensions: 32Mbx8 based 32Mx64/x72 Module(1 Rank)
M378T3253FG(Z)3 / M391T3253FG(Z)3
Units : Millimeters
M378T3253FG(Z)0 / M391T3253FG(Z)0
133.35
131.35
128.95
N/A
(for x64)
SPD
ECC
(for x72)
30.00
(2)
2.50
B
A
2.7
63.00
55.00
1.270 ± 0.10
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 32M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T56083QF
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Physical Dimensions: 32Mbx8 based 64Mx64/x72 Module(2 Ranks)
M378T6453FG(Z)3 / M391T6453FG(Z)3
Units : Millimeters
M378T6453FG(Z)0 / M391T6453FG(Z)0
133.35
131.35
128.95
N/A
(for x64)
SPD
ECC
30.00
(for x72)
(2)
2.50
B
A
4.00
63.00
55.00
N/A
(for x64)
ECC
(for x72)
1.270 ± 0.10
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
Detail B
1.50±0.10
Detail A
The used device is 32M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T56083QF
Rev. 1.3 Aug. 2005
256MB, 512MB Unbuffered DIMMs
DDR2 SDRAM
Revision History
Revision 1.0 (Jan. 2004)
- Initial Release
Revision 1.1 (Jun. 2004)
- Added lead-free part number in the ordering information
- Changed IDD2P
Revision 1.2 (Jan. 2005)
- Revised tIH value of 667 speed
Revision 1.3 (Aug. 2005)
- Added Dummy Pad PCB product part number in ordering information
Rev. 1.3 Aug. 2005
相关型号：
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