M381L1713FTM-CA2_技术文档

128MB, 256MB Unbuffered DIMM

DDR SDRAM

DDR SDRAM Unbuffered Module

184pin Unbuffered Module based on 128Mb F-die (x8)

64/72-bit ECC/Non ECC

Revision 1.0

March 2004

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

Revision History

Revision 1.0 (March, 2004))

- First release.

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

184Pin Unbuffered DIMM based on 128Mb F-die (x8)

Ordering Information

Part Number

M381L1713FTM-C(L)B3/A2/B0

Density

128MB

Organization

16M x 72

Component Composition

16Mx8( K4H280838F) * 9EA

Interface

1,250mil

Operating Frequencies

B3(DDR333@CL=2.5)

133MHz

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

Speed @CL2

Speed @CL2.5

CL-tRCD-tRP

133MHz

2-3-3

100MHz

133MHz

2.5-3-3

166MHz

2.5-3-3

Feature

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1,250 (mil), single (128MB), double (256MB) sided

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

Pin Configuration (Front side/back side)

Front

Back

1

VREF

DQ0

VSS

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

A5

DQ24

VSS

DQ25

DQS3

A4

VDD

DQ26

DQ27

A2

VSS

A1

CB0

CB1

VDD

DQS8

A0

CB2

VSS

CB3

BA1

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

VDDQ

/WE

93

94

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

VSS

A6

DQ28

DQ29

VDDQ

DM3

A3

DQ30

VSS

DQ31

CB4

CB5

VDDQ

CK0

/CK0

VSS

DM8

A10

CB6

VDDQ

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

/RAS

DQ45

VDDQ

/CS0

2

3

DQ41

/CAS

VSS

95

4

DQ1

DQS0

DQ2

VDD

DQ3

NC

96

5

97

/CS1

6

DQS5

DQ42

DQ43

VDD

*/CS2

DQ48

DQ49

VSS

/CK2

CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

98

DM5

VSS

7

99

8

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

*A13

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

NC

VSS

NC

DQ8

DQ9

DQS1

VDDQ

CK1

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

*BA2

DQ20

*A12

VSS

VDD

DM6

/CK1

VSS

DQ54

DQ55

VDDQ

NC

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ60

DQ61

VSS

KEY

KEY^CB7

VSS

53

54

55

56

57

58

59

60

61

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

145

146

147

148

149

150

151

152

153

DQ36

DQ37

VDD

DM7

DQS7

DQ58

DQ59

VSS

DQ21

A11

DQ62

DQ63

VDDQ

SA0

A9

DM2

VDD

DQ22

A8

DM4

DQ18

A7

DQ38

DQ39

VSS

BA0

DQ35

DQ40

NC

SA1

VDDQ

DQ19

SDA

SA2

SCL

DQ23

DQ44

VDDSPD

Note :

1. * : These pins are not used in this module.

2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module, and are not used on x64 module.

3. Pins 111, 158 are NC for 128MB modules & used for 256MB modules.

Pin Description

Pin Name

Function

Pin Name

Function

A0 ~ A11

Address input (Multiplexed) DM0 ~ 7, 8(for ECC) Data - in mask

BA0 ~ BA1

DQ0 ~ DQ63

DQS0 ~ DQS8

CK0,CK0 ~ CK2, CK2

CKE0, CKE1(for double banks) Clock enable input

CS0, CS1(for double banks)

Bank Select Address

Data input/output

Data Strobe input/output

Clock input

VDD

VDDQ

VSS

VREF

VDDSPD

SDA

Power supply (2.5V)

Power Supply for DQS(2.5V)

Ground

Power supply for reference

Serial EEPROM Power/Supply ( 2.3V to 3.6V )

Serial data I/O

Chip select input

RAS

CAS

WE

Row address strobe

Column address strobe

Write enable

SCL

SA0 ~ 2

NC

Serial clock

Address in EEPROM

No connection

CB0 ~ CB7 (for x72 module)

Check bit(Data-in/data-out)

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

128MB, 16M x 72 ECC Module (M381L1713FTM) (Populated as 1 bank of x8 DDR SDRAM Module)

Functional Block Diagram

CS0

DQS0

DM0

DQS4

DM4

DM/

CS DQS

DM/

I/O 5

CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 6

I/O 4

I/O 2

I/O 0

I/O 7

I/O 5

I/O 3

I/O 1

Serial PD

I/O 4

I/O 3

I/O 1

I/O 7

I/O 6

I/O 2

I/O 0

D0

D4

SCL

WP

SDA

SPD

A0

A1

A2

SA0 SA1 SA2

DQS1

DM1

DQS5

DM5

DM/

CS DQS

DM/

CS DQS

V

DDSPD

DQ8

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 5

I/O 1

I/O 0

I/O 6

I/O 4

I/O 3

I/O 2

I/O 7

I/O 4

I/O 3

I/O 0

I/O 6

I/O 5

I/O 2

I/O 1

D0 - D8

V

/V

DQ9

DD DDQ

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D0 - D8

VREF

D0 - D8

V

SS

DQS2

DM2

DQS6

DM6

D3/D0/D6

DM/

CS DQS

DM/

CS DQS

Cap/Cap/Cap

D4/D1/D7

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 6

I/O 5

I/O 3

I/O 0

I/O 7

I/O 4

I/O 2

I/O 1

I/O 6

I/O 4

I/O 3

I/O 2

I/O 7

I/O 5

I/O 1

I/O 0

D2

D6

R=120Ω

CK0/1/2

Card

Edge

Cap/Cap/Cap

D5/D2/D8

DQS3

DM3

DQS7

DM7

Cap/Cap/Cap

DM/

CS DQS

DM/

CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 4

I/O 3

I/O 1

I/O 6

I/O 5

I/O 2

I/O 0

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D3

D7

DQS8

DM8

DM/

CS DQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 5

I/O 4

I/O 1

I/O 0

I/O 7

I/O 6

I/O 3

I/O 2

D8

BA0 - BA1

A0 - A11

RAS

BA0-BA1 : DDR SDRAMs D0 - D8

A0-A11 : DDR SDRAMs D0 - D8

RAS : DDR SDRAMs D0 - D8

CAS : DDR SDRAMs D0 - D8

CKE : DDR SDRAMs D0 - D8

WE : DDR SDRAMs D0 - D8

Notes :

* Clock Wiring

DDR SDRAMs

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

Clock

Input

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

CAS

3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +

5%

*CK0/CK0 3 DDR SDRAMs

*CK1/CK1 3 DDR SDRAMs

*CK2/CK2 3 DDR SDRAMs

CKE0

WE

*Clock Net Wiring

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

Absolute Maximum Ratings

Parameter

Symbol

Value

Unit

Voltage on any pin relative to V_SS

V_IN, V_OUT

-0.5 ~ 3.6

V

Voltage on V_DD& V_DDQsupply relative to V_SS

Storage temperature

V_DD, V_DDQ

T_STG

P_D

-1.0 ~ 3.6

-55 ~ +150

V

°C

W

Power dissipation

1.5 * # of component

50

Short circuit current

I_OS

mA

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommend operation condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC Operating Conditions

Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter

Symbol

VDD

Min

2.3

Max

2.7

Unit

Note

Supply voltage(for device with a nominal VDD of 2.5V)

I/O Supply voltage

I/O Reference voltage

I/O Termination voltage(system)

VDDQ

VREF

V_TT

2.3

0.49*VDDQ

VREF-0.04

2.7

0.51*VDDQ

VREF+0.04

V

1

2

V

Input logic high voltage

Input logic low voltage

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

V-I Matching: Pullup to Pulldown Current Ratio

Input leakage current

VIH(DC)

VIL(DC)

VIN(DC)

VID(DC)

VI(Ratio)

II

VREF+0.15

-0.3

VDDQ+0.3

VREF-0.15

VDDQ+0.3

VDDQ+0.6

1.4

V

-0.3

0.36

0.71

-2

3

4

-

2

5

uA

mA

Output leakage current

Output High Current(Normal strengh driver) ;V_OUT= V_TT+ 0.84V

IOZ

-5

IOH

-16.8

Output High Current(Normal strengh driver) ;V_OUT= V_TT- 0.84V

Output High Current(Half strengh driver) ;V_OUT= V_TT+ 0.45V

Output High Current(Half strengh driver) ;V_OUT= V_TT- 0.45V

IOL

IOH

IOL

16.8

-9

mA

9

Note :

1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.

Peak-to peak noise on VREF may not exceed +/-2% of the dc value.

2. V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal to

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire

temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the

maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the

maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

DDR SDRAM IDD spec table

M381L1713FTM [ (16M x 8) * 9 , 128MB Module ]

(V_DD=2.7V, T = 10°C)

Symbol

IDD0

IDD1

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

Unit

mA

Notes

770

990

770

990

680

900

30

180

140

230

320

1,080

1,130

1,400

20

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

30

200

180

230

30

180

140

230

320

1,080

1,130

1,400

20

360

1,260

1,310

1,490

20

10

2,700

IDD6

Normal

Low power

IDD7A

10

2,250

Optional

2,700

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

AC Operating Conditions

Max

Parameter/Condition

Symbol

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

Min

Unit

V

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and CK inputs

VREF + 0.31

3

1

2

VREF - 0.31

VDDQ+0.6

0.5*VDDQ-0.2 0.5*VDDQ+0.2

0.7

Input Crossing Point Voltage, CK and CK inputs

Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V_IXis expected to equal 0.5*V_DDQof the transmitting device and must track variations in the DC level of the same.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in

simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

Vtt=0.5*VDDQ

RT=50Ω

Output

Z0=50Ω

CLOAD=30pF

VREF

=0.5*VDDQ

Output Load Circuit (SSTL_2)

Input/Output Capacitance

(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)

M381L1713FTM

Unit

Parameter

Symbol

Min

51

44

25

6

Max

60

53

30

7

Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS,WE )

Input capacitance(CKE0)

Input capacitance( CS0)

Input capacitance( CLK0, CLK1,CLK2)

Input capacitance(DM0~DM7, DM8(fpr ECC))

Data & DQS input/output capacitance(DQ0~DQ63)

Data input/output capacitance (CB0~CB7)

CIN1

CIN2

CIN3

CIN4

CIN5

Cout1

Cout2

pF

6

7

6

7

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

AC Timming Parameters & Specifications

B3

(DDR333@CL=2.5))

A2

B0

(DDR266@CL=2.5))

(DDR266@CL=2.0)

Parameter

Symbol

Unit

Note

Min

60

Max

Min

65

Max

Min

65

Max

Row cycle time

tRC

tRFC

tRAS

tRCD

tRP

ns

Refresh row cycle time

Row active time

72

75

42

70K

45

120K

45

120K

ns

RAS to CAS delay

18

20

ns

Row precharge time

18

20

ns

Row active to Row active delay

Write recovery time

tRRD

tWR

12

15

ns

15

ns

Last data in to Read command

Col. address to Col. address delay

tWTR

tCCD

1

tCK

ns

1

CL=2.0

CL=2.5

7.5

6

12

7.5

0.45

-0.75

-

12

10

12

Clock cycle time

tCK

12

7.5

0.45

-0.75

-

ns

Clock high level width

tCH

tCL

0.45

-0.6

-0.7

-

0.55

+0.6

+0.7

0.45

1.1

0.55

+0.75

0.5

0.55

+0.75

0.5

tCK

ns

Clock low level width

DQS-out access time from CK/CK

Output data access time from CK/CK

Data strobe edge to ouput data edge

Read Preamble

tDQSCK

tAC

ns

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPRE

tDSS

tDSH

tDQSH

tDQSL

tDSC

tIS

ns

12

3

0.9

0.4

0.75

0

0.9

0.4

0.75

0

1.1

0.9

0.4

0.75

0

1.1

tCK

ns

Read Postamble

0.6

CK to valid DQS-in

1.25

DQS-in setup time

DQS-in hold time

0.25

0.2

0.35

0.9

0.75

0.8

0.25

0.2

0.35

0.9

1.0

0.25

0.2

0.35

0.9

1.0

tCK

ns

DQS falling edge to CK rising-setup time

DQS falling edge from CK rising-hold time

DQS-in high level width

DQS-in low level width

DQS-in cycle time

1.1

Address and Control Input setup time(fast)

Address and Control Input hold time(fast)

Address and Control Input setup time(slow)

Address and Control Input hold time(slow)

Data-out high impedence time from CK/CK

Data-out low impedence time from CK/CK

Input Slew Rate(for input only pins)

Input Slew Rate(for I/O pins)

i,5.7~9

i, 6~9

1

tIH

ns

tIS

ns

tIH

ns

tHZ

+0.7

+0.75

ns

tLZ

-0.7

0.5

-0.75

0.5

-0.75

0.5

ns

1

tSL(I)

tSL(IO)

tSL(O)

tSLMR

V/ns

0.5

Output Slew Rate(x4,x8)

1.0

4.5

1.5

1.0

4.5

1.5

1.0

4.5

1.5

Output Slew Rate Matching Ratio(rise to fall)

0.67

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

B3

(DDR333@CL=2.5))

A2

B0

(DDR266@CL=2.5))

(DDR266@CL=2.0)

Parameter

Symbol

Unit

Note

Min

12

Max

Min

15

Max

Min

15

Max

Mode register set cycle time

DQ & DM setup time to DQS

DQ & DM hold time to DQS

tMRD

tDS

ns

0.45

0.5

j, k

tDH

0.45

0.5

Control & Address input pulse width

DQ & DM input pulse width

Power down exit time

tIPW

tDIPW

tPDEX

tXSNR

tXSRD

tREFI

2.2

1.75

6

2.2

1.75

7.5

2.2

1.75

7.5

ns

8

ns

Exit self refresh to non-Read command

Exit self refresh to read command

Refresh interval time

75

ns

200

tCK

us

15.6

-

15.6

-

15.6

-

4

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

Output DQS valid window

Clock half period

tQH

tHP

ns

11

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

-

10, 11

Data hold skew factor

tQHS

0.55

0.6

0.75

0.6

0.75

0.6

ns

11

2

DQS write postamble time

tWPST

0.4

18

0.4

20

0.4

20

tCK

Active to Read with Auto precharge

command

tRAP

Autoprecharge write recovery +

Precharge time

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

(tWR/tCK)

+

(tRP/tCK)

tDAL

tCK

13

System Characteristics for DDR SDRAM

The following specification parameters are required in systems using DDR333 & DDR266 devices to ensure proper sys-

tem performance. these characteristics are for system simulation purposes and are guaranteed by design.

Table 1 : Input Slew Rate for DQ, DQS, and DM

AC CHARACTERISTICS

DDR333

DDR266

PARAMETER

SYMBOL

DCSLEW

MIN

MAX

MIN

MAX

Units

V/ns

Notes

a, m

DQ/DM/DQS input slew rate measured between

VIH(DC), VIL(DC) and VIL(DC), VIH(DC)

TBD

Table 2 : Input Setup & Hold Time Derating for Slew Rate

Input Slew Rate

tIS

tIH

Units

Notes

0.5 V/ns

0

ps

i

0.4 V/ns

+50

+100

0

ps

0.3 V/ns

0

ps

Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate

Input Slew Rate

tDS

tDH

Units

Notes

0.5 V/ns

0

ps

k

0.4 V/ns

+75

+150

+75

+150

ps

0.3 V/ns

ps

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Delta Slew Rate

tDS

tDH

Units

Notes

+/- 0.0 V/ns

0

ps

j

+/- 0.25 V/ns

+/- 0.5 V/ns

+50

+100

+50

+100

ps

Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)

Typical Range

Minimum

(V/ns)

Maximum

(V/ns)

Slew Rate Characteristic

Notes

(V/ns)

Pullup Slew Rate

Pulldown slew

1.2 ~ 2.5

1.0

4.5

a,c,d,f,g,h

b,c,d,f,g,h

Table 6 : Output Slew Rate Characteristice (X16 Devices only)

Typical Range

Minimum

(V/ns)

Maximum

(V/ns)

Slew Rate Characteristic

Notes

(V/ns)

Pullup Slew Rate

Pulldown slew

1.2 ~ 2.5

0.7

5.0

a,c,d,f,g,h

b,c,d,f,g,h

Table 7 : Output Slew Rate Matching Ratio Characteristics

AC CHARACTERISTICS DDR333

DDR266

PARAMETER

Output Slew Rate Matching Ratio (Pullup to Pulldown)

MIN

TBD

MAX

TBD

MIN

TBD

MAX

TBD

Notes

e,m

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

Component Notes

1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a

specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).

2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys

tem performance (bus turnaround) will degrade accordingly.

3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A

valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ

ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could

be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

5. For command/address input slew rate ≥ 1.0 V/ns

6. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns

7. For CK & CK slew rate ≥ 1.0 V/ns

8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by

device design or tester correlation.

9. Slew Rate is measured between VOH(ac) and VOL(ac).

10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the

period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into

the clock traces.

11. tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The

pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst

case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-

channel to n-channel variation of the output drivers.

12. tDQSQ

Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given

cycle.

13. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and

tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)

tDAL = 5 clocks

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

System Notes :

a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.

Test point

Output

50Ω

VSSQ

Figure 1 : Pullup slew rate test load

b. Pulldown slew rate is measured under the test conditions shown in Figure 2.

VDDQ

50Ω

Output

Test point

Figure 2 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output

switching.

Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions

Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process

Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process

Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and

voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divices only.

h. Only intended for operation up to 266 Mbps per pin.

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns

as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or

VIH(DC) to VIL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.

Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the

slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this

would result in the need for an increase in tDS and tDH of 100 ps.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser

on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter

mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.

m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotony.

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

Command Truth Table

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

A0 ~ A9

Note

COMMAND

CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP

A11

Register

Extended MRS

Mode Register Set

Auto Refresh

H

X

H

L

OP CODE

1, 2

3

H

L

H

X

Entry

Refresh

Self

Refresh

L

H

L

H

X

L

H

X

H

X

H

Exit

L

H

X

3

Bank Active & Row Addr.

H

V

Row Address

(A0~A9, A11)

Read &

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

L

H

L

4

4, 6

7

Column

Address

H

X

L

H

L

H

V

Column Address

Write &

Column Address

Column

Address

H

X

L

H

L

H

L

H

Burst Stop

Precharge

X

Bank Selection

All Banks

V

X

L

H

X

5

H

L

X

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

Exit

H

L

H

L

Active Power Down

X

Entry

H

Precharge Power Down Mode

H

L

Exit

L

H

X

DM

X

8

9

H

L

X

H

X

H

No operation (NOP) : Not defined

Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Rev. 1.0 March. 2004

128MB, 256MB Unbuffered DIMM

DDR SDRAM

Physical Dimensions : 16M x72 (M381L1713FTM)

Units : Inches (Millimeters)

5.25 ± 0.006

(133.350 ± 0.13)

0.118

(3.00 Min)

5.077

(128.950)

1.25 ± 0.006

±0.15)

(31.75

N/A

(for x64)

ECC

(for x72)

A

B

2.500 +0.1/-0.0

0.10 M

C

B

A

0.07 Max

(1.20 Max)

2.55

(64.77)

1.95

(49.53)

0.050 ± 0.0039

(1.270 ± 0.10)

0.118

(3.00)

0.250

(6.350)

0.157

(4.00)

0.039 ± 0.002

0.26

(1.000 ± 0.050)

(6.62)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

Detail A

0.071

(1.80)

0.050

(1.270)

0.1575

(4.00+/-0.1)

C

0.10

B

AM

M

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 16Mx8 DDR SDRAM, TSOPII.

DDR SDRAM Part No : K4H280838F

Rev. 1.0 March. 2004


型号：	M381L1713FTM-CA2
厂家：	SAMSUNG
描述：	DDR DRAM Module, 16MX72, 0.75ns, CMOS, DIMM-184 时钟动态存储器双倍数据速率内存集成电路
文件：	总15页 (文件大小：273K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M381L1713FTM-CA2 [SAMSUNG]

相关型号：

M381L2923BTM-CB3

M381L2923BTM-CC4

M381L2923BTM-CCC

M381L2923BTM-LB3

M381L2923BTM-LC4

M381L2923BTM-LCC

M381L2923BUM-CA2

M381L2923BUM-CAA

M381L2923BUM-CB0

M381L2923BUM-CB3

M381L2923BUM-CC4

M381L2923BUM-CCC