M381L2923CUM-CCC [SAMSUNG]
DDR SDRAM Unbuffered Module; DDR SDRAM的无缓冲模块
| 型号： | M381L2923CUM-CCC |
| 厂家： | 
SAMSUNG |
| 描述： | DDR SDRAM Unbuffered Module |
| 文件： | 总25页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
DDR SDRAM Unbuffered Module
184pin Unbuffered Module based on 512Mb C-die
with 64/72-bit ECC/Non ECC
66 TSOP-II with Pb-Free
(RoHS compliant)
Revision 1.0
February. 2005
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
512Mb C-die Revision History
Revision 0.0 (April, 2004)
- First version for internal review
Revision 0.1 (August, 2004)
- Preliminary spec release.
Revision 0.2 (October, 2004)
- Changed IDD current.
Revision 1.0 (February, 2005)
- Revision 1.0 spec. release.
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
184Pin Unbuffered DIMM based on 512Mb C-die (x8, x16)
Ordering Information
Part Number
Density
256MB
512MB
512MB
1GB
Organization
32M x 64
Component Composition
Height
1,250mil
1,250mil
1,250mil
1,250mil
1,250mil
M368L3324CUS-C(L)CC/B3
M368L6523CUS-C(L)CC/B3
M381L6523CUM-C(L)CC/B3
M368L2923CUN-C(L)CC/B3
M381L2923CUM-C(L)CC/B3
32Mx16 (K4H511638C) * 4EA
64Mx8 (K4H510838C) * 8EA
64Mx8 (K4H510838C) * 9EA
64Mx8 (K4H510838C) * 16EA
64Mx8 (K4H510838C) * 18EA
64M x 64
64M x 72
128M x 64
128M x 72
1GB
Operating Frequencies
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
-
133MHz
166MHz
-
166MHz
200MHz
3-3-3
2.5-3-3
Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil) & single (256, 512MB), double (1GB) sided
• SSTL_2 Interface
• 66pin TSOP II Pb-Free package
• RoHS compliant
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Pin Configuration (Front side/back side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
2
3
4
5
6
7
8
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
*/CS2
DQ48
DQ49
VSS
93
94
95
96
97
VSS
DQ4
DQ5
VDDQ
DM0
DQ6
DQ7
VSS
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
A6
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DM8
A10
98
99
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
9
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NC
VSS
VSS
A1
DQ8
DQ9
DQS1
VDDQ
CK1
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
A12
VSS
DQ21
A11
DM2
VDD
DQ22
A8
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
/CK2
CK2
VDD
DM6
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
/CK1
VSS
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
CB6
VDDQ
CB7
KEY
KEY
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
DM7
DQ62
DQ63
VDDQ
SA0
SA1
SA2
DM4
DQ38
DQ39
VSS
NC
SDA
SCL
DQ23
DQ44
VDDSPD
Note :
1. * : These pins are not used in this module.
2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module ( M381~ ), and are not used on x64 module.
3. Pins 111, 158 are NC for 1row modules & used for 2row modules[ M368(81)L2923CUN(M) ].
4. Pins 137, 138 are NC for x16 1Row module (M368L3324CUS).
Pin Description
Pin Name
Function
Pin Name
Function
A0 ~ A12
Address input (Multiplexed) DM0 ~ 7, 8(for ECC) Data - in mask
Power supply
BA0 ~ BA1
Bank Select Address
VDD
(2.5V for DDR333, 2.6V for DDR400)
Power Supply for DQS
(2.5V for DDR333, 2.6V for DDR400)
DQ0 ~ DQ63
Data input/output
VDDQ
DQS0 ~ DQS8
Data Strobe input/output
Clock input
VSS
Ground
CK0,CK0 ~ CK2, CK2
VREF
VDDSPD
SDA
Power supply for reference
Serial EEPROM Power/Supply ( 2.3V to 3.6V )
Serial data I/O
CKE0, CKE1(for double banks) Clock enable input
CS0, CS1(for double banks)
Chip select input
RAS
Row address strobe
Column address strobe
Write enable
SCL
Serial clock
CAS
SA0 ~ 2
NC
Address in EEPROM
No connection
WE
CB0 ~ CB7 (for x72 module)
Check bit(Data-in/data-out)
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
256MB, 32M x 64 Non ECC Module (M368L3324CUS) (Populated as 1 bank of x16 DDR SDRAM Module)
Functional Block Diagram
CS0
LDQS
LDM
LDQS
LDM
DQS1
DM1
DQS5
DM5
CS
CS
DQ13
DQ14
DQ12
DQ15
DQ9
DQ10
DQ8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ41
DQ42
DQ45
DQ43
DQ44
DQ46
DQ40
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
D0
D2
DQ11
DQS0
DM0
DQS0
DM0
DQ0
DQ3
DQ4
DQ7
DQ5
DQ2
DQ1
DQ6
DQ32
DQ35
DQ36
DQ39
DQ33
DQ38
DQ37
DQ34
LDQS
LDQS
DQS3
DM3
CS
DQS3
DM3
CS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
UDQS
DQ57
DQ62
DQ56
DQ58
DQ61
DQ63
DQ60
DQ59
DQ29
DQ26
DQ25
DQ30
DQ28
DQ27
DQ24
DQ31
D1
D3
DQS0
DM0
DQS0
DM0
UDM
UDM
I/O 8
I/O 9
DQ20
DQ23
DQ16
DQ19
DQ17
DQ22
DQ21
DQ18
DQ48
DQ51
DQ52
DQ50
DQ49
DQ55
DQ53
DQ54
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
*Clock Net Wiring
D0/D2
BA0 - BA1
A0 - A12
BA0-BA1: DDR SDRAMs D0 - D3
A0-A12: DDR SDRAMs D0 - D3
Cap
Cap
R=120Ω
RAS
RAS: DDR SDRAMs D0 - D3
CAS: DDR SDRAMs D0 - D3
CK1/2
Card
Edge
Clock Wiring
Cap
CAS
Clock
CKE: DDR SDRAMs D0 - D3
Input
CKE0
DDR SDRAMs
D1/D3
*If two DRAMs are loaded,
Cap will replace DRAM
NC
WE
WE: DDR SDRAMs D0 - D3
CK0/CK0
CK1/CK1
CK2/CK2
2 DDR SDRAMs
2 DDR SDRAMs
Cap
VDDSPD
SPD
Notes:
Serial PD
VDD/VDDQ
D0 - D3
1. DQ-to-I/O wiring is shown as recomended but
may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 7.5 Ohms
+ 5%
SCL
WP
D0 - D3
SDA
VREF
VSS
A0
A1
A2
D0 - D3
D0 - D3
SA0 SA1 SA2
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
512MB, 64M x 64 Non ECC Module (M368L6523CUS) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS0
DQS0
DM0
DQS4
DM4
DM/
CS DQS
DM/
I/O 7
I/O 4
I/O 1
I/O 3
I/O 6
I/O 5
I/O 0
I/O 2
CS DQS
Serial PD
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 6
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 3
I/O 1
SCL
WP
D0
D4
SDA
A0
A1
A2
SA0 SA1 SA2
DQS1
DM1
DQS5
DM5
DM/
CS DQS
DM/
CS DQS
V
V
SPD
DDSPD
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 5
I/O 1
I/O 0
I/O 6
I/O 4
I/O 3
I/O 2
I/O 6
I/O 4
I/O 3
I/O 1
I/O 7
I/O 5
I/O 2
I/O 0
D0 - D7
D0 - D7
/V
D1
D5
DD DDQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D0 - D7
D0 - D7
VREF
V
SS
DQS2
DM2
DQS6
DM6
D3/D0/D5
DM/
CS DQS
DM/
CS DQS
Cap/Cap/Cap
Cap/D1/D6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 6
I/O 5
I/O 3
I/O 0
I/O 7
I/O 4
I/O 2
I/O 1
I/O 7
I/O 5
I/O 1
I/O 0
I/O 6
I/O 4
I/O 3
I/O 2
D2
D6
R=120Ω
CK0/1/2
Card
Edge
CK0/1/2
Cap/Cap/Cap
D4/D2/C7
DQS3
DM3
DQS7
DM7
Cap
Cap/Cap/Cap
DM/
CS DQS
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 4
I/O 2
I/O 1
I/O 6
I/O 5
I/O 3
I/O 0
I/O 5
I/O 4
I/O 1
I/O 0
I/O 7
I/O 6
I/O 3
I/O 2
D3
D7
Notes :
* Clock Wiring
DDR SDRAMs
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
BA0 - BA1
A0 - A12
RAS
BA0-BA1 : DDR SDRAMs D0 - D7
A0-A12 : DDR SDRAMs D0 - D7
RAS : DDR SDRAMs D0 - D7
CAS : DDR SDRAMs D0 - D7
CKE : DDR SDRAMs D0 - D7
WE : DDR SDRAMs D0 - D7
Clock
Input
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
*CK0/CK0 2 DDR SDRAMs
*CK1/CK1 3 DDR SDRAMs
*CK2/CK2 3 DDR SDRAMs
CAS
CKE0
WE
*Clock Net Wiring
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
512MB, 64M x 72 ECC Module (M381L6523CUM) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS0
DQS0
DM0
DQS4
DM4
DM/
CS DQS
DM/
I/O 7
I/O 4
I/O 3
I/O 0
I/O 6
I/O 5
I/O 2
I/O 1
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 6
I/O 4
I/O 2
I/O 0
I/O 7
I/O 5
I/O 3
I/O 1
Serial PD
D0
D4
SCL
WP
SDA
SPD
A0
A1
A2
SA0 SA1 SA2
DQS1
DM1
DQS5
DM5
DM/
CS DQS
DM/
CS DQS
V
DDSPD
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 5
I/O 1
I/O 0
I/O 6
I/O 4
I/O 3
I/O 2
I/O 6
I/O 4
I/O 3
I/O 2
I/O 7
I/O 5
I/O 1
I/O 0
D0 - D8
D0 - D8
V
/V
DD DDQ
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D0 - D8
D0 - D8
VREF
V
SS
DQS2
DM2
DQS6
DM6
D3/D0/D6
DM/
CS DQS
DM/
CS DQS
Cap/Cap/Cap
D4/D1/D7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 6
I/O 5
I/O 3
I/O 0
I/O 7
I/O 4
I/O 2
I/O 1
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D2
D6
R=120Ω
CK0/1/2
CK0/1/2
Card
Edge
Cap/Cap/Cap
D5/D2/D8
DQS3
DM3
DQS7
DM7
Cap/Cap/Cap
DM/
CS DQS
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 4
I/O 3
I/O 1
I/O 6
I/O 5
I/O 2
I/O 0
I/O 5
I/O 4
I/O 1
I/O 0
I/O 7
I/O 6
I/O 3
I/O 2
D3
D7
DQS8
DM8
DM/
CS DQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 5
I/O 4
I/O 3
I/O 1
I/O 7
I/O 6
I/O 2
I/O 0
D8
BA0 - BA1
A0 - A12
RAS
BA0-BA1 : DDR SDRAMs D0 - D8
A0-A12 : DDR SDRAMs D0 - D8
RAS : DDR SDRAMs D0 - D8
CAS : DDR SDRAMs D0 - D8
CKE : DDR SDRAMs D0 - D8
WE : DDR SDRAMs D0 - D8
Notes :
* Clock Wiring
DDR SDRAMs
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 5.1 Ohms +
5%
Clock
Input
CAS
*CK0/CK0 3 DDR SDRAMs
*CK1/CK1 3 DDR SDRAMs
*CK2/CK2 3 DDR SDRAMs
CKE0
WE
*Clock Net Wiring
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
1GB, 128M x 64 Non ECC Module (M368L2923CUN) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS1
CS0
DQS0
DM0
DQS4
DM4
DM/
CS DQS
DM/
I/O 7
I/O 6
I/O 1
I/O 2
I/O 5
I/O 4
I/O 3
I/O 0
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 5
I/O 2
I/O 3
I/O 4
I/O 7
D8
D4
D12
D0
DQS1
DM1
DQS5
DM5
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 5
I/O 6
I/O 1
I/O 0
I/O 7
I/O 4
I/O 3
I/O 2
I/O 2
I/O 1
I/O 6
I/O 7
I/O 0
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D1
D9
D5
D13
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS6
DM6
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 5
I/O 4
I/O 1
I/O 0
I/O 7
I/O 6
I/O 3
I/O 2
I/O 2
I/O 3
I/O 6
I/O 7
I/O 0
I/O 1
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 2
I/O 5
I/O 4
I/O 3
I/O 0
I/O 0
I/O 1
I/O 6
I/O 5
I/O 2
I/O 3
I/O 4
I/O 7
D2
D10
D6
D14
DQS3
DM3
DQS7
DM7
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 5
I/O 6
I/O 1
I/O 0
I/O 7
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 2
I/O 1
I/O 6
I/O 7
I/O 0
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D3
D7
D11
D15
D3/D0/D5
V
V
SPD
DDSPD
D11/D8/D13
Serial PD
D0 - D15
D0 - D15
/V
DD DDQ
R=120Ω
SCL
WP
*
Cap/D1/D6
CK0/1/2
CK0/1/2
SDA
D0 - D15
D0 - D15
VREF
A0
A1
A2
Card
Edge
*
Cap/D9/D14
V
SA0 SA1
SA2
SS
D4/D2/D7
D12/D10/D15
BA0 - BA1
A0 - A12
RAS
BA0-BA1 : DDR SDRAMs D0 - D15
A0-A12: DDR SDRAMs D0 - D15
RAS : DDR SDRAMs D0 - D15
Notes :
* Clock Wiring
DDR SDRAMs
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
Clock
Input
CAS
CKE 0/1
WE
CAS : DDR SDRAMs D0 - D15
CKE : DDR SDRAMs D0 - D15
WE : DDR SDRAMs D0 - D15
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors: 3 Ohms +
5%
*CK0/CK0 4 DDR SDRAMs
*CK1/CK1 6 DDR SDRAMs
*CK2/CK2 6 DDR SDRAMs
*Clock Net Wiring
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
1GB, 128M x 72 ECC Module (M381L2923CUM) (Populated as 2 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS1
CS0
DQS0
DM0
DQS4
DM4
DM/
CS DQS
DM/
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D9
D4
D13
D0
DQS1
DM1
DQS5
DM5
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS6
DM6
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D2
D11
D6
D15
DQS3
DM3
DQS7
DM7
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DM/
CS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D3
D7
D12
D16
DQS8
DM8
DM/
CS DQS
DM/
CS DQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D8
D17
D3/D0/D5
D12/D9/D14
D8/D1/D6
R=120Ω
V
V
SPD
DDSPD
Serial PD
CK0/1/2
SCL
WP
Card
Edge
D0 - D17
D0 - D17
/V
DD DDQ
D17/D10/D15
D4/D2/D7
SDA
A0
A1
A2
D0 - D17
D0 - D17
VREF
SA0 SA1 SA2
V
D13/D11/D16
SS
Notes :
BA0 - BA1
A0 - A12
RAS
BA0-BA1 : DDR SDRAMs D0 - D17
A0-A12 : DDR SDRAMs D0 - D17
RAS : DDR SDRAMs D0 - D17
1. DQ-to-I/O wiring is shown as recommended
but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
* Clock Wiring
DDR SDRAMs
Clock
Input
3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.
4. BAx, Ax, RAS, CAS, WE resistors:3 Ohms +
5%
CAS
CKE0/1
WE
CAS : DDR SDRAMs D0 - D17
CKE : DDR SDRAMs D0 - D17
WE : DDR SDRAMs D0 - D17
*CK0/CK0 6 DDR SDRAMs
*CK1/CK1 6 DDR SDRAMs
*CK2/CK2 6 DDR SDRAMs
*Clock Net Wiring
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
VDD, VDDQ
TSTG
PD
-1.0 ~ 3.6
-55 ~ +150
V
°C
W
Power dissipation
1.5 * # of component
50
Short circuit current
IOS
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
Unit Note
Supply voltage(for device with a nominal VDD of 2.5V for DDR333)
Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
VDD
2.3
2.7
V
VDD
2.5
2.7
2.7
V
V
V
I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR333)
I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400)
I/O Reference voltage
VDDQ
VDDQ
VREF
VTT
2.3
2.5
2.7
0.49*VDDQ
VREF-0.04
0.51*VDDQ
VREF+0.04
V
V
1
2
I/O Termination voltage(system)
Input logic high voltage
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VI(Ratio)
II
VREF+0.15
-0.3
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.4
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
-0.3
V
0.36
0.71
-2
V
3
4
-
2
uA
uA
mA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOH
-16.8
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
IOH
IOL
16.8
-9
mA
mA
mA
9
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to
peak noise on VREF may not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temper-
ature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum
difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to mini-
mum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
DDR SDRAM IDD spec table
M368L3324CUS [ (32M x 16) * 4, 256MB Non ECC Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
480
640
20
420
560
20
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
120
100
180
240
760
860
880
20
120
100
120
180
680
740
820
20
IDD6
Normal
Low power
IDD7A
12
12
Optional
1,600
1,520
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM IDD spec table
DDR SDRAM
M368L6523CUS [ (64M x 8) * 8, 512MB Non ECC Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Unit
Notes
960
1,200
40
840
1,080
40
mA
mA
mA
mA
mA
mA
320
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
240
240
200
200
360
240
480
360
1,240
1,400
1,760
40
1,120
1,200
1,640
40
IDD6
Normal
Low power
IDD7A
24
24
Optional
3,080
2,880
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M381L6523CUM [ (64M x 8) * 9, 512MB ECC Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Unit
Notes
1,080
1,350
45
950
1,220
45
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
270
270
230
230
410
270
540
410
1,400
1,580
1,980
45
1,260
1,350
1,850
45
IDD6
Normal
Low power
IDD7A
27
27
Optional
3,470
3,240
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM IDD spec table
DDR SDRAM
M368L2923CUN [ (64M x 8) * 16, 1GB Non ECC Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Unit
Notes
1,440
1,680
80
1,200
1,440
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
480
480
400
400
720
480
960
720
1,720
1,880
2,240
80
1,480
1,560
2,000
80
IDD6
Normal
Low power
IDD7A
48
48
Optional
3,560
3,240
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M381L2923CUM [ (64M x 8) * 18, 1GB ECC Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
CC(DDR400@CL=3)
B3(DDR333@CL=2.5)
Unit
Notes
1,620
1,890
90
1,350
1,620
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
540
540
450
450
810
540
1,080
1,940
2,120
2,520
90
810
1,670
1,760
2,250
90
IDD6
Normal
Low power
IDD7A
54
54
Optional
4,010
3,650
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
AC Operating Conditions
Max
Parameter/Condition
Symbol
Min
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
VREF + 0.31
3
3
1
2
VREF - 0.31
VDDQ+0.6
V
0.7
V
Input Crossing Point Voltage, CK and CK inputs
0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
M368L3324CUS M368L6523CUS M381L6523CUM Unit
Parameter
Symbol
Min
41
34
34
25
6
Max
45
38
38
30
7
Min
49
42
42
25
6
Max
57
50
50
30
7
Min
51
44
44
25
6
Max
60
53
53
30
7
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
Input capacitance( CS0)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
6
7
6
7
6
7
-
-
-
-
6
7
M368L2923CUN
M381L2923CUM
Unit
Parameter
Symbol
Min
65
42
42
28
10
10
-
Max
81
50
50
34
12
12
-
Min
69
44
44
28
10
10
10
Max
87
53
53
34
12
12
12
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0,CKE1)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
Input capacitance( CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7, DM8(for ECC))
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
AC Timming Parameters & Specifications
CC
(DDR400@CL=3.0)
B3
(DDR333@CL=2.5)
Parameter
Symbol
Unit
Note
Min
55
Max
Min
60
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
Refresh row cycle time
Row active time
70
72
40
70K
42
70K
RAS to CAS delay
Row precharge time
15
18
15
18
Row active to Row active delay
Write recovery time
tRRD
tWR
10
12
15
15
Last data in to Read command
tWTR
2
1
CL=2.0
CL=2.5
CL=3.0
-
-
7.5
6
12
12
Clock cycle time
tCK
6
12
5
10
-
-
Clock high level width
tCH
tCL
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.45
1.1
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tIS
ns
22
13
0.9
0.4
0.72
0
1.1
0.9
0.4
0.75
0
tCK
tCK
tCK
ns
Read Postamble
0.6
0.6
CK to valid DQS-in
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.35
0.6
0.6
0.7
0.7
-
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.8
0.8
-
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS
15, 17~19
15, 17~19
16~19
16~19
11
tIH
ns
tIS
ns
tIH
ns
tHZ
+0.65
+0.65
+0.7
+0.7
ns
tLZ
-0.65
10
-0.7
12
ns
11
tMRD
tDS
ns
0.4
0.45
ns
j, k
j, k
ns
DQ & DM hold time to DQS
tDH
0.4
0.45
Control & Address input pulse width
DQ & DM input pulse width
tIPW
tDIPW
tXSNR
tXSRD
tREFI
2.2
1.75
75
2.2
1.75
75
ns
ns
18
18
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
ns
200
200
tCK
us
7.8
7.8
14
21
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
ns
ns
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
20, 21
Data hold skew factor
tQHS
0.5
0.6
0.55
0.6
ns
21
12
DQS write postamble time
tWPST
0.4
15
0.4
18
tCK
Active to Read with Auto precharge
command
tRAP
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
Autoprecharge write recovery +
Precharge time
tDAL
tCK
23
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333 devices to ensure proper system perfor-
mance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR400
DDR333
PARAMETER
SYMBOL
DCSLEW
MIN
TBD
MAX
TBD
MIN
TBD
MAX
TBD
Units
V/ns
Notes
a, m
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
∆tIS
0
∆tIH
0
Units
ps
Notes
i
i
i
0.4 V/ns
+50
+100
0
ps
0.3 V/ns
0
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
∆tDS
0
∆tDH
0
Units
ps
Notes
k
k
k
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
+/- 0.0 V/ns
∆tDS
0
∆tDH
0
Units
ps
Notes
j
j
j
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g,h
b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g,h
b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS DDR400
DDR333
PARAMETER
Output Slew Rate Matching Ratio (Pullup to Pulldown)
MIN
TBD
MAX
TBD
MIN
TBD
MAX
TBD
Notes
e,m
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Component Notes
1. All voltages referenced to Vss.
2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels,
but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be
either a precise representation of the typical system environment nor a depiction of the actual load presented by a production
tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment.
Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester elec-
tronics).
VDDQ
50Ω
Output
(Vout)
30pF
Figure 1 : Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to
VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under nor-
mal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac).
5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result
of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc
input LOW (HIGH) level.
6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.2VDDQ is
recognized as LOW.
7. Enables on.chip refresh and address counters.
8. IDD specifications are tested after the device is properly initialized.
9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level
for signals other than CK/CK, is VREF.
10. The output timing reference voltage level is VTT.
11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to
a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
15. For command/address input slew rate ≥ 1.0 V/ns
16. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Component Notes
17. For CK & CK slew rate ≥ 1.0 V/ns
18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
19. Slew Rate is measured between VOH(ac) and VOL(ac).
20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
21. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
22. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
23. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
System Notes :
DDR SDRAM
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.
Test point
Output
50Ω
VSSQ
Figure 2 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 3.
VDDQ
50Ω
Output
Test point
Figure 3 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V(for DDR333) and 2.6V(for DDR400), typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V(for DDR333) and 2.5V(for DDR400), slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V(for DDR333) and 2.7V(for DDR400), fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotonic.
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Command Truth Table
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
A0 ~ A9
Note
COMMAND
CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP
A11, A12
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
V
V
Row Address
L
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
4
4
Column
Address
L
H
L
H
H
L
Write &
Column Address
4
Column
Address
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Physical Dimensions : 32Mx64 (M368L3324CUS)
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.077
(128.950)
1.25 ± 0.006
±0.15)
(31.75
A
B
2.500 +0.1/-0.0
0.10 M
C
B
A
1.95
(49.53)
2.55
(64.77)
0.098 Max
(2.47 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00 Min)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575 ± 0.004
(4.00 ± 0.1)
Detail A
0.10
C
M
AM
B
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 32Mx16 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H511638C-U***
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Physical Dimensions : 64Mx64 (M368L6523CUS)
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00Min)
5.077
(128.950)
1.25 ± 0.006
±0.15)
(31.75
A
B
2.500 +0.1/-0.0
0.10 M
C
B
A
0.07 Max
2.55
1.95
(64.77)
(49.53)
(1.20 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00Min)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ± 0.006
(0.20 ± 0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575 ± 0.004
(4.00 ± 0.1)
C
Detail A
0.10
B
AM
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 64Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H510838C-U***
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Physical Dimensions : 64Mx72 (M381L6523CUM)
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.077
(128.950)
1.25 ± 0.006
±0.15)
(31.75
A
B
2.500 +0.1/-0.0
0.10 M
C
B
A
0.07 Max
2.55
1.95
(64.77)
(49.53)
(1.20 Max)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00 Min)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ± 0.006
(0.20 ± 0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575 ± 0.004
(4.00 ± 0.1)
C
Detail A
0.10
B
AM
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 64Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H510838C-U***
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Physical Dimensions : 128Mx64 (M368L2923CUN)
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.077
(128.950)
1.25 ± 0.006
±0.15)
(31.75
A
B
2.500 +0.1/-0.0
0.10 M
C
B
A
2.55
(64.77)
0.145 Max
(3.67 Max)
1.95
(49.53)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00 Min)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ± 0.006
(0.20 ± 0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575 ± 0.004
(4.00 ± 0.1)
C
Detail A
0.10
B
AM
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 64Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H510838C-U***
Rev. 1.0 February. 2005
256MB, 512MB, 1GB Unbuffered DIMM
DDR SDRAM
Physical Dimensions : 128Mx72 (M381L2923CUM)
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118 Min
(3.00 Min)
5.077
(128.950)
1.25 ± 0.006
±0.15)
(31.75
A
B
2.500 +0.1/-0.0
0.10 M
C
B
A
2.55
(64.77)
0.145 Max
(3.67 Max)
1.95
(49.53)
0.050 ± 0.0039
(1.270 ± 0.10)
0.118 Min
(3.00 Min)
0.250
(6.350)
0.039 ± 0.002
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ± 0.006
(0.20 ± 0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575 ± 0.004
(4.00 ± 0.1)
C
Detail A
0.10
B
AM
M
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified.
The used device is 64Mx8 DDR SDRAM, TSOPII.
DDR SDRAM Part No : K4H510838C-U***
Rev. 1.0 February. 2005
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