M383L3223EUS-CA0_技术文档

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

DDR SDRAM Registered Module

184pin Registered Module based on 256Mb E-die (x4, x8)

with 1,700 / 1,200mil Height & 72-bit ECC

66 TSOP(II) with Pb-Free

(RoHS compliant)

Revision 1.1

Oct. 2004

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

Revision History

Revision 1.0 (February. 2004)

-First release

Revision 1.1 (October, 2004)

-Corrected typo

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

184Pin Registered DIMM based on 256Mb E-die (x4, x8)

Ordering Information

Part Number

Density

256MB

512MB

1GB

Organization

32M x 72

64M x 72

128M x 72

32M x 72

64M x 72

128M x 72

Component Composition

Height

1,700mil

1,200mil

M383L3223EUS-CAA/A2/B0/A0

M383L6423EUS-CAA/A2/B0/A0

M383L6420EUS-CAA/A2/B0/A0

M383L2828EU1-CAA/A2/B0/A0

M312L3223EUS-CAA/A2/B0/A0

M312L6423EUS-CAA/A2/B0/A0

M312L6420EUS-CAA/A2/B0/A0

M312L2828EU0-CAA/A2/B0/A0

32Mx8( K4H560838E) * 9EA

32Mx8( K4H560838E) * 18EA

64Mx4( K4H560438E) * 18EA

st.128Mx4( K4H510638E) * 18EA

32Mx8( K4H560838E) * 9EA

32Mx8( K4H560838E) * 18EA

64Mx4( K4H560438E) * 18EA

st.128Mx4( K4H510638E) * 18EA

256MB

512MB

1GB

Operating Frequencies

AA(DDR266@CL=2)

A2(DDR266@CL=2)

133MHz

B0(DDR266@CL=2.5)

100MHz

A0(DDR200@CL=2)

Speed @CL2

Speed @CL2.5

CL-tRCD-tRP

133MHz

2-2-2

100MHz

133MHz

-

2-3-3

2.5-3-3

2-2-2

Feature

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• 1,700mil / 1,200mil height & double sided

• SSTL_2 Interface Pb-Free

• RoHS compliant

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

Pin Configuration (Front side/back side)

Front

Back

1

2

3

4

5

6

7

8

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

NC

/RESET

VSS

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

A5

DQ24

VSS

DQ25

DQS3

A4

VDD

DQ26

DQ27

A2

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42

DQ43

VDD

*/CS2

DQ48

DQ49

VSS

*CK2

*/CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

93

94

95

96

97

VSS

DQ4

DQ5

124

125

126

127

128

VSS

A6

DQ28

DQ29

VDDQ

154

155

156

157

158

/RAS

DQ45

VDDQ

/CS0

VDDQ

DM0/DQS9

DQ6

/CS1

DM5/DQS14

VSS

98

99

129 DM3/DQS12 159

DQ7

VSS

NC

130

131

132

133

134

135

136

137

138

139

A3

DQ30

VSS

DQ31

CB4

CB5

VDDQ

CK0

160

161

162

163

164

165

166

167

168

169

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

*A13

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

VSS

A1

NC

DQ8

DQ9

VDDQ

DQ12

DQ13

DM1/DQS10

VDD

CB0

CB1

VDD

DQS8

A0

CB2

VSS

CB3

BA1

DQS1

VDDQ

*CK1

*/CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

/CK0

VSS

VDD

DM6/DQS15

DQ54

DQ55

VDDQ

NC

DQ14

DQ15

CKE1

VDDQ

*BA2

DQ20

A12

VSS

140 DM8/DQS17 170

141

142

143

144

A10

CB6

VDDQ

CB7

171

172

173

174

175

176

177

178

179

DQ60

DQ61

VSS

KEY

53

54

55

56

57

58

59

60

61

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

145

146

147

148

VSS

DQ36

DQ37

VDD

DM7/DQS16

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

DQS7

DQ58

DQ59

VSS

NC

SDA

DQ21

A11

DM2/DQS11

VDD

A9

DQ18

A7

VDDQ

DQ19

149 DM4/DQS13 180

150

151

152

153

DQ38

DQ39

VSS

181

182

183

184

DQ22

A8

DQ23

SCL

DQ44

Note :

1. * : These pins are not used in this module.

2. Pins 111, 158 are NC for 1row module[M383(12)L3223EUS, M383(12)L6420EUS] & used for 2row module [M383(12)L6423EUS,

M383(12)L2828EU1(0) ]

3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).

Pin Description

Pin Name

Function

Address input (Multiplexed)

Bank Select Address

Data input/output

Pin Name

DM0 ~ DM8

VDD

Function

A0 ~ A12

Data - in mask

BA0 ~ BA1

Power supply (2.5V)

Power Supply for DQS(2.5V)

Ground

DQ0 ~ DQ63

VDDQ

VSS

DQS0 ~ DQS17

CK0,CK0 ~ CK2, CK2

Data Strobe input/output

Clock input

VREF

Power supply for reference

Serial EEPROM Power/Supply ( 2.3V to 3.6V )

Serial data I/O

CKE0, CKE1(for double banks) Clock enable input

VDDSPD

SDA

CS0, CS1(for double banks)

Chip select input

RAS

Row address strobe

Column address strobe

Write enable

SCL

Serial clock

CAS

SA0 ~ 2

NC

Address in EEPROM

No connection

WE

CB0 ~ CB7

Check bit(Data-in/data-out)

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

256MB, 32M x 72 ECC Module (M383(12)L3223EUS) (Populated as 1 bank of x8 DDR SDRAM Module)

Functional Block Diagram

RCS0

DQS0

DM0

DQS4

DM4

DM/

CS DQS

DM/

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D0

D4

DQS1

DM1

DQS5

DM5

DM/

CS DQS

DM/

CS DQS

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D1

D5

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM/

CS DQS

DM/

CS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

D2

D6

DQS3

DM3

DQS7

DM7

DM/

CS DQS

DM/

CS DQS

Serial PD

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

SCL

WP

D3

D7

SDA

SPD

A0

A1

A2

SA0 SA1 SA2

DQS8

DM8

V

DDSPD

DM/

CS DQS

D0 - D8

V

/V

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DD DDQ

D8

D0 - D8

VREF

V

SS

PLL*

CK0,CK0

* Wire per Clock Loading table/wiring Diagrams

RCS0

CS0

R

E

G

I

S

T

E

R

Notes:

BA0 -BA1 : SDRAMs DQ0 - D8

A0 -A12 : SDRAMs D0 - D8

RAS : SDRAMs D0 - D8

CAS : SDRAMs D0 - D8

CKE : SDRAMs D0 - D8

WE: SDRAMs D0 - D8

RBA0 - RBA1

RA0 - RA12

RRAS

RCAS

RCKE0

BA0-BA1

A0-A12

RAS

CAS

CKE0

WE

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships

must be maintained as shown.

RWE

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

PCK

RESET

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

512MB, 64M x 72 ECC Module (M383(12)L6423EUS) (Populated as 2 bank of x8 DDR SDRAM Module)

Functional Block Diagram

RCS1

RCS0

DQS0

DM0

DQS4

DM4

DM/

CS DQS

DM/

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D9

D4

D13

D0

DQS1

DM1

DQS5

DM5

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D1

D10

D5

D14

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DQS6

DM6

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D2

D11

D6

D15

DQS3

DM3

DQS7

DM7

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DM/

CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D3

D7

D12

D16

DQS8

DM8

DM/

CS DQS

DM/

CS DQS

V

SPD

DDSPD

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

D8

D17

D0 - D17

/V

DD DDQ

D0 - D17

VREF

V

SS

Serial PD

SCL

WP

SDA

A0

A1

A2

PLL*

CK0,CK0

SA0 SA1 SA2

* Wire per Clock Loading table/wiring Diagrams

CS0

CS1

BA0-BA1

RCS0

RCS1

RBA0 - RBA1

RA0 - RA12

RRAS

R

E

G

I

S

T

E

R

Notes:

BA0 -BAn : SDRAMs DQ0 - D17

A0 -A12 : SDRAMs D0 - D17

RAS : SDRAMs D0 - D17

CAS : SDRAMs DQ0 - D17

CKE : SDRAMs D0 - D8

A0-A12

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships

must be maintained as shown.

RAS

CAS

CKE0

CKE1

WE

RCAS

RCKE0

RCKE1

RWE

CKE : SDRAMs D9 - D17

WE: SDRAMs D0 - D17

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

PCK

RESET

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

512MB, 64M x 72 ECC Module (M383(12)L6420EUS) (Populated as 1 bank of x4 DDR SDRAM Module)

Functional Block Diagram

VSS

RCS0

DQS0

DQS1

DQS9

(DM0)

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

DM

CS

D9

CS

D0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS10

(DM1)

DQS

CS

D1

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

D10

DQS11

(DM2)

DQS2

DQS3

DQS

CS

D2

I/O 3

I/O 2

I/O 1

I/O 0

DQ16

DQ17

DQ18

DQ19

I/O 3

I/O 2

I/O 1

I/O 0

DQ20

DQ21

DQ22

DQ23

D11

DQS12

(DM3)

DQS

CS

D3

DQ24

DQ25

DQ26

DQ27

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ28

DQ29

DQ30

DQ31

D12

DQS13

(DM4)

DQS4

DQS5

DQS

CS

D4

I/O 3

I/O 2

I/O 1

I/O 0

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 3

I/O 2

I/O 1

I/O 0

D13

DQS14

(DM5)

DQS

CS

D5

I/O 3

I/O 2

I/O 1

I/O 0

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

I/O 3

I/O 2

I/O 1

I/O 0

D14

DQS15

(DM6)

DQS6

DQS

CS

Serial PD

CS

D6

I/O 3

I/O 2

I/O 1

I/O 0

DQ48

DQ49

DQ50

DQ51

I/O 3

I/O 2

I/O 1

I/O 0

DQ52

DQ53

DQ54

DQ55

SCL

WP

D15

SDA

A0

A1

A2

DQS7

DQS8

DQS16

(DM7)

DQS

CS

D7

SA0 SA1 SA2

I/O 3

I/O 2

I/O 1

I/O 0

DQ56

DQ57

DQ58

DQ59

I/O 3

I/O 2

I/O 1

I/O 0

DQ60

DQ61

DQ62

DQ63

D16

V_DDSPD

SPD

DQS17

(DM8)

V_DD/V_DDQ

D0 - D17

DQS

CS

D8

I/O 3

I/O 2

I/O 1

I/O 0

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

I/O 3

I/O 2

I/O 1

I/O 0

D17

VREF

V_SS

D0 - D17

Strap: see Note 4

PLL*

CK0,CK0

* Wire per Clock Loading table/wiring Diagrams

CS0

RCS0_1

RCS0_2

RBA0 - RBA1

RA0 - RA12

RRAS

R

E

G

I

S

T

E

R

BA0 -BA1 : SDRAMs DQ0 - D17

A0 -A12 : SDRAMs D0 - D17

BA0-BA1

A0-A12

RAS

CAS

CKE0

Notes:

RAS : SDRAMs D0 - D17

CAS : SDRAMs DQ0 - D17

CKE : SDRAMs D0 - D8

CKE : SDRAMs D9 - D17

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must

be maintained as shown.

RCAS

RCKE0A

RCKE0B

RWE

WE

WE: SDRAMs D0 - D17

3. DQ, DQS, DM resistors: 22 Ohms.

PCK

RESET

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

1GB, 128M x 72 ECC Module [M383(12)L2828EU1(0)] (Populated as 2 bank of x4 DDR SDRAM Module)

Functional Block Diagram

V_SS

RCS1

RCS0

DQS0

DM0/DQS9

DM1/DQS10

DM2/DQS11

DM3/DQS12

DM4/DQS13

DM5/DQS14

DM6/DQS15

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS

D0

DM

DQS

I/O 3

I/O 2

I/O 1

I/O 0

CS

DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

CS

D8

DM

DQS

I/O 0

I/O 1

I/O 2

I/O 3

CS

DM

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

D16

D24

DQS1

DQS

CS

D1

CS

D9

CS

DQ8

DQ9

DQ10

DQ11

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ12

DQ13

DQ14

DQ15

D17

D25

DQS2

DQS

CS

D2

DQS

CS

DQS

CS

DQS

CS

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

D18

D10

D26

DQS3

DQS4

DQS5

DQS

CS

D3

CS

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ28

DQ29

DQ30

DQ31

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ24

DQ25

DQ26

DQ27

D19

D11

D27

DQS

CS

D4

DQS

CS

DQS

CS

DQS

CS

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ36

DQ37

DQ38

DQ39

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ32

DQ33

DQ34

DQ35

D20

D12

D28

DQS

CS

D5

CS

DQ40

DQ41

DQ42

DQ43

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ44

DQ45

DQ46

DQ47

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

D21

D13

D29

DQS6

DQS7

DQS

CS

D6

CS

DQ48

DQ49

DQ50

DQ51

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

DQ52

DQ53

DQ54

DQ55

D22

D14

D30

DM7/DQS16

DQS

CS

D7

CS

DQ56

DQ57

DQ58

DQ59

I/O 0

I/O 1

I/O 2

I/O 3

I/O 0

I/O 1

I/O 2

I/O 3

I/O 2

I/O 1

I/O 0

I/O 3

I/O 2

I/O 1

I/O 0

DQ60

DQ61

DQ62

DQ63

D23

D15

D31

Serial PD

V_DDSPD

SPD

SCL

WP

V_DD/V_DDQ

D0 - D35

SDA

A0

A1

A2

VREF

V_SS

D0 - D35

SA0 SA1 SA2

PLL

CK0,CK0

CS0

RCS0

RCS1

R

E

G

I

S

T

E

R

CS1

BA0-BA1

A0-A12

RAS

CAS

CKE0

CKE1

WE

* Wire per Clock Loading table/wiring Diagrams

RBA0 - RBA1

RA0 - RA12

BA0-BAn: SDRAMs D0 - D35

A0-An: SDRAMs D0 - D35

RAS: SDRAMs D0 - D35

CAS: SDRAMs D0 - D35

CKE: SDRAMs D0 - D17

CKE: SDRAMs D18 - D35

WE: SDRAMs D0 - D35

RRAS

RCAS

RCKE0

RCKE1

Notes:

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

RWE

PCK

RESET

Revision 1.1 Oct. 2004

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DDR SDRAM

Absolute Maximum Ratings

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD,VDDQ

TSTG

Value

-0.5 ~ 3.6

Unit

V

-1.0 ~ 3.6

V

-55 ~ +150

1.5 * # of component

50

°C

W

Power dissipation

PD

Short circuit current

IOS

mA

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Power & DC Operating Conditions (SSTL_2 In/Out)

Recommended operating conditions (Voltage referenced to VSS=0V, TA=0 to 70°C)

Parameter

Symbol

Min

Max

2.7

Unit

Note

Supply voltage(for device with a nominal VDD of 2.5V)

VDD

2.3

I/O Supply voltage

VDDQ

VREF

V_TT

2.3

2.7

V

I/O Reference voltage

I/O Termination voltage(system)

VDDQ/2-50mV VDDQ/2+50mV

1

2

4

VREF-0.04

VREF+0.04

V

Input logic high voltage

VIH(DC)

VIL(DC)

VIN(DC)

VID(DC)

II

VREF+0.15

VDDQ+0.3

VREF-0.15

VDDQ+0.3

VDDQ+0.6

2

V

Input logic low voltage

-0.3

0.3

-2

V

Input Voltage Level, CK and CK inputs

Input Differential Voltage, CK and CK inputs

Input leakage current

V

3

uA

Output leakage current

IOZ

-5

5

Output High Current(Normal strengh driver)

;V_OUT= V_TT+ 0.84V

IOH

IOL

IOH

IOL

-16.8

16.8

-9

mA

Output High Current(Normal strengh driver)

;V_OUT= V_TT- 0.84V

Output High Current(Half strengh driver)

;V_OUT= V_TT+ 0.45V

Output High Current(Half strengh driver)

;V_OUT= V_TT- 0.45V

9

Notes : 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on

VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise

coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of ≤ 3nH.

2. V_TTis not applied directly to the device. V_TTis a system supply for signal termination resistors, is expected to be set equal to

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHz

Revision 1.1 Oct. 2004

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DDR SDRAM

DDR SDRAM IDD spec table

M383(12)L3223EUS [ (32M x 8) * 9 , 256MB Module ]

(V_DD=2.7V, T = 10°C)

AA

A2

B0

A0

Symbol

Unit

Notes

(DDR266@CL=2)

(DDR266@CL=2.5)

(DDR200@CL=2)

IDD0

IDD1

1,560

1,790

360

1,350

1,570

360

1,350

1,570

360

1,180

1,360

330

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

810

670

490

450

600

530

1,030

1,890

1,840

2,070

360

1,030

1,890

1,840

2,070

360

1,030

1,890

1,840

2,070

360

860

1,580

1,490

1,810

330

IDD6

Normal

Low power

IDD7A

340

320

Optional

3,270

2,250

2,480

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M383(12)L6423EUS [ (32M x 8) * 18 , 512MB Module ]

(V_DD=2.7V, T = 10°C)

AA

A2

B0

A0

Symbol

Unit

Notes

(DDR266@CL=2)

(DDR266@CL=2.5)

(DDR200@CL=2)

IDD0

IDD1

2,180

2,410

510

1,880

2,100

510

1,880

2,100

510

1,660

1,840

480

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

1,110

780

1,110

780

1,110

780

950

720

990

880

1,560

2,420

2,370

2,600

510

1,560

2,420

2,370

2,600

510

1,560

2,420

2,370

2,600

510

1,350

2,070

1,980

2,290

480

IDD6

Normal

Low power

IDD7A

480

460

Optional

3,890

3,410

2,970

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

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DDR SDRAM

DDR SDRAM IDD spec table

M383(12)L6420EUS [ (64M x 4) * 18 , 512MB Module ]

(V_DD=2.7V, T = 10°C)

AA

A2

B0

A0

Symbol

Unit

Notes

(DDR266@CL=2)

(DDR266@CL=2.5)

(DDR200@CL=2)

IDD0

IDD1

2,370

2,730

380

2,070

2,430

380

2,070

2,430

380

1,850

2,120

360

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

990

830

650

590

870

750

1,440

2,790

3,060

3,510

379

1,440

2,790

3,060

3,510

379

1,440

2,790

3,060

3,510

379

1,220

2,300

2,480

3,110

360

IDD6

Normal

Low power

IDD7A

352

330

Optional

5,430

4,950

4,280

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

M383(12)L2828EU1(0) [ (st.128M x 4) * 18 , 1GB Module ]

(V_DD=2.7V, T = 10°C)

AA

A2

B0

A0

Symbol

Unit

Notes

(DDR266@CL=2)

(DDR266@CL=2.5)

(DDR200@CL=2)

IDD0

IDD1

3,490

3,850

558

3,000

3,360

558

3,000

3,360

558

2,700

2,970

540

mA

IDD2P

IDD2F

IDD2Q

IDD3P

IDD3N

IDD4R

IDD4W

IDD5

1,470

1,100

1,530

2,370

3,720

3,990

4,440

558

1,470

1,100

1,530

2,370

3,720

3,990

4,440

558

1,470

1,100

1,530

2,370

3,720

3,990

4,440

558

1,280

1,010

1,330

2,070

3,150

3,330

3,960

540

IDD6

Normal

Low power

IDD7A

504

480

Optional

6,550

5,880

5,130

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

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DDR SDRAM

AC Operating Conditions

Max

Parameter/Condition

Symbol

VIH(AC)

VIL(AC)

VID(AC)

VIX(AC)

Min

Unit

V

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input Low (Logic 0) Voltage, DQ, DQS and DM signals.

Input Differential Voltage, CK and CK inputs

VREF + 0.31

3

1

2

VREF - 0.31

VDDQ+0.6

V

0.7

V

Input Crossing Point Voltage, CK and CK inputs

0.5*VDDQ-0.2 0.5*VDDQ+0.2

V

Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of V_IXis expected to equal 0.5*V_DDQof the transmitting device and must track variations in the DC level of the same.

3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in

simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.

Vtt=0.5*VDDQ

RT=50Ω

Output

Z0=50Ω

VREF

=0.5*VDDQ

CLOAD=30pF

Output Load Circuit (SSTL_2)

Input/Output Capacitance

(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)

M383(12)L3223EUS, M383(12)L6420EUS

Parameter

Symbol

Unit

Min

9

Max

11

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )

Input capacitance(CKE0)

CIN1

CIN2

CIN3

CIN4

CIN5

Cout1

Cout2

pF

9

11

Input capacitance( CS0)

9

11

Input capacitance( CLK0, CLK0 )

11

10

12

11

Input capacitance(DM0~DM8)

Data & DQS input/output capacitance(DQ0~DQ63)

Data input/output capacitance (CB0~CB7)

11

M383(12)L6423EUS, M383(12)L2828EU1(0)

Parameter

Symbol

Unit

Min

9

Max

11

Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )

Input capacitance(CKE0,CKE1)

CIN1

CIN2

CIN3

CIN4

CIN5

Cout1

Cout2

pF

9

11

Input capacitance( CS0, CS1)

9

11

Input capacitance( CLK0, CLK0 )

11

14

12

16

Input capacitance(DM0~DM8)

Data & DQS input/output capacitance(DQ0~DQ63)

Data input/output capacitance (CB0~CB7)

Revision 1.1 Oct. 2004

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DDR SDRAM

AC Timming Parameters & Specifications

AA

A2

B0

A0

(DDR266@CL=2)

(DDR266@CL=2.5)

(DDR200@CL=2)

Parameter

Symbol

Unit Note

Min

60

Max

Min

65

Max

Min

65

Max

Min

70

80

48

20

15

1

Max

Row cycle time

tRC

tRFC

tRAS

tRCD

tRP

ns

Refresh row cycle time

Row active time

75

45

120K

45

120K

45

120K

ns

RAS to CAS delay

15

20

ns

Row precharge time

15

20

ns

Row active to Row active delay

Write recovery time

tRRD

tWR

15

ns

15

ns

Last data in to Read command

Col. address to Col. address delay

tWTR

tCCD

1

tCK

ns

1

CL=2.0

CL=2.5

7.5

0.45

-0.75

-

12

7.5

0.45

-0.75

-

12

10

12

10

12

Clock cycle time

tCK

7.5

0.45

-0.75

-

ns

Clock high level width

Clock low level width

tCH

tCL

0.55

+0.75

0.5

0.55

+0.75

0.5

0.55

+0.75

0.5

0.45

-0.8

-

0.55

+0.8

0.6

tCK

ns

DQS-out access time from CK/CK

Output data access time from CK/CK

Data strobe edge to ouput data edge

Read Preamble

tDQSCK

tAC

ns

tDQSQ

tRPRE

tRPST

tDQSS

tWPRES

tWPRE

tDSS

ns

12

3

0.9

0.4

0.75

0

1.1

0.9

0.4

0.75

0

1.1

0.9

0.4

0.75

0

1.1

0.9

0.4

0.75

0

1.1

tCK

ns

Read Postamble

0.6

CK to valid DQS-in

1.25

DQS-in setup time

DQS-in hold time

0.25

0.2

0.25

0.2

0.25

0.2

0.25

0.2

tCK

DQS falling edge to CK rising-setup time

DQS falling edge from CK rising-hold

tDSH

0.2

tCK

DQS-in high level width

DQS-in low level width

DQS-in cycle time

tDQSH

tDQSL

tDSC

tIS

0.35

0.9

0.35

0.9

0.35

0.9

0.35

0.9

tCK

1.1

Address and Control Input setup

0.9

1.0

0.9

1.0

0.9

1.0

1.1

ns

i,5.7~9

i, 6~9

Address and Control Input hold

Address and Control Input setup

Address and Control Input hold

tIH

tIS

tIH

i, 6~9

Data-out high impedence time from CK/

CK

tHZ

tLZ

-0.75

+0.75

-0.75

+0.75

-0.75

+0.75

-0.8

+0.8

ns

1

Data-out low impedence time from CK/

CK

Input Slew Rate(for input only pins)

Input Slew Rate(for I/O pins)

tSL(I)

tSL(IO)

tSL(O)

tSLMR

0.5

1.0

0.5

1.0

0.5

1.0

0.5

1.0

V/ns

Output Slew Rate(x4,x8)

4.5

1.5

4.5

1.5

4.5

1.5

4.5

1.5

Output Slew Rate Matching Ratio(rise to

0.67

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

AA

A2

B0

A0

(DDR200@CL=2)

(DDR266@CL=2)

(DDR266@CL=2.5)

Parameter

Symbol

Unit Note

Min

15

Max

Min

15

Max

Min

15

Max

Min

16

Max

Mode register set cycle time

DQ & DM setup time to DQS

DQ & DM hold time to DQS

tMRD

tDS

ns

0.5

0.6

ns

j, k

tDH

0.5

0.6

Control & Address input pulse width

DQ & DM input pulse width

Power down exit time

tIPW

tDIPW

tPDEX

tXSNR

tXSRD

tREFI

2.2

1.75

7.5

2.2

1.75

7.5

2.2

1.75

7.5

2.5

2

ns

8

10

80

200

ns

Exit self refresh to non-Read command

Exit self refresh to read command

Refresh interval time

75

ns

200

tCK

us

7.8

-

7.8

-

7.8

-

7.8

4

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

tHP

-tQHS

Output DQS valid window

Clock half period

tQH

tHP

-

ns

11

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

tCLmin

or tCHmin

-

10, 11

Data hold skew factor

tQHS

0.75

0.6

0.75

0.6

0.75

0.6

0.8

0.6

ns

11

2

DQS write postamble time

tWPST

0.4

20

0.4

20

0.4

20

0.4

20

tCK

Active to Read with Auto precharge

command

tRAP

Autoprecharge write recovery +

Precharge time

(tWR/tCK)

+

(tWR/tCK)

+

(tWR/tCK)

+

(tWR/tCK)

+

tDAL

tCK

13

(tRP/tCK)

System Characteristics for DDR SDRAM

The following specification parameters are required in systems using DDR266 & DDR200 devices to ensure proper sys-

tem performance. these characteristics are for system simulation purposes and are guaranteed by design.

Table 1 : Input Slew Rate for DQ, DQS, and DM

AC CHARACTERISTICS

DDR266

DDR200

PARAMETER

SYMBOL

DCSLEW

MIN

TBD

MAX

TBD

MIN

0.5

MAX

4.0

Units

V/ns

Notes

a, m

DQ/DM/DQS input slew rate measured between

VIH(DC), VIL(DC) and VIL(DC), VIH(DC)

Table 2 : Input Setup & Hold Time Derating for Slew Rate

Input Slew Rate

0.5 V/ns

tIS

0

tIH

0

Units

ps

Notes

i

0.4 V/ns

+50

+100

0

ps

0.3 V/ns

0

ps

Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate

Input Slew Rate

0.5 V/ns

tDS

0

tDH

0

Units

ps

Notes

k

0.4 V/ns

+75

+150

+75

+150

ps

0.3 V/ns

ps

Revision 1.1 Oct. 2004

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DDR SDRAM

Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Delta Slew Rate

+/- 0.0 V/ns

tDS

0

tDH

0

Units

ps

Notes

j

+/- 0.25 V/ns

+/- 0.5 V/ns

+50

+100

+50

+100

ps

Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)

Typical Range

(V/ns)

Minimum

(V/ns)

Maximum

(V/ns)

Slew Rate Characteristic

Notes

Pullup Slew Rate

Pulldown slew

1.2 ~ 2.5

1.0

4.5

a,c,d,f,g,h

b,c,d,f,g,h

Table 6 : Output Slew Rate Characteristice (X16 Devices only)

Typical Range

(V/ns)

Minimum

(V/ns)

Maximum

(V/ns)

Slew Rate Characteristic

Notes

Pullup Slew Rate

Pulldown slew

1.2 ~ 2.5

0.7

5.0

a,c,d,f,g,h

b,c,d,f,g,h

Table 7 : Output Slew Rate Matching Ratio Characteristics

AC CHARACTERISTICS DDR266

DDR200

PARAMETER

Output Slew Rate Matching Ratio (Pullup to Pulldown)

MIN

TBD

MAX

TBD

MIN

0.67

MAX

1.5

Notes

e,m

Revision 1.1 Oct. 2004

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DDR SDRAM

System Notes :

a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.

Test point

Output

50Ω

VSSQ

Figure 1 : Pullup slew rate test load

b. Pulldown slew rate is measured under the test conditions shown in Figure 2.

VDDQ

50Ω

Output

Test point

Figure 2 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output

switching.

Example : For typical slew rate, DQ0 is switching

For minmum slew rate, all DQ bits are switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions

Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process

Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process

Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and

voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package divices only.

h. Only intended for operation up to 266 Mbps per pin.

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5 V/ns

as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or

VIH(DC) to VIL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.

Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the

slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this

would result in the need for an increase in tDS and tDH of 100 ps.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser

on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter

mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.

m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotony.

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

Command Truth Table

A0 ~ A9

A11, A12

OP CODE

COMMAND

CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP

Note

Register

Extended MRS

H

X

H

L

1, 2

3

Mode Register Set

Auto Refresh

OP CODE

H

L

H

X

Entry

3

Refresh

Self

Refresh

L

H

L

H

X

L

H

X

H

X

H

3

Exit

L

H

X

3

Bank Active & Row Addr.

H

V

Row Address

(A0~A9, A11,A12)

Read &

Column Address

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

L

4

Column

Address

H

X

L

H

L

H

V

H

Write &

Column Address

L

4

Column

Address

H

X

L

H

L

H

L

H

4, 6

7

Burst Stop

Precharge

X

Bank Selection

All Banks

V

X

L

X

H

5

H

L

X

V

X

H

X

V

X

H

X

V

X

H

X

V

X

V

X

H

X

V

Entry

Exit

H

L

H

L

Active Power Down

X

H

L

Entry

H

Precharge Power Down Mode

X

H

L

Exit

L

H

DM

X

8

9

H

L

X

H

X

H

No operation (NOP) : Not defined

X

Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

Physical Dimensions : 32M x 72 (M383L3223EUS)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

0.118

(3.00)

5.171

(131.350)

5.077

(128.950)

0.0787

R (2.00)

0.78

(19.80)

REG

PLL

REG

A

B

2.500

M

0.10

C

B

A

0.157 Max

(3.99 Max)

0.050 ± 0.0039

(1.270 ± 0.10)

0.118

(3.00)

0.250

(6.350)

0.157

(4.00)

0.039 ± 0.002

(1.000 ± 0.050)

0.26

(6.62)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ±0.006

(0.20 ±0.15)

2.175

0.071

(1.80)

0.050

(1.270)

0.1575

(4.00)

0.10 M

C A M B

Detail A

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 32Mx8 DDR SDRAM, TSOPII.

DDR SDRAM Part No : K4H560838E

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

Physical Dimensions: 64Mx72 (M383L6423EUS), (M383L6420EUS)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

5.171

(131.350)

0.118

(3.00)

5.077

(128.950)

0.0787

R (2.00)

0.78

(19.80)

REG

PLL

REG

A

B

2.500

M

C

B

A

0.10

A

0.157 Max

(3.99 Max)

0.050 ± 0.0039

(1.270 ± 0.10)

0.118

(3.00)

0.250

(6.350)

0.157

(4.00)

0.039 ± 0.002

(1.000 ± 0.050)

0.26

(6.62)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ±0.006

(0.20 ±0.15)

2.175

0.071

(1.80)

0.050

(1.270)

0.1575

(4.00)

B

M

C A

0.10 M

Detail A

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 32Mx8, 64Mx4, DDR SDRAM, TSOPII.

DDR SDRAM Part No : K4H560838E, K4H560438E

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

Physical Dimensions: 128Mx72 (M383L2828EU1)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

0.118

(3.00)

5.171

(131.350)

5.077

(128.950)

0.0787

R (2.00)

0.78

(19.80)

REG

PLL

REG

A

B

2.500

0.10

M

C

B

A

0.268 Max

(6.81 Max)

0.050 ± 0.0039

(1.270 ± 0.10)

0.118

(3.00)

0.250

(6.350)

0.157

(4.00)

0.039 ± 0.002

(1.000 ± 0.050)

0.26

(6.62)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

0.071

(1.80)

0.050

(1.270)

0.1575

(4.00)

M

0.10

C A M B

Detail A

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is st.128Mx4 SDRAM, 66TSOPII

SDRAM Part No. : K4H510638E

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

Physical Dimensions : 32M x 72 (M312L3323EUS)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

0.118

(3.00)

5.171

(131.350)

5.077

(128.950)

REG

0.0787

R (2.00)

PLL

0.78

(19.80)

A

B

2.500

M

0.10

C B A

0.157 Max

(3.99 Max)

REG

0.050 ± 0.0039

(1.270 ± 0.10)

0.118

(3.00)

0.250

(6.350)

0.157

(4.00)

0.039 ± 0.002

(1.000 ± 0.050)

0.26

(6.62)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

0.071

(1.80)

0.050

(1.270)

0.1575

(4.00)

0.10

Detail A

M

C

A

B

M

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is 32Mx8 DDR SDRAM, TSOPII

SDRAM Part No : K4H560838E

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

Physical Dimensions: 64Mx72 (M312L6423EUS), (M312L6420EUS)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

0.118

(3.00)

5.171

(131.350)

5.077

(128.950)

REG

0.0787

R (2.00)

PLL

0.78

(19.80)

A

B

2.500

M

0.10

C B A

0.157 Max

(3.99 Max)

REG

0.050 ± 0.0039

(1.270 ± 0.10)

0.118

(3.00)

0.250

(6.350)

0.157

(4.00)

0.039 ± 0.002

(1.000 ± 0.050)

0.26

(6.62)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

0.071

(1.80)

0.050

(1.270)

0.1575

(4.00)

Detail A

M

0.10

C

A B

M

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is 32Mx8, 64Mx4 DDRSDRAM, TSOPII

SDRAM Part No. : K4H560838E, K4H560438E

Revision 1.1 Oct. 2004

256MB, 512MB, 1GB Registered DIMM Pb-Free

DDR SDRAM

Physical Dimensions: 128Mx72 (M312L2828EU0)

Units : Inches (Millimeters)

5.25 ± 0.005

(133.350 ± 0.13)

0.118

(3.00)

5.171

(131.350)

5.077

(128.950)

0.0787

Reg.

R (2.00)

0.78

(19.80)

A

B

2.500

M

0.10

C B A

0.268 Max

(6.81 Max)

PLL

0.050 ± 0.0039

(1.270 ± 0.10)

0.118

(3.00)

0.250

(6.350)

0.157

(4.00)

0.039 ± 0.002

(1.000 ± 0.050)

0.26

(6.62)

0.0787

R (2.00)

0.1496

(3.80)

0.0078 ± 0.006

(0.20 ± 0.15)

2.175

0.071

(1.80)

0.050

(1.270)

0.1575

(4.00)

0.10

Detail A

M

C

A

B

M

Detail B

Tolerances : ± 0.005(.13) unless otherwise specified

The used device is st.128Mx4 SDRAM, 66TSOPII

SDRAM Part NO : K4H510638E

Revision 1.1 Oct. 2004


型号：	M383L3223EUS-CA0
厂家：	SAMSUNG
描述：	DDR DRAM Module, 32MX72, 0.8ns, CMOS, DIMM-184 动态存储器双倍数据速率
文件：	总23页 (文件大小：491K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M383L3223EUS-CA0 [SAMSUNG]

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