M383L3313CT1-LB0 [SAMSUNG]
DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184;
| 型号： | M383L3313CT1-LB0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 32MX72, 0.75ns, CMOS, DIMM-184 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总13页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
184pin Registered DDR SDRAM MODULE
M383L3313CT1
256MB DDR SDRAM MODULE
(32Mx72(16Mx72*2 bank) based on 16Mx8 DDR SDRAM)
Registered 184pin DIMM
72-bit ECC/Parity
Revision 0.3
May. 2002
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
Revision History
Revision 0.0 (Mar. 2001)
1. First release
Revision 0.1 (June. 2001)
1. Changed module current speificaton
2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).
3. Changed AC parameter table.
Revision 0.2 (Jan. 2002)
- Add derating values for the specifications if the single-ended clock skew rate is less than 1.0V/ns in page 47.
- Revised "Absolute maximum rating" table in page 38.
. Changed "Voltage on VDDQ supply relative to VSS" value from -0.5~3.6V to -1~3.6V
. Changed "power dissipation" value from 1.0W to 1.5W.
- Revised AC parameter table
From
To
DDR266A
DDR266B
DDR200
DDR266A
DDR266B
DDR200
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
+0.8
tACmin
-400ps
tACmax
-400ps
tACmin
-400ps
tACmax
-400ps
tACmin
-400ps
tACmax
-400ps
tHZ
tLZ
-0.75
-0.75
+0.75
-0.75
-0.75
+0.75
-0.8
-0.8
tACmin
-400ps
tACmax
-400ps
tACmin
-400ps
tACmax
-400ps
tACmin
-400ps
tACmax
-400ps
+0.75
0.6
+0.75
0.6
+0.8
0.6
tWPST
(tCK)
0.25
0.25
10ns
0.25
0.4
0.4
0.4
tPDEX
10ns
10ns
7.5ns
7.5ns
10ns
- Deleted typical current in IDD spec. table
- Included address and control input setup/hold time(tIS/tIH) at slow slew rate in DDR200/266 AC specification
- Deleted Exit self refresh to write command(tXSW) in DDR200/266 AC specification
- Rename tXSA(exit self refresh to bank active command) to tXSNR(exit self refresh to non read command) at DDR200/266
- Rename tXSR(exit self refresh to read command) to tXSRD at DDR200/266
- Rename tWPREH(DQS in hold time) to tWPRE at DDR200/266
- Rename tREF(Refresh interval time) to tREFI at DDR200/266
- Changed tWR value from 2tCK to 15ns.
--Rename tCDLR(Write data out to Read command) t0 tWTR
- Added tDAL(tWR+tRP)
Revision 0.3 (May. 2002)
1. Change pin location of A13 from pin 103 to pin 167
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
M383L3313CT1 DDR SDRAM 184pin DIMM
32Mx72 DDR SDRAM 184pin DIMM based on 16Mx8
GENERAL DESCRIPTION
FEATURE
• Performance range
The Samsung M383L3313CT1 is 32M bit x 72 Double Data
Rate SDRAM high density memory modules. The Samsung
M383L3313CT1 consists of eighteen CMOS 16M x 8 bit with
4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil)
packages, mounted on a 184pin glass-epoxy substrate. Four
0.1uF decoupling capacitors are mounted on the printed circuit
board in parallel for each DDR SDRAM. The M383L3313CT1
is Dual In-line Memory Modules and intended for mounting into
184pin edge connector sockets.
Part No.
Max Freq.
Interface
M383L3313CT1-C(L)A2 133MHz(7.5ns@CL=2)
M383L3313CT1-C(L)B0 133MHz(7.5ns@CL=2.5)
M383L3313CT1-C(L)A0 100MHz(10ns@CL=2)
SSTL_2
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
• Serial presence detect with EEPROM
•
PCB : Height 1700 mil, double sided component
3313CT1 PIN CONFIGURATIONS (Front side/back side)
PIN DESCRIPTION
Pin Front
Pin
Front Pin
Front
Pin
Back
Pin
Back
Pin
Back
Pin Name
Function
1
2
VREF
DQ0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
A5
DQ24
VSS
DQ25
DQS3
A4
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDDQ
/WE
93
VSS
DQ4
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
VSS
A6
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
/RAS
DQ45
VDDQ
/CS0
/CS1
DM5
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
CB0 ~ CB7
DQS0 ~ DQS8
CK0,CK0
CKE0,CKE1
CS0, CS1
RAS
Address input (Multiplexed)
Bank Select Address
Data input/output
94
3
VSS
DQ41
/CAS
VSS
95
DQ5
DQ28
DQ29
VDDQ
DM3
A3
DQ1
4
96
VDDQ
DM0
DQ6
Check bit(Data-in/data-out)
Data Strobe input/output
Clock input
DQS0
DQ2
5
97
6
DQS5
DQ42
DQ43
VDD
98
VDD
DQ3
7
VDD
DQ26
DQ27
A2
99
DQ7
VSS
8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
VSS
DQ30
VSS
DQ46
DQ47
*/CS3
VDDQ
DQ52
DQ53
*A13
Clock enable input
Chip select input
NC
9
NC
/RESET
VSS
*/CS2
DQ48
DQ49
VSS
10
11
12
13
14
15
16
NC
DQ31
CB4
Row address strobe
Column address strobe
Write enable
VSS
A1
NC
DQ8
CAS
VDDQ
DQ12
DQ13
DM1
VDD
DQ14
DQ15
CKE1
VDDQ
*BA2
DQ20
*A12
VSS
CB5
DQ9
CB0
CB1
VDD
DQS8
A0
VDDQ
CK0
W E
DQS1
VDDQ
*CK1
*/CK2
*CK2
VDDQ
DQS6
DQ50
DQ51
VSS
DM0 ~ DM8
VDD
Data - in mask
/CK0
VSS
VDD
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
DM6
VDDQ
17 */CK1
DM8
A10
DQ54
DQ55
VDDQ
NC
18
19
20
21
CB2
VSS
CB3
BA1
VSS
DQ10
DQ11
CKE0
VSS
CB6
VREF
Power supply for reference
VDDQ
CB7
VDDSPD
Serial EEPROM Power
DQ60
DQ61
VSS
VDDID
DQ56
DQ57
VDD
Supply ( 2.3V to 3.6V )Supply
22 VDDQ
KEY
KEY
SDA
Serial data I/O
23
24
25
26
27
28
29
30
31
53
54
55
56
57
58
59
60
61
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
145
146
147
148
149
150
151
152
153
VSS
DQ36
DQ37
VDD
DQ16
DQ17
DQS2
VSS
DM7
SCL
Serial clock
DQ21
A11
DQ62
DQ63
VDDQ
SA0
DQS7
DQ58
DQ59
VSS
SA0 ~ 2
VDDID
RESET
NC
Address in EEPROM
VDD identification flag
Reset enable
A9
DM2
VDD
DQ22
A8
DM4
DQ38
DQ39
VSS
DQ18
A7
No connection
BA0
NC
SA1
DQ35
DQ40
SA2
* These pins are not used in this module.
VDDQ
DQ19
SDA
DQ23
DQ44
VDDSPD
SCL
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
Functional Block Diagram
RS1
RS0
DQS0
DM0/DQS9
DQS4
DM4/DQS13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
DQS
CS
D4
CS
DM
I/O 7
DQS
CS
D0
DM
CS DQS
D9
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
D13
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS5
DM5/DQS14
DQS1
DM1/DQS10
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DM
CS
D5
CS DQS
D14
CS DQS
D1
DM
DQS
CS
DQ40
DQ41
DQ42
DQ43
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ8
DQ9
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
D10
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ44
DQ45
DQ46
DQ47
DQS6
DM6/DQS15
DQS2
DM2/DQS11
DM
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D6
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D2
CS
DQ48
DQ16
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ17
DQ18
DQ19
D11
DQ20
DQ21
DQ22
DQ23
DQS7
DM7/DQS16
DQS3
DM3/DQS12
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D7
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS DQS
D16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D3
DM
CS DQS
D12
DQ56
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
DQ24
DQ57
DQ58
DQ59
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ60
DQ61
DQ62
DQ63
DQS8
DM8
Serial PD
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS DQS
D8
DM
CS DQS
D17
CB0
CB1
CB2
CB3
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
SCL
WP
SDA
A0
A1
A2
CB4
CB5
CB6
CB7
SA0 SA1
SA2
VDDSPD
SPD
VDD/VDDQ
D0 - D17
D0 - D17
VREF
VSS
D0 - D17
D0 - D17
PLL*
CK0,CK0
* Wire per Clock Loading table/wiring Diagrams
RCS0
CS0
R
E
G
I
S
T
E
R
Notes:
RCS1
RBA0 - RBAn
BA0 -BAn : SDRAMs DQ0 - D17
A0 -An : SDRAMs D0 - D17
RAS : SDRAMs D0 - D17
CAS : SDRAMs DQ0 - D17
CKE : SDRAMs D0 - D8
CKE : SDRAMs D9 - D17
WE: SDRAMs D0 - D17
CS1
BA0-BAN
A0-A13
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
RA0 - RA11
RRAS
RAS
CAS
CKE0
CKE1
WE
RCAS
RCKE0
RCKE1
RWE
3. DQ, DQS, DM resistors: 22 Ohms.
PCK
PCK
RESET
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
Absolute Maximum Rate
Parameter
Symbol
Value
Unit
Voltage on any pin relative to V
V
, V
-0.5 ~ 3.6
V
SS
IN
OUT
DDQ
Voltage on V
& V
supply relative to V
V
, V
-1.0 ~ 3.6
-55 ~ +150
27
V
°C
W
DD
DDQ
SS
DD
Storage temperature
Power dissipation
Short circuit current
T
STG
P
D
I
50
mA
OS
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V)
I/O Supply voltage
Symbol
VDD
Min
2.3
Max
2.7
Unit
Note
VDDQ
2.3
2.7
V
V
I/O Reference voltage
VREF
VDDQ/2-50mV VDDQ/2+50mV
1
2
4
4
I/O Termination voltage(system)
Input logic high voltage
V
VREF-0.04
VREF+0.04
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.35
V
TT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
II
VREF+0.15
V
Input logic low voltage
-0.3
-0.3
0.3
1.15
-2
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
V
V
3
5
V
2
uA
uA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver)
IOH
IOL
IOH
-16.8
16.8
-9
mA
mA
mA
;V
= V + 0.84V
TT
OUT
Output High Current(Normal strengh driver)
;V = V - 0.84V
OUT
TT
Output High Current(Half strengh driver)
;V = V + 0.45V
OUT
TT
Output High Current(Half strengh driver)
;V = V - 0.45V
IOL
9
mA
OUT
TT
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.
2.V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to
TT
TT
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
DDR SDRAM IDD spec table
(Vdd = 2.7V, T= 10’ C)
Symbol
IDD0
A2( DDR266@CL=2 )
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
2430
2700
1140
1470
1340
1730
2030
3010
2990
3430
1140
1120
4680
2430
2700
1140
1470
1340
1730
2030
3010
2990
3430
1140
1120
4680
2320
2610
1140
1400
1310
1700
1940
2760
2670
3250
1140
1120
4050
2536
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
Normal
Low power
IDD7A
IDD6
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
For the I
spec of a DDR SDRAM Module with 2 rows, SAMSUNG defines the test
DD
condition of each row as below:
Test (condition)
1 row (Active)
IDD0
2 row (Stand by)
IDD3N
IDD3N
IDD2P
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD2F
IDD2Q
IDD3P
IDD3N
IDD3N
IDD3N
IDD3N
IDD6
IDD6
IDD7
IDD3N
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
AC Operating Conditions
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC)
VIL(AC)
VID(AC)
VREF + 0.31
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
0.7
Input Crossing Point Voltage, CK and CK inputs
VIX(AC) 0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
Input Levels(VIH/VIL)
1.5
VREF+0.31/VREF-0.31
VREF
V
V
V
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Vtt
See Load Circuit
Vtt=0.5*VDDQ
RT=50W
Output
Z0=50W
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS, WE )
CIN1
-
12
pF
pF
pF
pF
pF
pF
pF
Input capacitance(CKE0,CKE1)
CIN2
CIN3
-
-
-
-
-
-
12
11
12
16
16
16
Input capacitance(CS0, CS1)
Input capacitance(CLK0, CLK0)
CIN4
Input capacitance(DM0~DM8)
CIN5
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance(CB0~CB7)
COUT1
COUT2
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)
-TCA2
(DDR266A)
-TCB0
(DDR266B)
-TCA0
(DDR200)
Parameter
Symbol
Unit Note
Min
Max
Min
Max
Min
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
65
75
65
75
70
80
48
20
20
15
15
1
ns
ns
Refresh row cycle time
Row active time
45
120K
45
120K
120K
ns
RAS to CAS delay
20
20
ns
Row precharge time
20
20
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
15
15
ns
15
15
ns
Last data in to Read command
Col. address to Col. address delay
tWTR
tCCD
1
1
tCK
tCK
1
1
1
CL=2.0
CL=2.5
7.5
7.5
0.45
0.45
-0.75
-0.75
-
12
12
10
12
12
10
12
ns
ns
5
5
Clock cycle time
tCK
7.5
0.45
0.45
-0.75
-0.75
-
Clock high level width
tCH
tCL
0.55
0.55
+0.75
+0.75
0.5
0.55
0.55
+0.75
+0.75
0.5
0.45
0.45
-0.8
-0.8
-
0.55
0.55
+0.8
+0.8
0.6
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
tDQSCK
tAC
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
ns
5
2
0.9
0.4
0.75
0
1.1
0.9
0.4
0.75
0
1.1
0.9
1.1
tCK
tCK
tCK
ns
Read Postamble
0.6
0.6
0.4
0.6
CK to valid DQS-in
1.25
1.25
0.75
0
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
-0.75
-0.75
0.5
0.5
1.0
0.67
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
-0.75
-0.75
0.5
0.5
1.0
0.67
0.25
0.2
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
0.2
0.35
0.35
0.9
DQS-in low level width
DQS-in cycle time
1.1
1.1
1.1
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
1.1
6
6
6
6
tIH
1.1
ns
tIS
1.1
ns
tIH
1.1
ns
tHZ
+0.75
+0.75
+0.75
+0.75
-0.8
-0.8
0.5
+0.8
+0.8
ns
tLZ
ns
tSL(I)
tSL(IO)
tSL(O)
tSLMR
V/ns
V/ns
V/ns
6
7
0.5
Output Slew Rate(x4,x8)
4.5
1.5
4.5
1.5
1.0
4.5
1.5
10
Output Slew Rate Matching Ratio(rise to fall)
0.67
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
-TCA2
(DDR266A)
-TCB0
(DDR266B)
-TCA0
(DDR200)
Parameter
Symbol
Unit
Note
Min
Max
Min
Max
Min
Max
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tMRD
tDS
15
15
16
ns
ns
ns
0.5
0.5
0.6
7,8,9
7,8,9
tDH
0.5
0.5
0.6
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
tIPW
2.2
1.75
7.5
2.2
1.75
7.5
2.5
2
ns
ns
tDIPW
tPDEX
10
ns
Exit self refresh to non-Read command tXSNR
75
75
80
ns
4
Exit self refresh to read command
Refresh interval time
tXSRD
tREFI
200
15.6
200
15.6
200
15.6
tCK
us
1
5
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
-
-
-
ns
ns
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
Data hold skew factor
tQHS
0.75
0.6
0.75
0.6
0.8
0.6
ns
DQS write postamble time
tWPST
0.4
20
0.4
20
0.4
20
tCK
3
Active to Read with Auto precharge
command
tRAP
tDAL
Autoprecharge write recovery +
Precharge time
(tWR/tCK)
+
(tWR/tCK)
+
(tWR/tCK)
+
tCK
11
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
1. Maximum burst refresh cycle : 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DIMMs, tCL and tCH are ³ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half period
jitter due to crosstalk (tJIT(crosstalk) ) on the DIMM.
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
DtIS
(ps)
0
DtIH
(ps)
0
(V/ns)
0.5
0.4
+50
+100
+50
+100
0.3
This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
IS IH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
DtDS
(ps)
0
DtDH
(V/ns)
0.5
(ps)
0
0.4
+75
+150
+75
0.3
+150
This derating table is used to increase t /t
in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
DS DH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
8. I/O Setup/Hold Plateau Derating
I/O Input Level
(mV)
DtDS
(ps)
DtDH
(ps)
± 280
+50
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
DtDS
(ps)
0
DtDH
(ps)
0
(ns/V)
0
±0.25
±0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
<Reference>
The following table specifies derating values for the specifications listed if the single-ended clock skew rate is less than 1.0V/ns.
CK slew rate
DtIH/tIS
DtDSS/tDSH
DtAC/tDQSCK
DtLZ(min)
DtHZ(max)
(Single ended)
(ps)
(ps)
(ps)
(ps)
(ps)
1.0V/ns
0.75V/ns
0.5V/ns
0
0
0
0
0
+50
+100
+50
+100
+50
+100
-50
-100
+50
+100
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
Command Truth Table
A11
A9 ~ A0
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
COMMAND
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
Refresh
Exit
L
H
X
X
3
Bank Active & Row Addr.
H
H
V
V
Row Address
Column
Address
(A0~A9)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
L
H
L
H
Column
Address
(A0~A9)
Write &
Column Address
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
X
DM
H
H
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
5.25 ± 0.005
(133.350 ± 0.13)
0.118
(3.00)
5.171
(131.350)
5.077
(128.950)
0.0787
R (2.00)
0.78
(19.80)
REG
PLL
REG
A
B
2.500
0.10 M
C
B
A
A
B
0.157 Max
(3.99 Max)
0.050± 0.0039
(1.270 ± 0.10)
0.118
(3.00)
0.250
(6.350)
0.157
(4.00)
0.039 ± 0.002
0.26
(6.62)
(1.000 ± 0.050)
0.0787
R (2.00)
0.1496
(3.80)
0.0078 ±0.006
(0.20 ±0.15)
2.175
0.071
(1.80)
0.050
(1.270)
0.1575
(4.00)
0.10 M
Detail A
C
A M B
Detail B
Tolerances : ± 0.005(.13) unless otherwise specified
The used device is 16Mx8 SDRAM, TSOP
SDRAM Part NO : K4H280838C
Rev. 0.3 May. 2002
184pin Registered DDR SDRAM MODULE
M383L3313CT1
184 Pin DDR Registered DIMM Clock Topolgy
0ns (nominal)
SDRAM
stack
PLL
R=120W
OUT1
CK0
120W
Probe point
CK0
Reg1 SDRAM
stack
Clock Reference Net
R=240
W
L6
L7
Reg2
R=240
120W
OUT ‘ N’
feedback
0.266
128
1.0
W
1.5pF
W
Note : Lenghts in inches
Z0=60
tD=2.2ns/ft
W
Note *
Notes* :
1. The Clock delay from the input of the PLL clock to the input of any SDRAM or register will be set to 0ns(nominal).
2. Input,output, and feedback clock lines are terminated from line to leine as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any addtional PLL outputs will be wired in a similar maner.
4. termination resistors for the PLL feedback path clocks are loacted after the pins of the PLL.
Rev. 0.3 May. 2002
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