M391B5673DZ1-CF8 [SAMSUNG]
DDR DRAM Module, 256MX72, 0.3ns, CMOS, ROHS COMPLIANT, DIMM-240;
| 型号： | M391B5673DZ1-CF8 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 256MX72, 0.3ns, CMOS, ROHS COMPLIANT, DIMM-240 动态存储器 双倍数据速率 |
| 文件： | 总50页 (文件大小：986K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DDR3 SDRAM
Unbuffered DIMM
DDR3 SDRAM Specification
240pin Unbuffered DIMM based on 1Gb D-die
64/72-bit Non-ECC/ECC
82/100FBGA with Lead-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Table Contents
1.0 DDR3 Registered DIMM Ordering Information ...........................................................................5
2.0 Key Features .................................................................................................................................5
3.0 Address Configuration .................................................................................................................5
4.0 x64 DIMM Pin Configurations (Front side/Back Side) ...............................................................6
5.0 x72 DIMM Pin Configurations (Front side/Back side) ...............................................................7
6.0 Pin Description .............................................................................................................................8
7.0 SPD and Thermal Sensor for ECC UDIMMs ...............................................................................8
8.0 Input/Output Functional Description ..........................................................................................9
8.1 Address Mirroring Feature ...........................................................................................................10
8.1.1 DRAM Pin Wiring Mirroring ...................................................................................................10
9.0 Function Block Diagram: ...........................................................................................................11
9.1 512MB, 64Mx64 Module (Populated as 1 rank of x16 DDR3 SDRAMs) ................................................11
9.2 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ...................................................12
9.3 1GB, 128Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ............................................13
9.4 2GB, 256Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs) .................................................14
9.5 2GB, 256Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs) ..........................................15
10.0 Absolute Maximum Ratings .....................................................................................................16
10.1 Absolute Maximum DC Ratings ..................................................................................................16
10.2 DRAM Component Operating Temperature Range ........................................................................16
11.0 AC & DC Operating Conditions ...............................................................................................16
11.1 Recommended DC Operating Conditions (SSTL - 15) ....................................................................16
12.0 AC & DC Input Measurement Levels .......................................................................................17
12.1 AC & DC Logic Input Levels for Single-ended Signals ...................................................................17
12.2 V
Tolerances .......................................................................................................................18
REF
12.3 AC & DC Logic Input Levels for Differential Signals ......................................................................19
12.3.1 Differential Signals Definition ..............................................................................................19
12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ............................19
12.3.3 Single-ended Requirements for Differential Signals ...............................................................20
12.3.4 Differential Input Cross Point Voltage ...................................................................................21
12.4 Slew Rate Definition for Single-ended Input Signals ......................................................................21
12.5 Slew Rate Definition for Differential Input Signals .........................................................................21
13.0 AC & DC Output Measurement Levels ....................................................................................22
13.1 Single-ended AC & DC Output Levels ..........................................................................................22
13.2 Differential AC & DC Output Levels .............................................................................................22
13.3 Single-ended Output Slew Rate ..................................................................................................22
13.4 DIfferential Output Slew Rate ....................................................................................................23
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DDR3 SDRAM
Unbuffered DIMM
14.0 IDD Specification Definition .....................................................................................................24
14.1 IDD SPEC Table ........................................................................................................................26
15.0 Input/Output Capacitance ........................................................................................................29
15.1 Non ECC UDIMM ......................................................................................................................29
15.2 ECC UDIMM .............................................................................................................................29
16.0 Electrical Characteristics and AC timing ...............................................................................30
16.1 Refresh Parameters by Device Density ........................................................................................30
16.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .............................................30
16.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ..............................................30
16.3.1 Speed Bin Table Notes .......................................................................................................31
17.0 Timing Parameters by Speed Grade .......................................................................................32
17.1 Jitter Notes ..............................................................................................................................35
17.2 Timing Parameter Notes ............................................................................................................36
17.3 Address / Command Setup, Hold and Derating .............................................................................37
17.4 Data Setup, Hold and Slew Rate Derating: ...................................................................................43
18.0 Physical Dimensions ................................................................................................................48
18.1 64Mbx16 based 64Mx64 Module (1 Rank) .....................................................................................48
18.2 128Mbx8 based 128Mx64/x72 Module (1 Rank) .............................................................................49
18.3 128Mbx8 based 256Mx64/x72 Module (2 Ranks) ............................................................................50
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Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Revision History
Revision
Month
Year
History
1.0
April
2008
- First release
- Change Current SPEC.
- Corrected Typo.
- Changed AC parameters to support binning down backward compatibility
(1333 Mbps 9-9-9 to 1066Mbps 7-7-7)
1.1
1.2
August
2008
2008
October
1.21
1.22
1.23
January
February
July
2009
2009
2009
- Corrected Module Physical Dimensions.
- Added Tolerances to Physical Dimensions
- Corrected Typo.
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Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
1.0 DDR3 Registered DIMM Ordering Information
Number of
Height
Part Number
Density
Organization
Component Composition
Rank
M378B6474DZ1-CF8/H9
M378B2873DZ1-CF8/H9
M391B2873DZ1-CF8/H9
M378B5673DZ1-CF8/H9
M391B5673DZ1-CF8/H9
512MB
1GB
1GB
2GB
2GB
64Mx64
128Mx64
128Mx72
256Mx64
256Mx72
64Mx16(K4B1G1646D-HC##)*4
128Mx8(K4B1G0846D-HC##)*8
128Mx8(K4B1G0846D-HC##)*9
128Mx8(K4B1G0846D-HC##)*16
128Mx8(K4B1G0846D-HC##)*18
1
1
1
2
2
30mm
30mm
30mm
30mm
30mm
Note :
- "##" - F8/H9
- F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9
2.0 Key Features
DDR3-1066
DDR3-1333
9-9-9
1.5
Speed
Unit
7-7-7
1.875
7
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
ns
tCK
ns
9
13.125
13.125
37.5
13.5
13.5
36
ns
tRAS(min)
tRC(min)
ns
50.625
49.5
ns
•
•
•
JEDEC standard 1.5V ± 0.075V Power Supply
DDQ = 1.5V ± 0.075V
533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin
V
•
•
•
•
•
•
8 independent internal bank
Programmable CAS Latency: 6,7,8,9,10
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 6(DDR3-1066) and 7(DDR3-1333)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
•
•
•
•
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then TCASE 85°C, 3.9us at 85°C < TCASE ≤ 95°C
•
Asynchronous Reset
3.0 Address Configuration
Organization
Row Address
A0-A13
Column Address
A0-A9
Bank Address
BA0-BA2
Auto Precharge
A10/AP
128x8(1Gb) based Module
64x16(1Gb) based Module
A0-A12
A0-A9
BA0-BA2
A10/AP
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Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
4.0 x64 DIMM Pin Configurations (Front side/Back Side)
Pin
1
Front
VREFDQ
VSS
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Back
Pin
42
43
44
45
46
47
48
Front
NC
Pin
162
163
164
165
166
167
168
Back
NC
Pin
82
Front
DQ33
VSS
Pin
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
Back
VSS
VSS
VSS
2
DQ4
DQ5
VSS
NC
83
DM4
NC
VSS
3
DQ0
DQ1
VSS
NC
NC
VSS
84
DQS4
DQS4
VSS
VSS
4
NC
NC
VSS
NC
85
5
DM0
NC
86
DQ38
DQ39
VSS
NC (TEST)3
Reset
6
DQS0
DQS0
VSS
87
DQ34
DQ35
VSS
VSS
DQ6
DQ7
VSS
7
88
8
KEY
89
DQ44
DQ45
VSS
CKE1,NC1
VDD
NC
9
DQ2
DQ3
VSS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
90
DQ40
DQ41
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CKE0
VDD
BA2
NC
91
DQ12
DQ13
VSS
NC
NC
92
DM5
NC
DQ8
DQ9
VSS
93
DQS5
DQS5
VSS
VDD
VSS
94
VDD
A11
A7
DM1
NC
A12/BC
A9
95
DQ46
DQ47
VSS
DQS1
DQS1
VSS
96
DQ42
DQ43
VSS
VSS
VDD
97
VDD
A5
DQ14
DQ15
VSS
A8
A6
98
DQ52
DQ53
VSS
DQ10
DQ11
VSS
99
DQ48
DQ49
VSS
VDD
A4
100
101
102
103
104
VDD
DQ20
DQ21
VSS
A3
A1
DM6
NC
DQ16
DQ17
VSS
A2
DQS6
DQS6
VSS
VDD
VDD
VSS
CK1,NC2
VDD
DM2
NC
DQ54
DQ55
VSS
CK1,NC2
VDD
24
25
26
27
28
29
30
31
32
33
34
35
36
DQS2
DQS2
VSS
144
145
146
147
148
149
150
151
152
153
154
155
156
64
65
66
67
68
69
70
71
72
73
74
75
76
184
185
186
187
188
189
190
191
192
193
194
195
196
CK0
CK0
VDD
105
106
107
108
109
110
111
112
113
114
115
116
117
DQ50
DQ51
VSS
225
226
227
228
229
230
231
232
233
234
235
236
237
VSS
VDD
DQ22
DQ23
VSS
DQ60
DQ61
VSS
VREFCA
DQ18
DQ19
VSS
NC
A0
DQ56
DQ57
VSS
NC
VDD
VDD
DQ28
DQ29
VSS
DM7
NC
DQ24
DQ25
VSS
A10/AP
BA0
BA1
VDD
DQS7
DQS7
VSS
VSS
VDD
DM3
NC
RAS
S0
DQ62
DQ63
VSS
DQS3
DQS3
VSS
WE
DQ58
DQ59
VSS
VSS
VDD
CAS
VDD
VDDSPD
DQ30
DQ31
VSS
ODT0
A13
S1, NC1
DQ26
DQ27
VSS
SA0
SA1
SDA
VSS
VTT
ODT1, NC1
VDD
VDD
37
38
39
40
41
157
158
159
160
161
77
78
79
80
81
197
198
199
200
201
118
119
120
SCL
SA2
VTT
238
239
240
NC
NC
VSS
NC
VSS
NC
NC
VSS
NC
VSS
DQ36
DQ37
NC
DQ32
NC = No Connect; NF = No Function; NU = Not Usable; RFU = Reserved Future Use
1. S1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs
2. CK1,NC2 and CK1,NC2 : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated
3. TEST (pin 167) used by memory bus analysis tools (unused on memory DIMMs)
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
6 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
5.0 x72 DIMM Pin Configurations (Front side/Back side)
Pin
1
Front
VREFDQ
VSS
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Back
Pin
42
43
44
45
46
47
48
Front
NC
Pin
162
163
164
165
166
167
168
Back
NC
Pin
82
Front
DQ33
VSS
Pin
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
Back
VSS
VSS
VSS
2
DQ4
DQ5
VSS
NC
83
DM4
NC
VSS
3
DQ0
DQ1
VSS
CB6
CB7
VSS
84
DQS4
DQS4
VSS
VSS
4
CB2
CB3
VSS
NC
85
5
DM0
NC
86
DQ38
DQ39
VSS
NC (TEST)3
Reset
6
DQS0
DQS0
VSS
87
DQ34
DQ35
VSS
VSS
DQ6
DQ7
VSS
7
88
8
KEY
89
DQ44
DQ45
VSS
CKE1,NC1
VDD
NC
9
DQ2
DQ3
VSS
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
90
DQ40
DQ41
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
CKE0
VDD
BA2
NC
91
DQ12
DQ13
VSS
NC
NC
92
DM5
NC
DQ8
DQ9
VSS
93
DQS5
DQS5
VSS
VDD
VSS
94
VDD
A11
A7
DM1
NC
A12/BC
A9
95
DQ46
DQ47
VSS
DQS1
DQS1
VSS
96
DQ42
DQ43
VSS
VSS
VDD
97
VDD
A5
DQ14
DQ15
VSS
A8
A6
98
DQ52
DQ53
VSS
DQ10
DQ11
VSS
99
DQ48
DQ49
VSS
VDD
A4
100
101
102
103
104
VDD
DQ20
DQ21
VSS
A3
A1
DM6
NC
DQ16
DQ17
VSS
A2
DQS6
DQS6
VSS
VDD
VDD
VSS
CK1,NC2
VDD
DM2
NC
DQ54
DQ55
VSS
CK1,NC2
VDD
24
25
26
27
28
29
30
31
32
33
34
35
36
DQS2
DQS2
VSS
144
145
146
147
148
149
150
151
152
153
154
155
156
64
65
66
67
68
69
70
71
72
73
74
75
76
184
185
186
187
188
189
190
191
192
193
194
195
196
CK0
CK0
VDD
105
106
107
108
109
110
111
112
113
114
115
116
117
DQ50
DQ51
VSS
225
226
227
228
229
230
231
232
233
234
235
236
237
VSS
VDD
DQ22
DQ23
VSS
DQ60
DQ61
VSS
VREFCA
DQ18
DQ19
VSS
EVENT
A0
DQ56
DQ57
VSS
NC
VDD
VDD
DQ28
DQ29
VSS
DM7
NC
DQ24
DQ25
VSS
A10/AP
BA0
BA1
VDD
DQS7
DQS7
VSS
VSS
VDD
DM3
NC
RAS
S0
DQ62
DQ63
VSS
DQS3
DQS3
VSS
WE
DQ58
DQ59
VSS
VSS
VDD
CAS
VDD
VDDSPD
DQ30
DQ31
VSS
ODT0
A13
S1, NC1
DQ26
DQ27
VSS
SA0
SA1
SDA
VSS
VTT
ODT1, NC1
VDD
VDD
37
38
39
40
41
157
158
159
160
161
77
78
79
80
81
197
198
199
200
201
118
119
120
SCL
SA2
VTT
238
239
240
CB4
CB5
VSS
NC
VSS
CB0
CB1
VSS
NC
VSS
DQ36
DQ37
DM8
DQ32
NC = No Connect; NF = No Function; NU = Not Usable; RFU = Reserved Future Use
1. S1, ODT1, CKE1: Used for dual-rank UDIMMs; NC on single-rank UDIMMs
2. CK1,NC2 and CK1,NC2 : Used for dual-rank UDIMMs; not used on single-rank UDIMMs, but terminated
3. TEST (pin 167) used by memory bus analysis tools (unused on memory DIMMs)
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
7 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
6.0 Pin Description
Pin Name
A0-A13
BA0-BA2
RAS
Description
Pin Name
SCL
Description
I2C serial bus clock for EEPROM
I2C serial bus data line for EEPROM
I2C serial address select for EEPROM
SDRAM address bus
SDRAM bank select
SDA
SDRAM row address strobe
SDRAM column address strobe
SDRAM write enable
SA0-SA2
VDD
*
CAS
SDRAM core power supply
VDDQ
*
WE
SDRAM I/O Driver power supply
SDRAM I/O reference supply
VREFDQ
VREFCA
VSS
S0, S1
CKE0,CKE1
DIMM Rank Select Lines
SDRAM clock enable lines
SDRAM command/address reference supply
Power supply return (ground)
ODT0, ODT1 On-die termination control lines
VDDSPD
NC
DQ0 - DQ63
CB0 - CB7
DIMM memory data bus
DIMM ECC check bits
Serial EEPROM positive power supply
Spare Pins(no connect)
SDRAM data strobes
Used by memory bus analysis tools
(unused on memory DIMMs)
DQS0 - DQS8
DQS0-DQS8
DM0-DM8
TEST
RESET
EVENT
VTT
(positive line of differential pair)
SDRAM differential data strobes
(negative line of differential pair)
Set DRAMs Known State
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
Reserved for optional temperature-sensing hardware
SDRAM I/O termination supply
Reserved for future use
SDRAM clocks
(positive line of differential pair)
CK0, CK1
SDRAM clocks
(negative line of differential pair)
CK0, CK1
RFU
*The V and V
pins are tied common to a single power-plane on these designs.
DDQ
DD
7.0 SPD and Thermal Sensor for ECC UDIMMs
On DIMM thermal sensor will provide DRAM temperature readout through a integrated thermal sensor.
SCL
SDA
EVENT
WP/EVENT
SA0
R1
0 Ω
SA1
SA1
SA2
SA2
R2
0 Ω
SA0
Note :
1. Raw Cards D (1Rx8 ECC) and E (2Rx8 ECC) support a thermal sensor.
2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.
When only the SPD is placed on the module, R2 is placed but R1 is not.
Temperature Sensor Characteristics
Temperature Sensor Accuracy
Grade
Range
Units
Notes
Min.
Typ.
+/- 0.5
+/- 1.0
+/- 2.0
0.25
Max.
75 < Ta < 95
40 < Ta < 125
-20 < Ta < 125
-
-
-
+/- 1.0
+/- 2.0
+/- 3.0
-
-
-
-
B
°C
Resolution
°C /LSB
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Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
8.0 Input/Output Functional Description
Symbol
Type
Function
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive
edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of
crossing)
CK0-CK1
CK0-CK1
SSTL
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self-Refresh mode
CKE0-CKE1
SSTL
SSTL
Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the
command decoder is disabled, new command are ignored but previous operations continue. This signal provides for
external rank selection on systems with multiple ranks.
S0-S1
RAS, CAS, WE
ODT0-ODT1
SSTL
SSTL
RAS, CAS, and WE (ALONG WITH S) define the command being entered.
When high, termination resistance is enabled for all DQ, DQS, DQS and DM pins, assuming the function is enabled in
the Extended Mode Register Set (EMRS).
VREFDQ
VREFCA
Supply Reference voltage for SSTL 15 I/O inputs.
Supply Reference voltage for SSTL 15 command/address inputs.
Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered
DIMM designs, VDDQ shares the same power plane as VDD pins.
VDDQ
Supply
BA0-BA2
SSTL
Selects which SDRAM bank of eight is activated.
During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)
During a Read or Write command cycle, Address input defines the column address, In addition to the column address,
AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is
selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a pre-
charge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is
high, all banks will be precharged regardless of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used
to define which bank to precharge. A12(BC) is sampled during READ and WRITE commands to determine if burst chop
(on-the-fly) will be performed (HIGH, no burst chop; Low, burst chopped).
A0-A13
SSTL
DQ0-DQ63
CB0-CB7
SSTL
SSTL
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data
during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading.
DM0-DM8
Power and ground for DDR3 SDRAM input buffers, and core logic. VDD and VDDQ pins are tied to VDD/VDDQ planes on
these modules.
V
DD,VSS
Supply
DQS0-DQS8
DQS0-DQS8
Data strobe for input and output data. For raw cards using x16 organized DRAMs, Pins DQ0-7 are associated with the
LDQS and LDQS pins and Pins DQ8-15 are associated with UDQS and UDQS pins.
SSTL
These signals and tied at the system planar to either VSS or VDDSPD to configure the serial SPD EERPOM address
range.
SA0-SA2
SDA
-
-
-
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected
from the SDA bus line to VDDSPD to act as a pull-up on the system board.
This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL
bus time to VDDSPD to act as a pull-up on the system board.
SCL
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane. EEPROM supply is operable
from 3.0V to 3.6V.
VDDSPD
Supply
-
RESET
EVENT
The RESET pin is connected to the RESET pin on each DRAM. When low, all DRAMs are set to a know state.
This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guaran-
tee the electrical level requirement is met for the EVENT pin on TS/SPD part
Output
9 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
8.1 Address Mirroring Feature
There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The length
of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend
the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.
The pins on the DRAM are defined in a manner that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical
support pins, do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are address pins A3, A4, A5,
A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 DRAM pins are wired straight, with no mismatch between the connector pin
assignment and the DRAM pin assignment. Some of the Rank 1 DRAM pins are cross wired as defined in the table. Pins not listed in the table are wired
straight.
8.1.1 DRAM Pin Wiring Mirroring
DRAM Pin
Connector Pin
Rank 0
A3
Rank 1
A4
A3
A4
A4
A3
A5
A5
A6
A6
A6
A5
A7
A7
A8
A8
A8
A7
BA0
BA1
BA0
BA1
BA1
BA0
Figure 1 illustrates the wiring in both the mirrored and non-mirrored case. The lengths of the traces to the DRAM pins, is obviously shorter. The via grid is smaller as well.
Figure 1 - Wiring Differences for Mirrored and Non-Mirrored Addresses
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is read the same way. There are limi-
tations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know
if the rank is mirrored or not. This requires a few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a
requirement that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been designed with the mir-
rored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller must read the SPD and have the capability of de-mirroring
the address when accessing the second rank.
10 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
9.0 Function Block Diagram:
9.1 512MB, 64Mx64 Module (Populated as 1 rank of x16 DDR3 SDRAMs)
S0
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS0
DQS0
DM0
DQS4
DQS4
DM4
CS
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D0
UDQS
UDQS
UDM
UDQS
UDQS
UDM
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
I/O 8
DQ9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
ZQ
ZQ
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS2
DM2
DQS6
DQS6
DM6
CS
CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D1
D1
UDQS
UDQS
UDM
UDQS
UDQS
UDM
DQS3
DQS3
DM3
DQS3
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 8
I/O 8
I/O 9
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
ZQ
ZQ
Serial PD
SCL
SDA
WP
A0
A1
A2
SA0 SA1 SA2
Note :
V
BA0 - BA2
A0 - A14
RAS
BA0-BA2 : SDRAMs D0 - D3
A0-A14 : SDRAMs D0 - D3
RAS : SDRAMs D0 - D3
CAS : SDRAMs D0 - D3
CKE : SDRAMs D0 - D3
WE : SDRAMs D0 - D3
ODT : SDRAMs D0 - D3
CK : SDRAMs D0 - D3
CK : SDRAMs D0 - D3
RESET : SDRAMs D0 - D3
DDSPD
SPD
V
/V
D0 - D3
D0 - D3
D0 - D3
D0 - D3
DD DDQ
1. DQ-to-I/O wiring is shown as recommended but may be
changed.
V
REFDQ
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be
maintained as shown.
CAS
V
SS
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
CKE0
WE
V
REFCA
4. Refer to the appropriate clock wiring topology under the
DIMM wiring details section of this document.
5. The pair CK1 and CK1 is terminated in 7.5Ω but is not
used on the module.
ODT0
CK0
6. A15 is not routed on the module.
7. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ω ± 1%
8. One SPD exists per module.
CK0
RESET
11 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
9.2 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs)
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
ZQ
ZQ
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
ZQ
ZQ
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
ZQ
ZQ
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
NU/ CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
ZQ
ZQ
Serial PD
SCL
SDA
WP
A0
Note :
BA0 - BA2
A0 - A13
RAS
BA0-BA2 : SDRAMs D0 - D7
A0-A13 : SDRAMs D0 - D7
RAS : SDRAMs D0 - D7
CAS : SDRAMs D0 - D7
CKE : SDRAMs D0 - D7
WE : SDRAMs D0 - D7
ODT : SDRAMs D0 - D7
CK : SDRAMs D0 - D7
A1
SA0 SA1
A2
1. DQ-to-I/O wiring is shown as recommended but may be
changed.
SA2
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be
maintained as shown.
CAS
V
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
DDSPD
SPD
CKE0
WE
V
/V
D0 - D7
D0 - D7
D0 - D7
D0 - D7
DD DDQ
4. Refer to the appropriate clock wiring topology under the
DIMM wiring details section of this document.
5. Refer to section 7.1 of this document for details on
address mirroring.
V
REFDQ
ODT0
CK0
V
SS
6. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
7. One SPD exists per module.
V
REFCA
12 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
9.3 1GB, 128Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs)
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
ZQ
ZQ
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
ZQ
ZQ
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
ZQ
ZQ
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
ZQ
ZQ
DQS8
DQS8
DM8
Serial PD
DM
CS DQS DQS
SCL
EVENT
SDA
EVENT
A0 A1
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
A2
SA0 SA1 SA2
ZQ
Note :
V
BA0 - BA2
A0 - A15
RAS
BA0-BA2 : SDRAMs D0 - D8
A0-A15 : SDRAMs D0 - D8
RAS : SDRAMs D0 - D8
CAS : SDRAMs D0 - D8
CKE : SDRAMs D0 - D8
WE : SDRAMs D0 - D8
ODT : SDRAMs D0 - D8
CK : SDRAMs D0 - D8
DDSPD
/V
SPD
V
D0 - D8
D0 - D8
D0 - D8
D0 - D8
1. DQ-to-I/O wiring is shown as recommended but may be
changed.
DD DDQ
V
REFDQ
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be
maintained as shown.
CAS
V
SS
3. DQ, CB, DM, DQS/DQS resistors: Refer to associated
topology diagram.
CKE0
WE
V
REFCA
4. Refer to the appropriate clock wiring topology under the
DIMM wiring details section of this document.
5. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
6. Refer to "SPD and Thermal sensor for ECC UDIMMs"
for SPD detail.
ODT0
CK0
13 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
9.4 2GB, 256Mx64 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
ZQ
ZQ
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
ZQ
ZQ
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
ZQ
ZQ
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
ZQ
ZQ
DQS8
DQS8
DM8
Serial PD
DM
CS DQS DQS
SCL
EVENT
SDA
EVENT
A0 A1
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
A2
SA0 SA1 SA2
ZQ
Note :
V
BA0 - BA2
A0 - A15
RAS
BA0-BA2 : SDRAMs D0 - D8
A0-A15 : SDRAMs D0 - D8
RAS : SDRAMs D0 - D8
CAS : SDRAMs D0 - D8
CKE : SDRAMs D0 - D8
WE : SDRAMs D0 - D8
ODT : SDRAMs D0 - D8
CK : SDRAMs D0 - D8
DDSPD
/V
SPD
V
D0 - D8
D0 - D8
D0 - D8
D0 - D8
1. DQ-to-I/O wiring is shown as recommended but may be
changed.
DD DDQ
V
REFDQ
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be
maintained as shown.
CAS
V
SS
3. DQ, CB, DM, DQS/DQS resistors: Refer to associated
topology diagram.
CKE0
WE
V
REFCA
4. Refer to the appropriate clock wiring topology under the
DIMM wiring details section of this document.
5. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
6. Refer to "SPD and Thermal sensor for ECC UDIMMs"
for SPD detail.
ODT0
CK0
14 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
9.5 2GB, 256Mx72 ECC Module (Populated as 2 ranks of x8 DDR3 SDRAMs)
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D9
D4
D13
ZQ
ZQ
ZQ
ZQ
DQS1
DQS1
DM1
DQS5
DQS5
DM5
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
ZQ
ZQ
ZQ
ZQ
DQS2
DQS2
DM2
DQS6
DQS6
DM6
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
D2
D11
D6
D15
I/O 6
I/O 7
I/O 6
I/O 7
ZQ
ZQ
ZQ
ZQ
DQS3
DQS3
DM3
DQS7
DQS7
DM7
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D12
D7
D16
ZQ
ZQ
ZQ
ZQ
DQS8
DQS8
DM8
Serial PD
DM
CS DQS DQS
DM
CS DQS DQS
SCL
EVENT
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D17
SDA
EVENT
A0 A1
A2
SA0 SA1 SA2
ZQ
ZQ
Note :
BA0 - BA2
BA0-BA2 : SDRAMs D0 - D17
A0-A15 : SDRAMs D0 - D17
CKE : SDRAMs D9 - D17
CKE : SDRAMs D0 - D8
RAS : SDRAMs D0 - D17
CAS : SDRAMs D0 - D17
WE : SDRAMs D0 - D17
ODT : SDRAMs D0 - D8
ODT : SDRAMs D9 - D17
CK : SDRAMs D0 - D8
A0 - A15
CKE1
CKE0
RAS
1. DQ-to-I/O wiring is shown as recommended but may be
changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be
maintained as shown.
V
DDSPD
SPD
V
/V
D0 - D17
D0 - D17
D0 - D17
D0 - D17
3. DQ, CB, DM, DQS, DQS resistors: Refer to associated
topology diagram.
DD DDQ
V
REFDQ
4. Refer to section 7.1 of this document for details on
address mirroring.
CAS
V
SS
WE
5. For each DRAM, a unique ZQ resistor is connected to
ground. The ZQ resistor is 240 Ohm +/- 1%
6. Refer to "SPD and Thermal sensor for ECC UDIMMs"
for SPD detail.
V
REFCA
ODT0
ODT1
CK0
CK1
CK : SDRAMs D9 - D17
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10.0 Absolute Maximum Ratings
10.1 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Notes
VDD
Voltage on VDD pin relative to VSS
-0.4 V ~ 1.975 V
V
1,3
VDDQ
Voltage on VDDQ pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
-0.4 V ~ 1.975 V
-0.4 V ~ 1.975 V
-55 to +100
V
V
1,3
1
V
IN, VOUT
TSTG
Note :
°C
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than 0.6 x VDDQ, When VDD and VDDQ are less than
500mV; VREF may be equal to or less than 300mV.
10.2 DRAM Component Operating Temperature Range
Symbol
Parameter
rating
Unit
Notes
TOPER
Operating Temperature Range
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the
JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case tem-
perature must be maintained between 0-85°C under all operating conditions
3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaran-
teed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us. It is also possible to specify a component
with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with
Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode
(MR2 A6 = 1b and MR2 A7 = 0b)
11.0 AC & DC Operating Conditions
11.1 Recommended DC Operating Conditions (SSTL - 15)
Rating
Typ.
1.5
Symbol
Parameter
Units
Notes
Min.
1.425
1.425
Max.
1.575
1.575
VDD
Supply Voltage
Supply Voltage for Output
V
V
1,2
1,2
VDDQ
1.5
Note :
1. Under all conditions VDDQ must be less than or equal to VDD
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
.
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12.0 AC & DC Input Measurement Levels
12.1 AC & DC Logic Input Levels for Single-ended Signals
Single Ended AC and DC input levels for Command and Address
DDR3-1066
DDR3-1333
Symbol
Parameter
Unit Notes
Max.
Min.
Max.
Min.
VIH.CA(DC)
VREF + 100
VDD
VREF + 100
VSS
VDD
DC input logic high
DC input logic low
AC input logic high
AC input logic low
AC input logic high
AC input logic low
mV
mV
mV
mV
mV
mV
1
V
IL.CA(DC)
IH.CA(AC)
IL.CA(AC)
IH.CA(AC150)
IL.CA(AC150)
VSS
VREF - 100
VREF - 100
1
V
VREF + 175
VREF + 175
-
-
1,2
1,2
1,2
1,2
V
VREF - 175
VREF - 175
-
-
-
-
V
VREF+150
-
-
-
V
VREF-150
-
Reference Voltage for ADD,
CMD inputs
V
REFCA(DC)
0.49*VDD
0.51*VDD
0.49*VDD
0.51*VDD
V
3,4
Note :
1. For input only pins except RESET, VREF = VREFCA(DC)
2. See "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
Single Ended AC and DC input levels for DQ and DM
DDR3-1066
DDR3-1333
Symbol
Parameter
Unit Notes
Min.
Max.
Min.
Max.
VIH.DQ(DC)
VREF + 100
VDD
VREF + 100
VDD
DC input logic high
DC input logic low
mV
mV
mV
mV
V
1
V
IL.DQ(DC)
IH.DQ(AC)
IL.DQ(AC)
VREFDQ(DC)
Note :
VSS
VREF - 100
VSS
VREF - 100
1
V
VREF + 175
VREF + 150
AC input logic high
AC input logic low
-
-
1,2,5
1,2,5
3,4
V
VREF - 175
0.51*VDD
VREF - 150
0.51*VDD
-
-
0.49*VDD
0.49*VDD
I/O Reference Voltage(DQ)
1. For input only pins except RESET, VREF = VREFDQ(DC)
2. See 9.6 "Overshoot and Undershoot specifications" section.
3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV)
4. For reference : approx. VDD/2 ± 15mV
5. Single ended swing requirement for DQS - DQS is 350mV (peak to peak). Differential swing for DQS - DQS is 700mV (peak to peak).
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12.2 V
Tolerances
REF
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 2. It shows a valid reference voltage
REF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise).
REF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of VREF. Fur-
thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD
V
V
.
voltage
VDD
VSS
time
Figure 2. Illustration of VREF(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF
.
"VREF" shall be understood as VREF(DC), as defined in Figure 2.
This clarifies, that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF ac-noise. Timing
and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.
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12.3 AC & DC Logic Input Levels for Differential Signals
12.3.1 Differential Signals Definition
tDVAC
VIH.DIFF.AC.MIN
VIH.DIFF.MIN
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 3 : Definition of differential ac-swing and "time above ac level" tDVAC
12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)
DDR3-1066/1333
Symbol
Parameter
unit
Note
min
+0.2
max
note 3
VIHdiff
VILdiff
differential input high
differential input low
V
V
V
V
1
1
2
2
note 3
-0.2
V
IHdiff(AC)
ILdiff(AC)
2 x (VIH(AC)-VREF
note 3
)
differential input high ac
differential input low ac
note 3
V
2 x (VREF - VIL(AC))
Notes:
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a
reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet
Specification " on page20.
Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS.
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
Slew Rate [V/ns]
min
75
57
50
38
34
29
22
13
0
max
min
175
170
167
163
162
161
159
155
150
150
max
> 4.0
4.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
0
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12.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every
half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle
proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD sig-
nals, then these ac-levels apply also for the single-ended signals CK and CK .
VDD or VDDQ
VSEH min
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSEL max
VSEL
VSS or VSSQ
time
Figure 4 : Single-ended requirement for differential signals.
Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement
with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common
mode characteristics of these signals.
Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3-1066/1333
Symbol
Parameter
Unit
Notes
Min
Max
Note3
Note3
(VDD/2)+0.175
(VDD/2)+0.175
Note3
Single-ended high-level for strobes
Single-ended high-level for CK, CK
Single-ended low-level for strobes
Single-ended low-level for CK, CK
V
V
V
V
1, 2
1, 2
1, 2
1, 2
VSEH
(VDD/2)-0.175
(VDD/2)-0.175
VSEL
Note3
Notes:
1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a
signal group, then the reduced level applies also here
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot
Specification"
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12.3.4 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input
signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signal to the mid level between of VDD and VSS
.
VDD
CK, DQS
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
Figure 5. VIX Definition
Cross point voltage for differential input signals (CK, DQS)
DDR3-1066/1333
Symbol
Parameter
Unit
Notes
Min
-150
-175
-150
Max
150
175
150
mV
mV
mV
VIX
VIX
Differential Input Cross Point Voltage relative to VDD/2 for CK,CK
1
Differential Input Cross Point Voltage relative to VDD/2 for DQS,DQS
Note :
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing VSEL
/
V
SEH of at least VDD/2 =/-250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns. Refer to table 11 on page 17 for VSEL and VSEH standard
values.
12.4 Slew Rate Definition for Single-ended Input Signals
See "Address / Command Setup, Hold and Derating" on page 36 for single-ended slew rate definitions for address and command signals.
See "Data Setup, Hold and Slew Rate Derating"° on page 42 for single-ended slew rate definitions for data signals.tDH nominal slew rate for a falling sig-
nal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF
12.5 Slew Rate Definition for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.
Differential input slew rate definition
Measured
From
Description
Defined by
To
VIHdiffmin - VILdiffmax
Delta TRdiff
VIHdiffmin - VILdiffmax
VILdiffmax
VIHdiffmin
Differential input slew rate for rising edge (CK-CK and DQS-DQS)
Differential input slew rate for falling edge (CK-CK and DQS-DQS)
VIHdiffmin
VILdiffmax
Delta TFdiff
V
IHdiffmin
ILdiffmax
0
V
delta TFdiff
delta TRdiff
Figure 6. Differential Input Slew Rate definition for DQS, DQS and CK, CK
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13.0 AC & DC Output Measurement Levels
13.1 Single-ended AC & DC Output Levels
Single Ended AC and DC output levels
Symbol Parameter
DDR3-1066/1333
Units
Notes
VOH(DC) DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
V
OM(DC) DC output mid measurement level (for IV curve linearity)
OL(DC) DC output low measurement level (for IV curve linearity)
OH(AC) AC output high measurement level (for output SR)
OL(AC) AC output low measurement level (for output SR)
0.5 x VDDQ
0.2 x VDDQ
V
V
V
V
V
V
VTT + 0.1 x VDDQ
VTT - 0.1 x VDDQ
1
1
V
Note : 1. The swing of +/-0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2.
13.2 Differential AC & DC Output Levels
Differential AC and DC output levels
Symbol
Parameter
DDR3-1066/1333
Units
Notes
V
OHdiff(AC)
AC differential output high measurement level (for output SR)
+0.2 x VDDQ
V
1
V
OLdiff(DC)
AC differential output low measurement level (for output SR)
-0.2 x VDDQ
V
1
Note : 1. The swing of +/-0.2xVDDQ is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω
and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs.
13.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC)
for single ended signals as shown in below.
Single Ended Output slew rate definition
Measured
Description
Defined by
From
To
VOH(AC)-VOL(AC)
Delta TRse
VOL(AC)
VOH(AC)
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
VOH(AC)-VOL(AC)
Delta TFse
VOH(AC)
VOL(AC)
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
Single Ended Output slew rate
DDR3-1066
DDR3-1333
Parameter
Symbol
Units
Min
Max
Min
Max
Single ended output slew rate
Description : SR : Slew Rate
SRQse
2.5
5
2.5
5
V/ns
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
se : Singe-ended Signals
For Ron = RZQ/7 setting
V
OH(AC)
V
V
TT
OL(AC)
delta TFse
delta TRse
Figure 7. Single Ended Output Slew Rate definition
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13.4 DIfferential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and
OHdiff(AC) for differential signals as shown in below.
V
Differential Output slew rate definition
Description
Measured
Defined by
From
To
VOHdiff(AC)-VOLdiff(AC)
Delta TRdiff
V
OLdiff(AC)
VOHdiff(AC)
Differential output slew rate for rising edge
Differential output slew rate for falling edge
VOHdiff(AC)-VOLdiff(AC)
Delta TFdiff
V
OHdiff(AC)
VOLdiff(AC)
Note : Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output slew rate
DDR3-1066
DDR3-1333
Parameter
Symbol
Units
Min
Max
Min
Max
Differential output slew rate
Description : SR : Slew Rate
SRQse
5
10
5
10
V/ns
Q : Query Output (like in DQ, which stands for Data-in, Query-Output
diff : Singe-ended Signals
V
(AC)
OHdiff
V
V
TT
(AC)
OLdiff
delta TFdiff
delta TRdiff
Figure 8. Differential Output Slew Rate definition
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14.0 IDD Specification Definition
Symbol
Description
Operating One Bank Active-Precharge Current
a)
CKE: High; External clock: On; tCK, nRC, nRAS, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: High between ACT and PRE; Command, Address, Bank
IDD0
Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer
b)
and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0
Operating One Bank Active-Read-Precharge Current
a)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: High between ACT, RD and PRE; Command, Address,
IDD1
Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... ; Output Buffer and
b)
RTT: Enabled in Mode Registers ; ODT Signal: stable at 0;
Precharge Standby Current
a)
IDD2N
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling ;
Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0
b)
Precharge Standby ODT Current
a)
DD2NT
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling ;
Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: toggling
b)
DDQ2NT
(optional)
Precharge Standby ODT IDDQ Current
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
a)
IDD2P0
b)
FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Precharge
c)
Power Down Mode: Slow Exit
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data
a)
IDD2P1
IDD2Q
IDD3N
IDD3P
b)
IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pecharge
c)
Power Down Mode: Fast Exit
Precharge Quiet Standby Current
a)
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0
b)
Active Standby Current
a)
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling
according to Table 34 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers ; ODT Sig-
nal: stable at 0
b)
Active Power-Down Current
a)
CKE: Low; External clock: On; tCK, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO:
FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0
b)
Operating Burst Read Current
a)
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially tog-
gling ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 36 ; DM:stable at 0; Bank Activity: all
banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 10); Output Buffer and RTT: Enabled in Mode Registers ; ODT
Signal: stable at 0
IDD4R
b)
IDDQ4R
(optional)
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
a)
CKE: High; External clock: On; tCK, CL: AC Timing Table ; BL: 8 ; AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially tog-
gling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank Activity: all banks open, WR com-
mands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at HIGH
IDD4W
IDD5B
IDD6
b)
Burst Refresh Current
a)
CKE: High; External clock: On; tCK, CL, nRFC: AC Timing Table ; BL: 8 ; AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: par-
tially toggling according to Table 38 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output Buffer and RTT:
Enabled in Mode Registers ; ODT Signal: stable at 0
b)
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Normal ; CKE: Low; External clock: Off; CK and CK:
LOW; CL: AC Timing Table ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-Refresh opera-
tion; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
d)
e)
a)
b)
24 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Symbol
Description
f)
Self-Refresh Current: Extended Temperature Range (optional)
d)
e)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Extended ; CKE: Low; External clock: Off; CK and CK:
LOW; CL: AC Timing Table ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Extended Tempera-
ture Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
IDD6ET
a)
b)
f)
Auto Self-Refresh Current (optional)
d)
e)
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabled ; Self-Refresh Temperature Range (SRT): Normal ; CKE: Low; External clock: Off; CK and CK:
IDD6TC
IDD7
a)
LOW; CL: AC Timing Table ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING; DM:stable at 0; Bank Activity: Auto
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING
b)
Operating Bank Interleave Read Current
a)
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: AC Timing Table; BL: 8 ; AL: CL-1; CS: High between ACT and RDA; Com-
mand, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and the next one ; DM:stable at 0;
Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output Buffer and RTT: Enabled in Mode Reg-
b)
isters ; ODT Signal: stable at 0
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device
g) IDD current measure method and detail patterns are described on DDR3 component datasheet
25 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
14.1 IDD SPEC Table
M378B6474DZ1 : 512MB(64Mx64) Module
F8
H9
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
360
500
44
400
540
48
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
180
220
220
180
240
920
940
840
40
200
240
240
200
260
1160
1160
880
40
IDD4R
IDD4W
IDD5B
IDD6
IDD7
1240
1480
M378B2873DZ1 : 1GB(128Mx64) Module
F8
H9
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
680
840
88
720
880
96
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
360
440
440
360
480
1360
1520
1680
80
400
480
480
400
520
1640
1840
1760
80
IDD4R
IDD4W
IDD5B
IDD6
IDD7
2200
2920
26 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
M378B5673DZ1: 2GB(256Mx64) Module
F8
H9
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
1120
1280
176
720
880
880
720
920
1800
1960
2120
160
1200
1360
192
800
960
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
960
800
1000
2120
2320
2240
160
IDD4R
IDD4W
IDD5B
IDD6
IDD7
2640
3400
M391B2873DZ1: 1GB(128Mx72) Module
F8
H9
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
765
945
100
405
495
495
405
540
1530
1710
1890
90
810
990
108
450
540
540
450
585
1845
2070
1980
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD4R
IDD4W
IDD5B
IDD6
IDD7
2475
3285
27 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
M391B5673DZ1 : 2GB(256Mx72) Module
F8
H9
Symbol
Unit
Notes
(DDR3-1066@CL=7)
(DDR3-1333@CL=9)
IDD0
IDD1
IDD2P0(slow exit)
IDD2P1(fast exit)
IDD2N
IDD2Q
IDD3P(fast exit)
IDD3N
1260
1440
200
810
990
1350
1530
220
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
900
1080
1080
900
1125
2385
2610
2520
180
990
810
1035
2025
2205
2385
180
IDD4R
IDD4W
IDD5B
IDD6
IDD7
2970
3825
28 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
15.0 Input/Output Capacitance
15.1 Non ECC UDIMM
M378B6474DZ1
DDR3-1066 DDR3-1333
Parameter
Symbol
Units
Notes
Notes
Notes
Min
Max
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
M378B2873DZ1
DDR3-1066 DDR3-1333
Parameter
Symbol
Units
Min
Max
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
M378B5673DZ1
DDR3-1066 DDR3-1333
Parameter
Symbol
Units
Min
Max
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
15.2 ECC UDIMM
M391B2873DZ1
DDR3-1066 DDR3-1333
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
M391B5673DZ1
DDR3-1066 DDR3-1333
Parameter
Symbol
Units
Notes
Min
Max
Min
Max
Input/output capacitance
(DQ, DM, DQS, DQS, TDQS, TDQS)
CIO
-
TBD
-
TBD
pF
Input capacitance (CK and CK)
CCK
CI
-
-
-
TBD
TBD
TBD
-
-
-
TBD
TBD
TBD
pF
pF
pF
Input capacitance (All other input-only pins)
Input/output capacitance of ZQ pin
CZQ
29 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
16.0 Electrical Characteristics and AC timing
(0 °C<TCASE ≤95 °C, VDDQ = 1.5V ± 0.075V; VDD = 1.5V ± 0.075V)
16.1 Refresh Parameters by Device Density
Parameter
All Bank Refresh to active/refresh cmd time
Symbol
tRFC
1Gb
110
7.8
2Gb
160
7.8
4Gb
300
7.8
8Gb
350
7.8
Units
ns
Note
0 °C ≤ TCASE ≤ 85°C
µs
Average periodic refresh interval
tREFI
85 °C < TCASE ≤ 95°C
3.9
3.9
3.9
3.9
µs
1
Note :
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or
requirements referred to in this material.
16.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
DDR3-1066
7-7-7
min
DDR3-1333
9-9-9
min
9
Units
Note
Bin (CL - tRCD - tRP)
Parameter
CL
7
tCK
ns
ns
ns
ns
ns
ns
tRCD
tRP
13.13
13.13
37.5
13.5
13.5
36
tRAS
tRC
50.63
7.5
49.5
6.0
tRRD
tFAW
37.5
30
16.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin
DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-1066 Speed Bins
Speed
CL-nRCD-nRP
DDR3-1066
7 - 7 - 7
Units
Note
Parameter
Symbol
tAA
min
13.125
13.125
13.125
50.625
37.5
max
20
Internal read command to first data
ACT to internal read or write delay time
PRE command period
ns
ns
tRCD
-
tRP
-
-
ns
ACT to ACT or REF command period
ACT to PRE command period
tRC
ns
tRAS
9*tREFI
3.3
ns
8
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
ns
1,2,3,6
1,2,3,4
4
CL = 6
CL = 7
CL = 8
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
Reserved
Reserved
ns
ns
1.875
1.875
<2.5
<2.5
ns
1,2,3,4
4
Reserved
ns
ns
1,2,3
Supported CL Settings
Supported CWL Settings
6,7,8
5,6
nCK
nCK
30 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
DDR3-1333 Speed Bins
Speed
CL-nRCD-nRP
DDR3-1333
9 -9 - 9
Units
Note
Parameter
Symbol
tAA
min
max
20
Internal read command to first data
ACT to internal read or write delay time
PRE command period
13.5 (13.125)5,9
13.5 (13.125)5,9
13.5 (13.125)5,9
49.5 (49.125)5,9
36
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRCD
-
tRP
-
-
ACT to ACT or REF command period
ACT to PRE command period
tRC
tRAS
9*tREFI
3.3
8
1,2,3,7
1,2,3,4,7
4
CWL = 5
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
2.5
CL = 6
CWL = 6
CWL = 7
CWL = 5
Reserved
Reserved
Reserved
4
1.875
<2.5
<2.5
CL = 7
CWL = 6
tCK(AVG)
ns
1,2,3,4,7
(Optional) Note 5,9
Reserved
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5,6
CWL = 7
CWL = 5,6
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
tCK(AVG)
ns
ns
1,2,3,4,
Reserved
4
1,2,3,7
1,2,3,4,
4
CL = 8
CL = 9
CL = 10
1.875
ns
Reserved
Reserved
ns
ns
1.5
1.5
<1.875
<1.875
ns
1,2,3,4
4
Reserved
ns
ns
1,2,3
5
CWL = 7
tCK(AVG)
(Optional)
6,7,8,9
5,6,7
ns
Supported CL Settings
Supported CWL Settings
nCK
nCK
16.3.1 Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Note :
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be ful-
filled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequen-
cies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL".
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns
or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. "Reserved" settings are not allowed. User must program a different value.
5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier’s data sheet and/
or the DIMM SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but
verified by Design/Characterization.
9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to
match. For example, DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte
16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should pro-
gram 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRC-
min (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin=36ns+13.125ns) for DDR3-1333(CL9) and
48.125ns (tRASmin+tRPmin=35ns+13.125ns) for DDR3-1600(CL11).
31 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
17.0 Timing Parameters by Speed Grade
Speed
DDR3-1066
DDR3-1333
Units
Note
Parameter
Symbol
MIN
MAX
MIN
MAX
Clock Timing
tCK(DLL_OF
F)
Minimum Clock Cycle Time (DLL off mode)
8
-
8
-
ns
6
Average Clock Period
Clock Period
tCK(avg)
tCK(abs)
See Speed Bins Table
ps
ps
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
Average high pulse width
tCH(avg)
tCL(avg)
0.47
0.47
-90
0.53
0.53
90
0.47
0.47
-80
0.53
0.53
80
tCK(avg)
Average low pulse width
tCK(avg)
ps
Clock Period Jitter
tJIT(per)
Clock Period Jitter during DLL locking period
Cycle to Cycle Period Jitter
tJIT(per, lck)
tJIT(cc)
-80
80
-70
70
ps
180
160
160
140
ps
Cycle to Cycle Period Jitter during DLL locking period
Cumulative error across 2 cycles
Cumulative error across 3 cycles
Cumulative error across 4 cycles
Cumulative error across 5 cycles
Cumulative error across 6 cycles
Cumulative error across 7 cycles
Cumulative error across 8 cycles
Cumulative error across 9 cycles
Cumulative error across 10 cycles
Cumulative error across 11 cycles
Cumulative error across 12 cycles
tJIT(cc, lck)
tERR(2per)
tERR(3per)
tERR(4per)
tERR(5per)
tERR(6per)
tERR(7per)
tERR(8per)
tERR(9per)
tERR(10per)
tERR(11per)
tERR(12per)
ps
- 132
- 157
- 175
- 188
- 200
- 209
- 217
- 224
- 231
- 237
- 242
132
157
175
188
200
209
217
224
231
237
242
- 118
- 140
- 155
- 168
- 177
- 186
- 193
- 200
- 205
- 210
- 215
118
140
155
168
177
186
193
200
205
210
215
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
ps
24
Absolute clock HIGH pulse width
tCH(abs)
tCL(abs)
0.43
0.43
-
-
0.43
0.43
-
-
tCK(avg)
tCK(avg)
25
26
Absolute clock Low pulse width
Data Timing
DQS,DQS to DQ skew, per group, per access
DQ output hold time from DQS, DQS
DQ low-impedance time from CK, CK
DQ high-impedance time from CK, CK
Data setup time to DQS, DQS referenced to V (AC)V (AC) levels
tDQSQ
tQH
-
150
-
-
125
-
ps
tCK(avg)
ps
13
0.38
-600
-
0.38
-500
-
13, g
tLZ(DQ)
tHZ(DQ)
tDS(base)
300
300
-
250
250
-
13,14, f
13,14, f
d, 17
ps
25
30
ps
IH
IL
Data hold time to DQS, DQS referenced to V (AC)V (AC) levels
tDH(base)
tDIPW
100
490
65
-
ps
ps
d, 17
28
-
-
IH
IL
DQ and DM Input pulse width for each input
Data Strobe Timing
400
-
DQS, DQS READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS output high time
tRPRE
tRPST
tQSH
0.9
0.3
Note 19
0.9
0.3
Note 19
tCK
tCK
13, 19, g
11, 13, b
13, g
Note 11
Note 11
0.38
0.38
0.9
-
-
0.4
-
-
tCK(avg)
tCK(avg)
tCK
DQS, DQS output low time
tQSL
0.4
13, g
DQS, DQS WRITE Preamble
DQS, DQS WRITE Postamble
tWPRE
tWPST
tDQSCK
tLZ(DQS)
tHZ(DQS)
tDQSL
tDQSH
tDQSS
tDSS
-
0.9
-
0.3
-
0.3
-
tCK
DQS, DQS rising edge output access time from rising CK, CK
DQS, DQS low-impedance time (Referenced from RL-1)
DQS, DQS high-impedance time (Referenced from RL+BL/2)
DQS, DQS differential input low pulse width
-300
-600
-
300
300
300
0.55
0.55
0.25
-
-255
-500
-
255
250
250
0.55
0.55
0.25
-
ps
13,f
13,14,f
12,13,14
29, 31
30, 31
c
ps
ps
0.45
0.45
-0.25
0.2
0.45
0.45
-0.25
0.2
tCK
DQS, DQS differential input high pulse width
tCK
DQS, DQS rising edge to CK, CK rising edge
tCK(avg)
tCK(avg)
tCK(avg)
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
c, 32
tDSH
0.2
-
0.2
-
c, 32
32 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Speed
Parameter
DDR3-1066
DDR3-1333
Units
Note
Symbol
MIN
MAX
MIN
MAX
Command and Address Timing
DLL locking time
tDLLK
tRTP
512
-
-
512
-
-
nCK
max
max
internal READ Command to PRECHARGE Command delay
e
(4nCK,7.5ns)
(4nCK,7.5ns)
max
max
Delay from start of internal write transaction to internal read command
tWTR
-
-
e,18
e
(4nCK,7.5ns)
(4nCK,7.5ns)
WRITE recovery time
tWR
15
4
-
-
15
4
-
-
ns
Mode Register Set command cycle time
tMRD
nCK
max
max
Mode Register Set command update delay
tMOD
-
-
-
(12nCK,15ns)
(12nCK,15ns)
CAS# to CAS# command delay
tCCD
tDAL(min)
tMPRR
tRAS
4
-
4
nCK
nCK
nCK
ns
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
WR + roundup (tRP / tCK(AVG))
1
-
1
-
22
e
See " Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin"
max
max
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRD
-
-
-
-
e
e
(4nCK,7.5ns)
(4nCK,6ns)
max
max
(4nCK,10ns)
(4nCK,7.5ns)
Four activate window for 1KB page size
Four activate window for 2KB page size
tFAW
tFAW
37.5
50
-
-
-
30
45
65
-
-
-
ns
ns
ps
e
e
Command and Address setup time to CK, CK referenced to V (AC) / V (AC) levels tIS(base)
125
b,16
IH
IL
Command and Address hold time from CK, CK referenced to V (AC) / V (AC) lev-
IH
IL
tIH(base)
200
140
-
ps
b,16
-
els
tIS(base)
AC150
Command and Address setup time to CK, CK referenced to V (AC) / V (AC) levels
125 + 150
780
65+125
620
-
-
ps
ps
b,16,27
28
-
-
IH
IL
Control & Address Input pulse width for each input
Calibration Timing
tIPW
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
Reset Timing
tZQinitI
tZQoper
tZQCS
512
256
64
-
-
-
512
256
64
-
-
-
nCK
nCK
nCK
23
max(5nCK, tRFC +
10ns)
max(5nCK, tRFC +
10ns)
Exit Reset from CKE HIGH to a valid command
Self Refresh Timing
tXPR
-
-
max(5nCK,tRFC +
10ns)
max(5nCK,tRFC +
10ns)
Exit Self Refresh to commands not requiring a locked DLL
tXS
-
-
Exit Self Refresh to commands requiring a locked DLL
Minimum CKE low width for Self refresh entry to exit timing
tXSDLL
tCKESR
tDLLK(min)
-
-
tDLLK(min)
-
-
nCK
tCKE(min) + 1tCK
tCKE(min) + 1tCK
max(5nCK,
10ns)
max(5nCK,
10ns)
Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) tCKSRE
-
-
-
-
Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX)
max(5nCK,
10ns)
max(5nCK,
10ns)
tCKSRX
or Reset Exit
33 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Speed
Parameter
DDR3-1066
DDR3-1333
Units
Note
Symbol
MIN
MAX
MIN
MAX
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Precharge Power
Down with DLL
max
max
tXP
tXPDLL
tCKE
(3nCK,
7.5ns)
-
-
-
-
-
-
(3nCK,6ns)
frozen to commands not requiring a locked DLL
max
(10nCK,
24ns)
max
(10nCK,
24ns)
Exit Precharge Power Down with DLL frozen to commands requiring a locked
DLL
2
max
max
CKE minimum pulse width
(3nCK,
5.625ns)
(3nCK,
5.625ns)
Command pass disable delay
tCPDED
tPD
1
-
1
-
nCK
tCK
Power Down Entry to Exit Timing
tCKE(min)
9*tREFI
tCKE(min)
9*tREFI
15
20
20
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
tACTPDEN
tPRPDEN
tRDPDEN
1
1
-
-
-
1
1
-
-
-
nCK
nCK
RL + 4 +1
RL + 4 +1
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
WL + 4 +(tWR/
tCK(avg))
WL + 4 +(tWR/
tCK(avg))
tWRPDEN
tWRAPDEN
tWRPDEN
tWRAPDEN
-
-
-
-
-
-
-
-
nCK
nCK
nCK
nCK
9
10
9
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
WL + 4 +WR +1
WL + 4 +WR +1
Timing of WR command to Power Down entry
(BL4MRS)
WL + 2 +(tWR/
tCK(avg))
WL + 2 +(tWR/
tCK(avg))
Timing of WRA command to Power Down entry
(BL4MRS)
WL +2 +WR +1
WL +2 +WR +1
10
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT Timing
tREFPDEN
tMRSPDEN
1
-
-
1
-
-
20,21
tMOD(min)
tMOD(min)
ODT high time without write command or with write command and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with DLL frozen)
Asynchronous RTT turn-off delay (Power-Down with DLL frozen)
ODT turn-on
ODTH4
ODTH8
tAONPD
tAOFPD
tAON
4
6
-
4
6
-
nCK
nCK
-
-
2
8.5
8.5
300
0.7
0.7
2
8.5
8.5
250
0.7
0.7
ns
2
2
ns
-300
0.3
0.3
-250
0.3
0.3
ps
7,f
8,f
f
RTT_NOM and RTT_WR turn-off time from ODTLoff reference
RTT dynamic change skew
tAOF
tCK(avg)
tCK(avg)
tADC
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining mode is programmed
DQS/DQS delay after tDQS margining mode is programmed
Setup time for tDQSS latch
tWLMRD
tWLDQSEN
tWLS
40
25
-
-
-
40
25
-
-
-
tCK
tCK
ps
3
3
245
195
Write leveling hold time from rising DQS, DQS crossing to rising CK, CK cross-
ing
tWLH
245
-
195
-
ps
Write leveling output delay
Write leveling output error
tWLO
0
0
9
2
0
0
9
2
ns
ns
tWLOE
34 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
17.1 Jitter Notes
Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input
clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another
Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Specific Note b These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge
to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per),
tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these param-
eters should be met whether clock jitter is present or not.
Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)) crossing to its respective clock signal (CK, CK) cross-
ing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the
clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.
Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe
signal (DQS(L/U), DQS(L/U)) crossing. Specific Note e For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] =
RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the
device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For
DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifi-
cations are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to
input clock jitter.
Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock,
where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)
For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps,
then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) =
tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) =
- 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!)
Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=
12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.
Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (out-
put deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act =
2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9
x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min =
0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/max usage!)
35 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
17.2 Timing Parameter Notes
1. Actual value dependant upon measurement level definitions which are TBD.
2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
3. The max values are system dependent.
4. WR as programmed in mode register
5. Value must be rounded-up to next higher integer value
6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
7. For definition of RTT turn-on time tAON see "Device Operation"
8. For definition of RTT turn-off time tAOF see "Device Operation".
9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
10. WR in clock cycles as programmed in MR0
11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See Device Operation Datasheet
12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated
by TBD
13. Value is valid for RON34
14. Single ended signal parameter.
15. tREFI depends on T
OPER
16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,
V
(DC) = V DQ(DC). FOr input only pins except RESET, V (DC)=V CA(DC).
REF
REF
REF
REF
See "Address/ Command Setup, Hold and Derating"
17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,
V
(DC)= V
DQ(DC). For input only pins except RESET, V
(DC)=V
CA(DC).
REF
REF
REF
REF
See "Data Setup, Hold and Slew Rate Derating".
18. Start of internal write transaction is defined as follows ;
For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.
For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL
For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL
19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation"
20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down
IDD spec will not be applied until finishing those operations.
21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time
such as tXPDLL(min) is also required. See "Device Operation".
22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming
the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The
appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-
ject to in the application, is illustrated. The interval could be defined by the following formula:
ZQCorrection
(TSens x Tdriftrate) + (VSens x Vdriftrate)
where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.
For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-
lated as:
0.5
~
~
= 0.133
128ms
(1.5 x 1) + (0.15 x 15)
24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.
26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.
27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter-
nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns].
28. Pulse width of a input signal is defined as the width between the first crossing of V
(DC) and the consecutive crossing of V
(DC)
REF
REF
29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.
30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.
31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.
36 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
17.3 Address / Command Setup, Hold and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value to the ∆tIS
and ∆tIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
REF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate
line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line any-
where between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ’dc to VREF(DC) region’, use nominal slew rate for derating value (see
Figure 9). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line
to the actual signal from the dc level to VREF(DC) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in Table below, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
ADD/CMD Setup and Hold Base-Values for 1V/ns
[ps]
tIS(base)
DDR3-1066
125
DDR3-1333
65
reference
VIH/L(AC)
VIH/L(DC)
VIH/L(AC)
tIH(base)
200
140
tIS(base)-AC150
125 + 150
65+125
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate
Note : The tIS(base)-AC150 specifications are further adjusted to add an additional 100ps of derating to accommodate for the lower alternate thresh-old
of 150mV and another 25ps to account for the earlier reference point [(175mv-150mV)/1 V/ns].
Derating values DDR3-1066/1333 tIS/tIH-ac/dc based
∆tIS, ∆tIH Derating [ps] AC/DC based
AC175 Threshold -> VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV
CLK,CLK Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
∆tIS
1.0V/ns
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
58
42
8
∆tIS
∆tIH
66
50
16
12
6
∆tIS
∆tIH
74
58
24
20
14
8
∆tIH
84
68
34
30
24
18
8
∆tIS
∆tIH
100
84
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
0
88
59
0
88
59
0
96
67
8
104
75
16
14
10
5
112
83
24
20
13
13
7
120
91
32
30
26
21
15
-2
128
99
40
38
34
29
23
5
34
34
34
0
0
0
50
CMD/
ADD
Slew
rate
-2
-4
-2
-4
-2
-4
6
4
46
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
2
-2
40
-11
-17
-35
-62
-11
-17
-35
-62
-11
-17
-35
-62
-3
-9
-27
-54
-8
0
34
V/ns
-18
-32
-52
-1
-10
-24
-44
-2
24
-19
-46
-11
-38
-16
-36
-6
10
-30
-26
-22
-10
37 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Derating values DDR3-1333/1600 tIS/tIH-ac/dc based - Alternate AC150 Threshold
∆tIS, ∆tIH Derating [ps] AC/DC based
Alternate AC150 Threshold -> VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV
CLK,CLK Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
1.2V/ns
∆tIS
1.0V/ns
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
58
42
8
∆tIS
∆tIH
66
50
16
12
6
∆tIS
∆tIH
74
58
24
20
14
8
∆tIH
84
68
34
30
24
18
8
∆tIS
∆tIH
100
84
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
75
50
0
75
50
0
75
50
0
83
58
8
91
66
16
16
16
16
15
6
99
74
24
24
24
24
23
14
-1
107
82
32
32
32
32
31
22
7
115
90
40
40
40
40
39
30
15
34
34
34
0
0
0
50
CMD/
ADD
Slew
rate
0
-4
0
-4
0
-4
8
4
46
0
-10
-16
-26
-40
-60
0
-10
-16
-26
-40
-60
0
-10
-16
-26
-40
-60
8
-2
40
0
0
0
8
-8
0
34
V/ns
-1
-10
-25
-1
-10
-25
-1
-10
-25
7
-18
-32
-52
-10
-24
-44
-2
24
-2
-17
-16
-36
-6
10
-9
-26
-10
Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition
tVAC @175mV [ps]
Slew Rate[V/ns]
tVAC @150mV [ps]
min
max
min
175
170
167
163
162
161
159
155
150
150
max
>2.0
2.0
75
57
50
38
34
29
22
13
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.5
1.0
0.9
0.8
0.7
0.6
0.5
< 0.5
0
38 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
VIH(AC) min
VREF to ac
region
VIH(DC) min
nominal
slew rate
VREF(DC)
nominal slew
rate
VIL(DC) max
VREF to ac
region
VIL(AC) max
VSS
tVAC
Delta TF
Delta TR
Setup Slew Rate
Rising Signal
V
IH(AC)min - VREF(DC)
Delta TR
V
REF(DC) - VIL(AC)max
Delta TF
Setup Slew Rate
=
=
Falling Signal
Figure 9 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
39 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
VIH(DC) min
dc to VREF
region
nominal
slew rate
VREF(DC)
nominal
dc to VREF
region
dc to VREF
region
slew rate
VIL(DC) max
VIL(AC) max
VSS
Delta TF
Delta TR
Hold Slew Rate
Hold Slew Rate
Rising Signal
V
REF(DC) - VIL(DC)max
Delta TR
V
IH(DC)min - VREF(DC)
Delta TF
=
=
Falling Signal
Figure 10 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
40 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
nominal
line
VIH(AC) min
V
REF to ac
region
V
IH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VIL(AC) max
VREF to ac
region
nominal
line
Delta TR
VSS
tangent line[VIH(AC)min - VREF(DC)]
Delta TR
Setup Slew Rate
=
Rising Signal
Delta TF
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max]
=
Falling Signal
Delta TF
Figure 11. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
41 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
nominal
line
V
IH(DC) min
dc to VREF
region
tangent
line
VREF(DC)
tangent
line
dc to VREF
region
nominal
line
VIL(DC) max
VIL(AC) max
VSS
Delta TF
Delta TR
tangent line [ VREF(DC) - VIL(DC)max ]
Delta TR
Hold Slew Rate
=
Rising Signal
tangent line [ VIH(DC)min - VREF(DC) ]
Delta TF
Hold Slew Rate
=
Falling Signal
Figure 12 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock)
42 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
17.4 Data Setup, Hold and Slew Rate Derating:
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value to the ∆
tDS and ∆tDH derating value respectively. Example: tDS (total setup time) = tDS(base) + ∆tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min.
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If
the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value. If the
actual signal is later than the nominal slew rate line anywhere
between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(DC) region’, use nominal slew rate for derating value. If
the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to the actual
signal from the dc level to VREF(DC) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization
Data Setup and Hold Base-Value
[ps]
tDS(base)
tDH(base)
DDR3-1066
DDR3-1333
reference
VIH/L(AC)
VIH/L(DC)
25
30
65
100
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
Derating values DDR3-1066/1333 tIS/tIH-ac/dc based
∆tDS, ∆tDH Derating [ps] AC/DC baseda
DQS,DQS Differential Slew Rate
1.8 V/ns 1.6 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.4V/ns
1.2V/ns
1.0V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
0
-
50
34
0
-
88
59
0
-2
-
50
34
0
-4
-
88
59
0
50
34
0
-
67
8
6
2
-3
-
-
42
8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16
14
10
5
16
12
6
-
-
-
-
DDR3 DQ
-2
-6
-
-4
-10
-
4
22
18
13
7
20
14
8
-
-
-
-
-
-
-
Slew
-
-
-2
-8
-
26
21
15
-2
-30
-
24
18
8
800/ rate
1066 V/ns
-
-
-
-
0
29
23
6
34
24
10
-10
-
-
-
-
-
-
-
-1
-
-10
-
-2
-16
-
-
-
-
-
-
-
-
-
-11
-
-6
-26
-
-
-
-
-
-
-
-
-
-
-
-
-22
-
75
50
0
-
50
34
0
-
75
50
0
0
-
50
34
0
-4
-
75
50
0
50
34
0
-
-
-
-
-
58
8
8
8
8
-
42
8
-
-
-
-
-
-
-
-
16
16
16
16
15
-
16
12
6
-
-
-
-
-
-
-
DDR3 DQ
0
-4
-10
-
4
24
24
24
23
14
-
20
14
8
-2
-16
-
-
-
-
-
Slew
-
-
0
-2
-8
-
32
32
31
22
7
24
18
8
-6
-26
-
-
1333/ rate
1600 V/ns
-
-
-
-
-
0
40
39
30
15
34
24
10
-10
-
-
-
-
-
-
-10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note : a. Cell contents shaded in red are defined as ’not supported’.
Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition
tVAC[ps] DDR3-1066
tVAC[ps] DDR3-1333
Slew Rate[V/ns]
min
75
57
50
38
34
29
22
13
0
max
min
max
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
-
-
-
-
-
-
-
-
-
-
175
170
167
163
162
161
159
155
155
150
-
-
-
-
-
-
-
-
-
-
0
43 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
VIH(AC) min
VREF to ac
region
VIH(DC) min
nominal
slew rate
VREF(DC)
nominal slew
rate
VIL(DC) max
VREF to ac
region
VIL(AC) max
VSS
tVAC
Delta TF
Delta TR
Setup Slew Rate VIH(AC)min - VREF(DC)
V
REF(DC) - VIL(AC)max
Delta TF
Setup Slew Rate
=
=
Rising Signal
Delta TR
Falling Signal
Figure 13 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
44 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
V
IH(DC) min
dc to VREF
region
nominal
slew rate
VREF(DC)
nominal
dc to VREF
region
dc to VREF
region
slew rate
VIL(DC) max
VIL(AC) max
VSS
Delta TF
Delta TR
V
REF(DC) - VIL(DC)max
Delta TR
VIH(DC)min - VREF(DC)
Delta TF
Hold Slew Rate
Rising Signal
Hold Slew Rate
Falling Signal
=
=
Figure 14 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
45 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
nominal
line
VIH(AC) min
V
REF to ac
region
V
IH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VIL(AC) max
VREF to ac
region
nominal
line
Delta TR
VSS
tangent line[VIH(AC)min - VREF(DC)]
Delta TR
Setup Slew Rate
=
Rising Signal
Delta TF
tangent line[VREF(DC) - VIL(AC)max]
Delta TF
Setup Slew Rate
=
Falling Signal
Figure 15 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
46 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
Note :Clock and Strobe are drawn on a different time scale.
CK
tIH
tIH
tIS
tIS
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
nominal
line
V
IH(DC) min
dc to VREF
region
tangent
line
VREF(DC)
tangent
line
dc to VREF
region
nominal
line
VIL(DC) max
VIL(AC) max
VSS
Delta TF
Delta TR
tangent line [ VREF(DC) - VIL(DC)max ]
Delta TR
Hold Slew Rate
=
Rising Signal
tangent line [ VIH(DC)min - VREF(DC) ]
Delta TF
Hold Slew Rate
=
Falling Signal
Figure 16 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock)
47 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
18.0 Physical Dimensions
18.1 64Mbx16 based 64Mx64 Module (1 Rank)
Units : Millimeters
133.35 ± 0.15
128.95
SPD
(2)
2.50
54.675
A
B
47.00
71.00
Max 4.00
1.270 ± 0.10
5.00
2x 2.10 ± 0.15
0.80 ± 0.05
0.2 ± 0.15
3.80
1.50±0.10
1.00
2.50
Detail A
Detail B
The used device is 64M x16 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G1646D-HC∗∗
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
48 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
18.2 128Mbx8 based 128Mx64/x72 Module (1 Rank)
Units : Millimeters
133.35 ± 0.15
128.95
N/A
(for x64)
SPD
ECC
(for x72)
(2)
2.50
54.675
A
B
47.00
71.00
Max 4.00
1.270 ± 0.10
5.00
2x 2.10 ± 0.15
0.80 ± 0.05
0.2 ± 0.15
3.80
1.50±0.10
1.00
2.50
Detail A
Detail B
The used device is 128M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G0846D-HC∗∗
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
49 of 50
Rev. 1.23 July 2009
DDR3 SDRAM
Unbuffered DIMM
18.3 128Mbx8 based 256Mx64/x72 Module (2 Ranks)
Units : Millimeters
133.35 ± 0.15
128.95
N/A
(for x64)
SPD
ECC
(for x72)
(2)
2.50
54.675
A
B
Max 4.00
47.00
71.00
N/A
(for x64)
ECC
(for x72)
1.270 ± 0.10
5.00
2x 2.10 ± 0.15
0.80 ± 0.05
0.2 ± 0.15
3.80
1.50±0.10
1.00
2.50
Detail A
Detail B
The used device is 128M x8 DDR3 SDRAM, FBGA.
DDR3 SDRAM Part NO : K4B1G0846D-HC∗∗
* Note : Tolerances on all dimensions ±0.15 unless otherwise specified.
50 of 50
Rev. 1.23 July 2009
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