M392B5270DH0-CH9_技术文档

Rev. 1.3, Jul. 2011

M392B5773DH0

M392B5273DH0

M392B5270DH0

M392B1K70DM0

M392B1K73DM0

240pin VLP Registered DIMM

based on 2Gb D-die

78FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

datasheet

SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND

SPECIFICATIONS WITHOUT NOTICE.

Products and specifications discussed herein are for reference purposes only. All information discussed

herein is provided on an "AS IS" basis, without warranties of any kind.

This document and all information discussed herein remain the sole and exclusive property of Samsung

Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property

right is granted by one party to the other party under this document, by implication, estoppel or other-

wise.

Samsung products are not intended for use in life support, critical care, medical, safety equipment, or

similar applications where product failure could result in loss of life or personal or physical harm, or any

military or defense application, or any governmental procurement to which special terms or provisions

may apply.

For updates or additional information about Samsung products, contact your nearest Samsung office.

All brand names, trademarks and registered trademarks belong to their respective owners.

- 1 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

Revision History

Revision No.

History

Draft Date

Sep. 2010

Nov. 2010

Jan. 2011

May. 2011

Jul. 2011

Remark

Editor

S.H.Kim

J.Y.Lee

1.0

1.1

- First SPEC. Release

-

- Changed Input/Output capacitance on page 29.

- Changed 1866 speed bin table on page 33.

- Corrected Typo

1.2

1.21

1.22

1.23

1.3

- Corrected Typo

- Changed timing parameters(Setup/Hold time)

Jul. 2011

- 2 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

1. DDR3 VLP Registered DIMM Ordering Information

Number of

Height

Part Number²

Density

Organization

Component Composition

Rank

M392B5773DH0-CF8/H9/K0/MA

M392B5273DH0-CF8/H9/K0/MA

M392B5270DH0-CF8/H9/K0/MA

M392B1K70DM0-CF8/H9/K0/MA

M392B1K73DM0-CF8/H9

2GB

4GB

8GB

256Mx72

512Mx72

1Gx72

256Mx8(K4B2G0846D-HC##)*9

256Mx8(K4B2G0846D-HC##)*18

512Mx4(K4B2G0446D-HC##)*18

DDP 1Gx4(K4B4G0446D-MC##)*18

DDP 512Mx8(K4B4G0846D-MC##)*18

1

2

1

2

4

18.75mm

1Gx72

NOTE :

1. "##" - F8/H9/K0/MA

2. F8 - 1066Mbps 7-7-7 / H9 - 1333Mbps 9-9-9 / K0 - 1600Mbps 11-11-11 / MA - 1866Mbps 13-13-13

- DDR3-1866(13-13-13) is backward compatible to DDR3-1600(11-11-11), DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1600(11-11-11) is backward compatible to DDR3-1333(9-9-9), DDR3-1066(7-7-7)

- DDR3-1333(9-9-9) is backward compatible to DDR3-1066(7-7-7)

2. Key Features

DDR3-800

6-6-6

2.5

DDR3-1066

7-7-7

DDR3-1333

9-9-9

1.5

DDR3-1600

11-11-11

1.25

DDR3-1866

13-13-13

1.07

Speed

Unit

tCK(min)

CAS Latency

tRCD(min)

tRP(min)

1.875

7

ns

nCK

ns

6

9

11

13

15

13.125

37.5

13.5

36

13.75

35

13.91

34

15

ns

tRAS(min)

tRC(min)

37.5

52.5

ns

50.625

49.5

48.75

47.91

ns

•

JEDEC standard 1.5V ± 0.075V Power Supply

V_DDQ= 1.5V ± 0.075V

•

400MHz f_CKfor 800Mb/sec/pin, 533MHz f_CKfor 1066Mb/sec/pin, 667MHz f_CKfor 1333Mb/sec/pin, 800MHz f_CKfor 1600Mb/sec/pin,

933MHz f_CKfor 1866Mb/sec/pin

•

8 independent internal bank

Programmable CAS Latency: 6,7,8,9,10,11,13

Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock

Programmable CAS Write Latency(CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600) and 9 (DDR3-1866)

Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or

write [either On the fly using A12 or MRS]

•

Bi-directional Differential Data Strobe

On Die Termination using ODT pin

Average Refresh Period 7.8us at lower then T_CASE85°C, 3.9us at 85°C < T_CASE≤ 95°C

•

Asynchronous Reset

3. Address Configuration

Organization

Row Address

A0-A14

Column Address

A0-A9, A11

A0-A9

Bank Address

BA0-BA2

Auto Precharge

A10/AP

512Mx4(2Gb) based Module

256Mx8(2Gb) based Module

1Gx4(4Gb DDP) based Module

512Mx8(4Gb DDP) based Module

A0-A14

BA0-BA2

A10/AP

A0-A14

A0-A9, A11

A0-A9

BA0-BA2

A10/AP

A0-A14

BA0-BA2

A10/AP

- 5 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

4. Registered DIMM Pin Configurations (Front side/Back side)

Front

Back

Front

Back

Front

Back

NC,DQS17

,TDQS17

V

1

121

42

DQS8

162

82

DQ33

202

REFDQ

SS

DM4,DQS13

,TDQS13

NC,DQS13

V

2

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

DQ4

DQ5

43

44

45

46

47

48

DQS8

163

164

165

166

167

168

83

84

203

204

205

206

207

208

209

210

211

212

213

214

215

216

217

218

219

220

221

222

223

224

225

226

227

228

229

230

231

232

233

234

235

236

237

238

239

240

SS

V

3

DQ0

DQ1

CB6,NC

CB7,NC

DQS4

SS

,TDQS13

V

4

CB2,NC

CB3,NC

85

SS

DM0,DQS9

,TDQS9

NC,DQS9

V

5

86

DQ38

DQ39

SS

V

6

DQS0

NC(TEST)

RESET

87

DQ34

DQ35

SS

,TDQS9

V

, NC

V

7

88

SS

TT

SS

V

8

DQ6

DQ7

KEY

89

DQ44

DQ45

SS

V

, NC

9

DQ2

DQ3

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

CKE1, NC

90

DQ40

DQ41

TT

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

CKE0

91

SS

DD

SS

DM5,DQS14

,TDQS14

NC,DQS14

V

DQ12

DQ13

NC

92

SS

DD

SS

DQ8

DQ9

BA2

A14

93

DQS5

,TDQS14

V

Err_Out/NC

94

SS

DD

SS

DM1,DQS10

,TDQS10

NC,DQS10

V

A12/BC

A9

95

DQ46

DQ47

SS

DD

SS

DQS1

A11

A7

96

DQ42

DQ43

,TDQS10

V

97

SS

DD

SS

V

DQ14

DQ15

A8

A6

98

DQ52

DQ53

SS

DD

SS

DQ10

DQ11

A5

A4

99

DQ48

DQ49

V

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

SS

DD

SS

DM6,DQS15

,TDQS15

NC,DQS15

V

DQ20

DQ21

A3

A1

SS

DD

SS

DQ16

DQ17

A2

DQS6

,TDQS15

V

SS

DD

SS

DM2,DQS11

,TDQS11

NC,DQS11

V

NC, CK1

DQ54

DQ55

SS

DD

SS

DQS2

CK0

DQ50

DQ51

,TDQS11

V

SS

DD

SS

V

DQ22

DQ23

DQ60

DQ61

SS

DD

SS

V

DQ18

DQ19

EVENT,NC

A0

DQ56

DQ57

REFCA

V

NC/Par_In

SS

DM7/DQS16

TDQS16

DM7,DQS16

,TDQS16

V

DQ28

DQ29

SS

DD

SS

DQ24

DQ25

A10/AP

BA0

BA1

DQS7

V

SS

DD

SS

DM3,DQS12

,TDQS12

NC,DQS12

V

RAS

S0

DQ62

DQ63

SS

DD

SS

DQS3

WE

DQ58

DQ59

,TDQS12

V

CAS

SS

DD

SS

V

DQ30

DQ31

ODT0

A13

SS

DD

SS

DDSPD

DQ26

DQ27

S1,NC

SA0

SCL

SA2

SA1

SDA

V

ODT1,NC

SS

DD

V

CB4,NC

CB5,NC

S3,NC

SS

DD

SS

V

CB0,NC

CB1,NC

S2,NC

SS

TT

V

DQ36

DQ37

SS

DM8,DQS17

TDQS17,NC

V

DQ32

SS

NOTE : NC = No internal Connection

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

- 6 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

5. Pin Description

Pin Name

Description

Clock Input, positive line

Clock Input, negative line

Number

Pin Name

ODT[1:0]

DQ[63:0]

CB[7:0]

Description

On Die Termination Inputs

Data Input/Output

Number

CK0

1

2

1

2

64

8

CKE[1:0]

RAS

Clock Enables

Data check bits Input/Output

Data strobes

Row Address Strobe

Column Address Strobe

DQS[8:0]

9

CAS

Data strobes, negative line

9

DM[8:0]/

DQS[17:9]

TDQS[17:9]

Data Masks/ Data strobes,

Termination data strobes

WE

Write Enable

1

9

DQS[17:9] Data strobes, negative line, Termination data

TDQS[17:9] strobes

S[3:0]

Chip Selects

4

2\14

1

9

2

1

A[9:0],A11,

A[15:13]

Address Inputs

RFU

EVENT

TEST

Reserved for Future Use

Reserved for optional hardware temperature

sensing

A10/AP

A12/BC

Address Input/Autoprecharge

Address Input/Burst chop

Memory bus test toll (Not Connected and Not

Usable on DIMMs)

1

BA[2:0]

SCL

SDRAM Bank Addresses

3

1

3

1

RESET

V_DD

Register and SDRAM control pin

Power Supply

1

22

59

1

Serial Presence Detect (SPD) Clock Input

SPD Data Input/Output

V_SS

SDA

Ground

V_REFDQ

V_REFCA

SA[2:0]

Par_In

SPD Address Inputs

Reference Voltage for DQ

Reference Voltage for CA

Parity bit for the Address and Control bus

1

Parity error found on the Address and Control

bus

V_TT

Err_Out

1

Termination Voltage

4

V_DDSPD

SPD Power

Total

1

240

NOTE :

*The V and V

pins are tied common to a single power-plane on these designs.

DDQ

DD

6. ON DIMM Thermal Sensor

SCL

SDA

EVENT

WP/EVENT

SA0

R1

SA1

SA2

0 Ω

R2

0 Ω

SA0

NOTE : 1. All Samsung RDIMM support Thermal sensor on DIMM

2. When the SPD and the thermal sensor are placed on the module, R1 is placed but R2 is not.

When only the SPD is placed on the module, R2 is placed but R1 is not.

[ Table 1 ] Temperature Sensor Characteristics

Temperature Sensor Accuracy

Grade

Range

Units

NOTE

Min.

Typ.

+/- 0.5

+/- 1.0

+/- 2.0

0.25

Max.

+/- 1.0

+/- 2.0

+/- 3.0

75 < Ta < 95

40 < Ta < 125

-20 < Ta < 125

-

B

°C

Resolution

°C /LSB

- 7 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

7. Input/Output Functional Description

Symbol

Type

Polarity

Function

Positive

Edge

CK0

Input

Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver.

Negative

Edge

CK0

Input

Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.

CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers

CKE[1:0]

Active High and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN

and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank)

Enables the associated SDRAM command decoder when low and disables decoder when high.

When decoder is disabled, new commands are ignored and previous operations continue.

These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both

inputs are high. When both S[1:0] are high, all register outputs (except CKE, ODT and Chip select) remain in

S[3:0]

Input

Active Low

the previous state. For modules supporting 4 ranks, S[3:2] operate similarly to S[1:0] for a second set of reg-

ister outputs.

ODT[1:0]

Input

Active High On-Die Termination control signals

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be exe-

RAS, CAS, WE

Active Low

cuted by the SDRAM.

V_REFDQ

V_REFCA

Supply

Reference voltage for DQ0-DQ63 and CB0-CB7

Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1.

Selects which SDRAM bank of eight is activated.

BA[2:0]

Input

BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank

address also determines mode register is to be accessed during an MRS cycle.

Provided the row address for Active commands and the column address and Auto Precharge bit for Read/

Write commands to select one location out of the memory array in the respective bank. A10 is sampled dur-

ing a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks

(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL 4/8

identification for "BL on the fly" during CAS command. The address inputs also provide the op-code during

Mode Register Set commands.

A[15:13,

12/BC,11,

10/AP,9:0]

Input

I/O

DQ[63:0],

CB[7:0]

Data and Check Bit Input/Output pins

Active High Masks write data when high, issued concurrently with input data.

V

_DD, V_SSSupply Power and ground for the DDR SDRAM input buffers and core logic.

DM[8:0]

V

_TTSupply Termination Voltage for Address/Command/Control/Clock nets.

DQS[17:0]

I/O

Positive Edge Positive line of the differential data strobe for input and output data.

Negative Edge Negative line of the differential data strobe for input and output data.

TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will

enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When dis-

abled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.

X4/X16 DRAMs must disable the TDQS function via mode register A11=0 in MR1

TDQS[17:9],

TDQS[17:9]

OUT

These signals are tied at the system planar to either V_SSor V_DDSPDto configure the serial SPD EEPROM

address range.

SA[2:0]

SDA

IN

I/O

IN

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be

connected from the SDA bus line to V_DDSPDon the system planar to act as a pull-up.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected

from the SCL bus time to V_DDSPDon the system planar to act as a pull-up.

SCL

OUT

(open

drain)

This signal indicates that a thermal event has been detected in the thermal sensing device.The system

should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part.

EVENT

V_DDSPD

Active Low

Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from

3.0 Volt to 3.6 Volt (nominal 3.3V) operation.

Supply

The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When

low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set

to low level (the Clock Driver will remain synchronized with the input clock)

RESET

Par_In

Err_Out

TEST

IN

Parity bit for the Address and Control bus. ("1 " : Odd, "0 ": Even)

OUT

(open

drain)

Parity error detected on the Address and Control bus. A resistor may be connected from Err_Out

bus line to V_DDon the system planar to act as a pull up.

Used by memory bus analysis tools (unused (NC) on memory DIMMs)

- 8 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

8. Pinout Comparison Based On Module Type

RDIMM

UDIMM

Signal

NOTE

Signal

NOTE

Additional connection for Termination Voltage for

Address/Command/Control/Clock nets.

V_TT

48, 49

120, 240

53

NC

Not used on UDIMMs

Termination Voltage for Address/Command/Con-

trol/Clock nets.

Termination Voltage for Address/Command/Con-

trol/Clock nets.

V_TT

NC

Connected to the register on all RDIMMs NC Not

used on UDIMMs

Err_Out

NC Not used on UDIMMs

63

64

68

NC

CK1

NC

Used for 2 rank UDIMMs, not used on single-rank

UDIMMs, but terminated

Not used on RDIMMs

Par_In

Connected to the register on all RDIMMs

Not used on RDIMMs

Used for dual-rank UDIMMs, not connected

on single-rank UDIMMs

76

77

S1

Connected to the register on dual- and quadrank

RDIMMs; NC on single-rank RDIMMs

Used for dual-rank UDIMMs, not connected

on single-rank UDIMMs

ODT1, NC

ODT1,NC

Connected to the register on quad-rank

RDIMMs, not connected on single or dual rank

RDIMMs

79

S2, NC

NC

Not used on UDIMMs

TEST input used only on bus analysis

probes

167

169

NC

TEST input used only on bus analysis probes

Connected to the register on dual- and quadrank

RDIMMs; NC on single-rank RDIMMs

CKE1,

NC

Used for dual-rank UDIMMs, not connected

on single-rank UDIMMs

CKE1

171

172

196

A15

A14

A13

A15, NC

A14

Depending on device density, may not be

connected to SDRAMs on UDIMMs. However,

these signals are terminated on

Connected to the register on all RDIMMs

A13

UDIMMs. A15 not routed on some RCs

Connected to the register on quad-rank

RDIMMs, not connected on single-or dual-rank

RDIMMs

198

S3, NC

CBn

NC

NC, CBn

DMn

Not used on UDIMMs

39, 40, 45, 46,

158, 159, 164,

165

Used on x72 UDIMMs, (n = 0...7); not

used on x64 UDIMMs

Used on all RDIMMs; (n = 0...7)

125, 134, 143,

152, 161, 203,

212, 221, 230

Connected to DM on x8 DRAMs, UDM or

LDM on x16 DRAMs on UDIMMs;

(n = 0...8)

DQSn,

TDQSn

Connected to DQS on x4 SDRAMs,

TDQS on x8 SDRAMs on RDIMMs; (n = 9...17)

126, 135, 144,

153, 162, 204,

213, 222, 231

DQSn,

TDQSn

Connected to DQS on x4 DRAMs, TDQS on x8

SDRAMs on RDIMMs; (n=9...17)

NC

Not used on UDIMMs

Connected to optional thermal sensing compo-

nent.

NC on Modules without a thermal sensing

component.

EVENT

NC

187

NC

NOTE : NC = No internal Connection

- 9 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

9. Registering Clock Driver Specification

9.1 Timing & Capacitance values

T_C= TBD

V_DD= 1.5 ± 0.075V

Symbol

Parameter

Conditions

Units Notes

Min

300

0.4

Max

670

-

fclock

Input Clock Frequency

application frequency

MHz

t_CK

t_CH/t_CL

Pulse duration, CK, CK HIGH or LOW

Inputs active time4 before RESET is taken HIGH

Setup time

DCKE0/1 = LOW and

DCS0/1 = HIGH

t_ACT

t_SU

t_CK

ps

8

-

Input valid before CK/CK

100

175

Input to remain Valid after CK/

CK

t_H

Hold time

t_PDM

Propagation delay, single-bit switching

output disable time(1/2-Clock pre-launch)

output disable time(3/4-Clock pre-launch)

output enable time(1/2-Clock pre-launch)

output enable time(3/4-Clock pre-launch)

Data Input Capacitance

CK/CK to output

0.65

0.5

0.25

-

1.0

-

ns

t_DIS

t_CK

CK/CK to output float

-

0.5

0.25

2.5

t_EN

t_CK

CK/CK to output driving

-

C_IN(DATA)

1.5

C

_IN(CLOCK)

_IN(RST)

Data Input Capacitance

Reset Input Capacitance

2

-

3

pF

C

9.2 Clock driver Characteristics

T_C= TBD

V_DD= 1.5 ± 0.075V

Symbol

Parameter

Conditions

Units Notes

Min

0

Max

40

6

t_jit(cc)

t_STAB

Cycle-to-cycle period jitter

ps

us

ps

Stabilization time

-

t_fdyn

Dynamic phase offset

Clock Output skew

Yn Clock Period jitter

Half period jitter

-50

50

40

t_CKsk

t_jit(per)

t_jit(hper)

-40

-50

-100

-80

50

200

300

200

300

80

Output Inversion enabled

OUtput Inversion disabled

Output Inversion enabled

OUtput Inversion disabled

Qn Output to clock tolerance (Standard 1/2 -Clock

Pre-Launch)

t_Qsk1

ps

t_Qsk1

Output clock tolerance (3/4 Clock Pre-Launch)

Maximum re-driven dynamic clock off-set

ps

t_dynoff

- 10 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

10. Function Block Diagram:

10.1 2GB, 256Mx72 Module (Populated as 1 rank of x8 DDR3 SDRAMs)

ZQ

DQS8

DM8/DQS17

DQS17

DQS4

DM4/DQS13

DQS13

DQS

TDQS

DQ[7:0]

DQS

TDQS

DQ[7:0]

D8

D3

D2

D1

D0

D4

D5

D6

D7

CB[7:0]

DQ[39:32]

Thermal sensor with SPD

DQS3

DM3/DQS12

DQS12

DQS5

DM5/DQS14

DQS14

DQS

TDQS

DQ[7:0]

DQS

TDQS

DQ[7:0]

SCL

SDA

EVENT

A0 A1 A2

DQ[31:24]

DQ[47:40]

SA0 SA1 SA2

DQS2

DM2/DQS11

DQS11

DQS6

DM6/DQS15

DQS15

DQS

TDQS

DQ[7:0]

DQS

TDQS

DQ[7:0]

DQ[23:16]

DQ[55:48]

V

Serial PD

D0 - D8

DDSPD

DD

DQS1

DM1/DQS10

DQS10

DQS7

DM7/DQS16

DQS16

DQS

TDQS

DQ[7:0]

DQS

TDQS

DQ[7:0]

TT

V

D0 - D8

REFCA

REFDQ

SS

DQ[15:8]

DQ[63:56]

Vtt

DQS0

DM0/DQS9

DQS9

DQS

TDQS

DQ[7:0]

NOTE :

DQ[7:0]

1. ZQ resistors are 240 1% For all other resistor values refer to the appropriate wiring

diagram.

Vtt

S0*

S1*

RS0A-> CS0 : SDRAMs D[3:0], D8

RS0B-> CS0 : SDRAMs D[7:4]

BA[N:0]

RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D8

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4]

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D8

RA[N:0]B -> A[N:0] : SDRAMs D[7:4]

RRASA -> RAS : SDRAMs D[3:0], D8

RRASB -> RAS : SDRAMs D[7:4]

RCASA -> CAS : SDRAMs D[3:0], D8

RCASB -> CAS : SDRAMs D[7:4]

RWEA -> WE : SDRAMs D[3:0], D8

RWEB -> WE : SDRAMs D[7:4]

A[N:0]

RAS

1:2

R

E

G

I

CAS

WE

S

T

CKE0

ODT0

E

R

RCKE0A -> CKE0 : SDRAMs D[3:0], D8

RCKE0B -> CKE0 : SDRAMs D[7:4]

RODT0A -> ODT0 : SDRAMs D[3:0], D8

RODT0B -> ODT0 : SDRAMs D[7:4]

PCK0A -> CK : SDRAMs D[3:0], D8

PCK0A -> CK : SDRAMs D[7:4]

CK0

PCK0A -> CK : SDRAMs D[3:0], D8

PCK0A -> CK : SDRAMs D[7:4]

QERR

RST

PAR_IN

Err_out

RESET**

RST** : SDRAMs D[8:0]

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

(Unused register inputs ODT1 and CKE1 have a 330 ohm resistor to ground)

- 11 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

10.2 4GB, 512Mx72 Module (Populated as 2 ranks of x8 DDR3 SDRAMs)

DQS8

DM8/DQS17

DQS17

DQS4

DM4/DQS13

DQS13

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

D8

D3

D2

D1

D0

D17

D12

D11

D10

D9

D4

D5

D6

D7

D13

D14

D15

D16

CB[7:0]

DQ[39:32]

DQS3

DM3/DQS12

DQS12

DQS5

DM5/DQS14

DQS14

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQ[31:24]

DQ[47:40]

DQS2

DM2/DQS11

DQS11

DQS6

DM6/DQS15

DQS15

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQ[23:16]

DQ[55:48]

DQS1

DM1/DQS10

DQS10

DQS7

DM7/DQS16

DQS16

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQ[15:8]

DQ[63:56]

Vtt

DQS0

DM0/DQS9

DQS9

DQS

TDQS

DQ[7:0]

ZQ

DQS

TDQS

DQ[7:0]

ZQ

DQ[7:0]

S0*

RS0A-> CS0 : SDRAMs D[3:0], D8

RS0B-> CS0 : SDRAMs D[7:4]

S1*

RS1A-> CS1 : SDRAMs D[12:9], D17

RS1B-> CS1 : SDRAMs D[16:13]

BA[N:0]

A[N:0]

RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17

RA[N:0]B -> A[N:0] : SDRAMs D[7:4, D[16:13]]

Vtt

RAS

RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17

RRASB -> RAS : SDRAMs D[7:4], D[16:13]

RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17

RCASB -> CAS : SDRAMs D[7:4], D[16:13]

RWEA -> WE : SDRAMs D[3:0], D[12:8], D17

RWEB -> WE : SDRAMs D[7:4], D[16:13]

RCKE0A -> CKE0 : SDRAMs D[3:0], D8

RCKE0B -> CKE0 : SDRAMs D[7:4]

RCKE1A -> CKE1 : SDRAMs D[12:9], D17

RCKE1B -> CKE1 : SDRAMs D[16:13]

RODT0A -> ODT0 : SDRAMs D[3:0], D8

RODT0B -> ODT0 : SDRAMs D[7:4]

V

Thermal sensor with SPD

CAS

Serial PD

D0 - D17

DDSPD

DD

SCL

1:2

R

E

G

I

S

T

E

R

WE

SDA

EVENT

A0 A1 A2

CKE0

CKE1

ODT0

ODT1

TT

SA0 SA1 SA2

V

D0 - D17

REFCA

REFDQ

SS

RODT1A -> ODT1 : SDRAMs D[12:9], D17

RODT1A -> ODT1 : SDRAMs D[16:13]

CK0

PCK0A -> CK : SDRAMs D[3:0], D8

PCK0B -> CK : SDRAMs D[7:4]

PCK1A -> CK : SDRAMs D[12:9], D17

PCK1B -> CK : SDRAMs D[16:13]

NOTE :

1. Unless otherwise noted, resistor values are 15Ω ± 5%.

2. RS0 and RS1 alternate between the back and front sides of the DIMM.

3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate

wiring diagram.

4. See the wiring diagrams for all resistors associated with the command, address

and control bus.

PCK0A -> CK : SDRAMs D[3:0], D8

PCK0B -> CK : SDRAMs D[7:4]

PCK1A -> CK : SDRAMs D[12:9], D17

PCK1B -> CK : SDRAMs D[16:13]

QERR

PAR_IN

Err_out

RST

RESET**

RST** : SDRAMs D[8:0]

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

- 12 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

10.3 4GB, 512Mx72 Module (Populated as 1 rank of x4 DDR3 SDRAMs)

ZQ

DQS8

VSS

DQS17

VSS

DQS8

VSS

DQS17

VSS

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[3:0]

D8

D3

D2

D1

D0

D17

D12

D11

D10

D9

D4

D5

D6

D7

D13

D14

D15

D16

DQ[3:0]

CB[3:0]

CB[7:4]

DQ[35:32]

DQ[39:36]

ZQ

DQS3

VSS

DQS17

VSS

DQS8

VSS

DQS17

VSS

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[3:0]

DQ[27:24]

DQ[31:28]

DQ[43:40]

DQ[47:44]

DQS8

VSS

DQS17

VSS

DQS8

VSS

DQS17

VSS

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[3:0]

DQ[19:16]

DQ[23:20]

DQ[51:48]

DQ[55:52]

DQS8

VSS

DQS17

VSS

DQS8

VSS

DQS17

VSS

DQS

DM

DQS

DM

DQS

DM

DQS

DM

DQ[3:0]

DQ[11:8]

DQ[15:12]

DQ[59:56]

DQ[63:60]

Vtt

DQS8

VSS

DQS17

VSS

DQS

DM

DQS

DM

DQ[3:0]

S0*

S1*

RS0A-> CS0 : SDRAMs D[3:0], D[12:8], D17

RS0B-> CS0 : SDRAMs D[7:4], D[16:13]]

DQ[3:0]

DQ[7:4]

BA[N:0]

A[N:0]

RBA[N:0]A -> BA[N:0] : SDRAMs D[3:0], D[12:8], D17

RBA[N:0]B -> BA[N:0] : SDRAMs D[7:4], D[16:13]

RA[N:0]A -> A[N:0] : SDRAMs D[3:0], D[12:8], D17

RA[N:0]B -> A[N:0] : SDRAMs D[7:4], D[16:13]

RAS

CAS

WE

RRASA -> RAS : SDRAMs D[3:0], D[12:8], D17

RRASB -> RAS : SDRAMs D[7:4], D[16:13]

RCASA -> CAS : SDRAMs D[3:0], D[12:8], D17

RCASB -> CAS : SDRAMs D[7:4], D[16:13]

RWEA -> WE : SDRAMs D[3:0], D[12:8], D17

RWEB -> WE : SDRAMs D[7:4], D[16:13]

Vtt

1:2

R

E

G

I

S

T

E

R

Thermal sensor with SPD

V_DDSPD

V_DD

Serial PD

SCL

D0 - D17

SDA

CKE0

ODT0

RCKE0A -> CKE0 : SDRAMs D[3:0], D[12:8], D17

RCKE0B -> CKE0 : SDRAMs D[7:4], D[16:13]

EVENT

A0 A1 A2

V_TT

RODT0A -> ODT0 : SDRAMs D[3:0], D[12:8], D17

RODT0B -> ODT0 : SDRAMs D[7:4], D[16:13]

SA0 SA1 SA2

V_REFCA

V_REFDQ

V_SS

D0 - D17

CK0

PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17

PCK0B -> CK : SDRAMs D[7:4], D[16:13]

PCK0A -> CK : SDRAMs D[3:0], D[12:8], D17

PCK0B -> CK : SDRAMs D[7:4], D[16:13]

NOTE :

1. Unless otherwise noted, resistor values are 15Ω ± 5%.

2. See the wiring diagrams for all resistors associated with the command, address

QERR

PAR_IN

RESET**

Err_out

RST

and control bus.

3. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appropriate

wiring diagram.

RST** : SDRAMs D[17:0]

*S[3:2], CKE1, ODT1, CK1 and CK1 are NC

(Unused register inputs ODT1 and CKE1 have a 330

Ω resistor to ground)

- 13 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

10.4 8GB, 1Gx72 Module (Populated as 2 ranks of x4 DDR3 SDRAMs)

VSS

RS0

RS1

DM CS ZQ

VSS

DM CS ZQ

VSS

DM CS ZQ

VSS

DM CS ZQ

D27

VSS

DQS0

DQS9

DQS

D0

D18

D9

DQ[3:0]

DQ[4:7]

DM CS ZQ

D19

DM CS ZQ

D10

DM CS ZQ

DQS1

DQS10

DQS

D1

D28

DQ[3:0]

DQ[11:8]

DQ[12:15]

DM CS ZQ

D29

DQS2

DQS11

DQS

D2

D20

D11

DQ[3:0]

DQ[16:19]

DQ[20:23]

DM CS ZQ

D21

DM CS ZQ

D12

DM CS ZQ

DQS3

DQS12

DQS

D3

D30

DQ[3:0]

DQ[24:27]

DQ[28:31]

DM CS ZQ

D31

DQS4

DQS13

DQS

D4

D22

D13

DQ[3:0]

DQ[32:35]

DQ[36:39]

DM CS ZQ

D23

DM CS ZQ

D14

DM CS ZQ

DQS5

DQS14

DQS

D5

D32

DQ[3:0]

DQ[40:43]

DQ[44:47]

DM CS ZQ

D33

DQS6

DQS15

DQS

D6

D24

D15

DQ[3:0]

DQ[48:51]

DQ[52:55]

DM CS ZQ

D25

DM CS ZQ

D16

DM CS ZQ

DQS7

DQS16

DQS

D7

D34

DQ[3:0]

DQ[56:59]

DQ[60:63]

DM CS ZQ

D35

DQS8

DQS17

DQS

D8

D26

D17

DQ[3:0]

CB[3:0]

CB[7:4]

Thermal sensor with SPD

S0[1:0]

S0[3:2]

RS0A-> CS0A : SDRAMs D[9:0]

RS1A-> CS1A : SDRAMs D[27:18]

RS0B-> CS0B : SDRAMs D[17:10]

RS1B-> CS1B : SDRAMs D[35:28]

RBA[2:0]A -> BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RBA[2:0]B -> BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

SCL

SDA

EVENT_n

A0 A1 A2

BA[2:0]

SA0 SA1 SA2

RA[15:0]A -> A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RA[15:0]B -> A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

A[15:0]

RAS

Serial PD w/integrated Thermal Sensor

RRASA -> RAS: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RRASB -> RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RCASA -> CAS: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RCASB -> CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

V

CAS

Serial PD

D0 - D17

DDSPD

1:2

R

E

G

I

S

T

E

R

RWEA -> WE: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RWEB -> WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

RCKE0A -> CKE0A: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RCKE0B -> CKE0B: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

V

DD

WE

V

TT

CKE0

RODT[1:0]A -> ODT0: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35

RODT[1:0]B -> ODT0: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]

V

D0 - D17

REFCA

REFDQ

SS

ODT0

CK0A_R0 -> CK: SDRAMs D[4:0], D[22:18]

CK0B_R0 -> CK: SDRAMs D[13:10], D[31:28]

CK0C_R1 -> CK: SDRAMs D[9:5], D[27:23]

CK0D_R1 -> CK: SDRAMs D[17:14], D[35:32]

CK0

CK0A_R0 -> CK: SDRAMs D[4:0], D[22:18]

CK0B_R0 -> CK: SDRAMs D[13:10], D[31:28]

CK0C_R1 -> CK: SDRAMs D[9:5], D[27:23]

NOTE :

CK0

1. ZQ resistors are 240Ω ± 1% . For all other resistor values refer to the appro-

priate wiring diagram.

CK0D_R1 -> CK: SDRAMs D[17:14], D[35:32]

PAR_IN

RESET

Err_out

QERR

RST

RST : SDRAMs D[35:0]

- 14 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

10.5 8GB, 1Gx72 Module (Populated as 4 ranks of x8 DDR3 SDRAMs)

DQS0

DQS

U0

U1

U2

U3

U4

U9

U18

U19

U20

U21

U22

U27

U28

U29

U30

U31

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

DQS1

S0

S1

RS0-> CS0 : SDRAMs D[8:0]

DQS

RS1-> CS1 : SDRAMs D[17:9]

RS2-> CS2 : SDRAMs D[26:18]

S2

S3

U10

U11

U12

U13

RS3-> CS3 : SDRAMs D[35:27]

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[15:8]

WBA[N:0] -> BA[N:0]: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

EBA[N:0] -> BA[N:0]: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

BA[N:0]

WA[N:0] -> A[N:0]: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

EA[N:0] -> A[N:0]: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

A[N:0]

RAS

WRAS -> RAS: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

ERAS -> RAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

DQS2

DQS

WCAS -> CAS: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

ECAS -> CAS: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

CAS

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[23:16]

1:2

R

E

G

I

S

T

E

R

WWE -> WE: SDRAMs D[4:0], D8, D[13:9], D[22:18], D[31:27]

EWE -> WE: SDRAMs D[8:5], D[17:14], D[26:23], D[35:32]

WCKE0 -> CKE0: SDRAMs D[4:0], D[22:18]

WE

CKE0

ECKE0 -> CKE0: SDRAMs D[8:5], D[26:23]

WCKE1 -> CKE1: SDRAMs D[13:9], D[31:27]

ECKE1 -> CKE1: SDRAMs D[17:14], D[35:32]

WODT0 -> ODT0: SDRAMs D[4:0]

EODT0 -> ODT0: SDRAMs D[8:5]

WODT1 -> ODT1: SDRAMs D[22:18]

EODT1 -> ODT1: SDRAMs D[26:23]

CKE1

DQS3

DQS

ODT0

ODT1

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[31:24]

PCK0 -> CK: SDRAMs D[4:0], D[13:9]

PCK1 -> CK: SDRAMs D[8:5], D[26:23]

PCK2 -> CK: SDRAMs D[22:18], D[31:27]

PCK3 -> CK: SDRAMs D[17:14], D[35:32]

CK0

PCK0 -> CK: SDRAMs D[4:0], D[13:9]

PCK1 -> CK: SDRAMs D[8:5], D[26:23]

PCK2 -> CK: SDRAMs D[22:18], D[31:27]

PCK3 -> CK: SDRAMs D[17:14], D[35:32]

DQS8

DQS

CK0

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

CB[7:0]

QERR

PAR_IN

RESET

Err_out

RST

RST : SDRAMs D[35:0]

Vtt

Thermal sensor with SPD

SCL

EVENT

SDA

EVENT

A0 A1 A2

SA0 SA1 SA2

DQS4

DQS

V

Serial PD

D0 - D35

DDSPD

U5

U6

U7

U8

U14

U15

U16

U17

U23

U24

U25

U26

U32

U33

U34

U35

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[39:32]

V

DD

TT

V

D0 - D35

DQS5

REFCA

REFDQ

SS

DQS

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[47:40]

DQS6

DQS

NOTE :

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[55:48]

1. Unless otherwise noted, resistor values are 15Ω ± 5%.

2. See the wiring diagrams for all resistors associated with the

command, address and control bus.

3. ZQ resitors are 240Ω ± 1% . For all other resistor values refer to

DQS3

DQS

the appropriate wiring diagram.

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[7:0]

ZQ

DQ[31:24]

Vtt

- 15 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

11. Absolute Maximum Ratings

11.1 Absolute Maximum DC Ratings

Symbol

Parameter

Rating

Units

NOTE

V_DD

Voltage on V_DDpin relative to V_SS

-0.4 V ~ 1.975 V

-55 to +100

V

1,3

V_DDQ

Voltage on V_DDQpin relative to V_SS

Voltage on any pin relative to V_SS

Storage Temperature

V

1,3

1

V

_IN,V_OUT

T_STG

°C

1, 2

NOTE :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

3. V and V

must be within 300mV of each other at all times; and V

must be not greater than 0.6 x V

, When V and V

are less than 500mV; V

may be

REF

DD

DDQ

REF

DDQ

DD

DDQ

equal to or less than 300mV.

11.2 DRAM Component Operating Temperature Range

Symbol

Parameter

rating

Unit

NOTE

T_OPER

Operating Temperature Range

0 to 95

°C

1, 2, 3

NOTE :

1. Operating Temperature T

is the case surface temperature on the center/top side of the DRAM. For measurement conditions, please refer to the JEDEC document

OPER

JESD51-2.

2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be main-

tained between 0-85°C under all operating conditions

3. Some applications require operation of the Extended Temperature Range between 85°C and 95°C case temperature. Full specifications are guaranteed in this range, but the

following additional conditions apply:

a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.

b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature

Range capability (MR2 A6 = 0b and MR2 A7 = 1b), in this case IDD6 current can be increased around 10~20% than normal Temperature range.

12. AC & DC Operating Conditions

12.1 Recommended DC Operating Conditions (SSTL-15)

Rating

Symbol

Parameter

Units

NOTE

Min.

1.425

Typ.

1.5

Max.

1.575

V_DD

Supply Voltage

Supply Voltage for Output

V

1,2

V_DDQ

1.5

NOTE:

1. Under all conditions V

must be less than or equal to V

.

DDQ

DD

2. V

tracks with V . AC parameters are measured with V and V

tied together.

DDQ

DD

DDQ

- 16 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

13. AC & DC Input Measurement Levels

13.1 AC & DC Logic Input Levels for Single-ended Signals

[ Table 2 ] Single-ended AC & DC input levels for Command and Address

DDR3-800/1066/1333/1600

DDR3-1866

Symbol

Parameter

Unit NOTE

Max.

Min.

Max.

Min.

V_IH.CA(DC100)

V_REF+ 100

V_DD

V_REF+ 100

V_SS

V_DD

DC input logic high

DC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

mV

1,5

V

_IL.CA(DC100)

_IH.CA(AC175)

_IL.CA(AC175)

_IH.CA(AC150)

_IL.CA(AC150)

_IH.CA(AC135)

_IL.CA(AC135)

_IH.CA(AC125)

_IL.CA(AC125)

V_SS

V_REF- 100

1,6

V

V_REF+ 175

Note 2

-

1,2,7

1,2,8

1,2,7

1,2,8

1,2,7

1,2,8

1,2,7

1,2,8

V

V_REF- 175

Note 2

-

V

V_REF+150

Note 2

-

V

V_REF-150

Note 2

-

V

V_REF+ 135

-

Note 2

V_REF- 135

V

Note 2

V

V_REF+125

Note 2

V

V_REF-125

Note 2

Reference Voltage for ADD,

CMD inputs

V

_REFCA(DC)

0.49*V_DD

0.51*V_DD

0.49*V_DD

0.51*V_DD

V

3,4

NOTE :

1. For input only pins except RESET, V

= V

(DC)

REFCA

REF

2. See ’Overshoot/Undershoot Specification’ on page 18.

3. The AC peak noise on V may not allow V to deviate from V

(DC) by more than ± 1% V (for reference : approx. ± 15mV)

REF

DD

4. For reference : approx. V /2 ± 15mV

DD

5. V (dc) is used as a simplified symbol for V

(DC100)

IH

IH.CA

6. V (dc) is used as a simplified symbol for V

(DC100)

IL

IL.CA

7. V (ac) is used as a simplified symbol for V

(AC175), V

(AC150), V

(AC135) and V

(AC125); V

(AC175) value is used when V

+ 175mV is referenced

REF

IH

IH.CA

, V

(AC150) value is used when VREF + 150mV is referenced, V

(AC135) value is used when VREF + 135mV is referenced and V

(AC125) value is used when

IH.CA

VREF + 125mV is referenced.

8. V (ac) is used as a simplified symbol for V

(AC175) and V

(AC150), V

(AC135) and V

(AC125); V

(AC175) value is used when V

- 175mV is refer-

REF

IL

IL.CA

enced,

V

(AC150) value is used when V

- 150mV is referenced, V

(AC135) value is used when V

- 135mV is referenced and V (AC125) value is used

IL.CA

REF

IL.CA

REF

when V

- 125mV is referenced.

REF

[ Table 3 ] Single-ended AC & DC input levels for DQ and DM

DDR3-800/1066

DDR3-1333/1600

DDR3-1866

Symbol

Parameter

Unit NOTE

Min.

Max.

Min.

Max.

Min.

Max.

V_IH.DQ(DC100)

V_REF+ 100

V_DD

V_REF+ 100

V_DD

V_REF+ 100

V_DD

DC input logic high

DC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

AC input logic high

AC input logic low

mV

1,5

V

_IL.DQ(DC100)

_IH.DQ(AC175)

_IL.DQ(AC175)

_IH.DQ(AC150)

_IL.DQ(AC150)

_IH.DQ(AC135)

_IL.DQ(AC135)

V_SS

V_REF- 100

V_SS

V_REF- 100

V_SS

V_REF- 100

1,6

V

V_REF+ 175

NOTE 2

-

1,2,7

1,2,8

1,2,7

1,2,8

1,2,7

1,2,8

V

V_REF- 175

NOTE 2

-

V

V_REF+ 150

NOTE 2

V_REF- 150

-

V

V_REF- 150

NOTE 2

-

V

V_REF+ 135

-

NOTE 2

V_REF- 135

V

NOTE 2

Reference Voltage for DQ,

DM inputs

V_REF_DQ(DC)

0.49*V_DD

0.51*V_DD

0.49*V_DD

0.51*V_DD

0.49*V_DD

0.51*V_DD

V

3,4

NOTE :

1. For input only pins except RESET, V

= V

(DC)

REFDQ

REF

2. See ’Overshoot/Undershoot Specification’ on page 18.

3. The AC peak noise on V

may not allow V

to deviate from V

(DC) by more than ± 1% V (for reference : approx. ± 15mV)

REF DD

REF

4. For reference : approx. V /2 ± 15mV

DD

5. V (dc) is used as a simplified symbol for V

(DC100)

IH

IH.DQ

6. V (dc) is used as a simplified symbol for V

(DC100)

IL

IL.DQ

7. V (ac) is used as a simplified symbol for V

(AC175), V

(AC150) and V

(AC135) ; V

(AC175) value is used when V

+ 175mV is referenced,

REF

IH

IH.DQ

V

(AC150) value is used when V

+ 150mV is referenced.

IH.DQ

REF

8. V (ac) is used as a simplified symbol for V

(AC175), V

(AC150) ; V

(AC175) value is used when V

- 175mV is referenced, V

(AC150) value is used when

IL.DQ

IL

IL.DQ

REF

V

- 150mV is referenced.

REF

- 17 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

13.2 V Tolerances.

REF

The dc-tolerance limits and ac-noise limits for the reference voltages V_REFCAand V_REFDQare illustrate in Figure 1. It shows a valid reference voltage

_REF(t) as a function of time. (V_REFstands for V_REFCAand V_REFDQlikewise).

_REF(DC) is the linear average of V_REF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of V_REF. Fur-

thermore V_REF(t) may temporarily deviate from V_REF(DC) by no more than ± 1% V_DD

V

.

voltage

V_DD

V_SS

time

Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits

The voltage levels for setup and hold time measurements V_IH(AC), V_IH(DC), V_IL(AC) and V_IL(DC) are dependent on V_REF

.

"V_REF" shall be understood as V_REF(DC), as defined in Figure 1.

This clarifies, that dc-variations of V_REFaffect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to

which setup and hold is measured. System timing and voltage budgets need to account for V_REF(DC) deviations from the optimum position within the

data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V_REFac-noise.

Timing and voltage effects due to ac-noise on V_REFup to the specified limit (+/-1% of V_DD) are included in DRAM timings and their associated deratings.

- 18 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

13.3 AC and DC Logic Input Levels for Differential Signals

13.3.1 Differential Signals Definition

tDVAC

V_IH.DIFF.AC.MIN

V_IH.DIFF.MIN

0.0

half cycle

V_IL.DIFF.MAX

V_IL.DIFF.AC.MAX

tDVAC

time

Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC

13.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS)

DDR3-800/1066/1333/1600/1866

Symbol

Parameter

unit

NOTE

min

max

NOTE 3

V_IHdiff

V_ILdiff

_IHdiff(AC)

_ILdiff(AC)

differential input high

differential input low

+0.2

NOTE 3

V

1

2

-0.2

V

2 x (V_IH(AC) - V_REF)

differential input high ac

differential input low ac

NOTE 3

V

2 x (V_IL(AC) - V_REF)

NOTE 3

NOTE :

1. Used to define a differential signal slew-rate.

2. for CK - CK use V /V (AC) of ADD/CMD and V

; for DQS - DQS use V /V (AC) of DQs and V

; if a reduced ac-high or ac-low level is used for a signal group,

IH IL

REFCA

IH IL

REFDQ

then the reduced level applies also here.

3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL need to be within the respective limits (V (DC) max, V (DC)min) for single-

IH

IL

ended signals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"

[ Table 4 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.

tDVAC [ps] @ |V_IH/Ldiff(AC)|

= 350mV

tDVAC [ps] @ |V_IH/Ldiff(AC)|

= 300mV

tDVAC [ps] @ |V_IH/Ldiff(AC)|

= 270mV

tDVAC [ps] @ |V_IH/Ldiff(AC)|

= 250mV

Slew Rate [V/ns]

min

75

57

50

38

34

29

22

13

0

max

min

175

170

167

163

162

161

159

155

150

max

min

TBD

max

min

TBD

max

> 4.0

4.0

-

3.0

2.0

1.8

1.6

1.4

1.2

1.0

< 1.0

0

- 19 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

13.3.3 Single-ended Requirements for Differential Signals

Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.

CK and CK have to approximately reach V_SEHmin / V_SELmax (approximately equal to the ac-levels ( V_IH(AC) / V_IL(AC) ) for ADD/CMD signals) in every

half-cycle.

DQS, DQS have to reach V_SEHmin / V_SELmax (approximately the ac-levels ( V_IH(AC) / V_IL(AC) ) for DQ signals) in every half-cycle proceeding and follow-

ing a valid transition.

Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V_IH150(AC)/V_IL150(AC) is used for ADD/CMD

signals, then these ac-levels apply also for the single-ended signals CK and CK .

V_DDor V_DDQ

V_SEHmin

V_SEH

V_DD/2 or V_DDQ/2

CK or DQS

V_SELmax

V_SEL

V_SSor V_SSQ

time

Figure 3. Single-ended requirement for differential signals

Note that while ADD/CMD and DQ signal requirements are with respect to V_REF, the single-ended components of differential signals have a requirement

with respect to V_DD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-

ended components of differential signals the requirement to reach V_SELmax, V_SEHmin has no bearing on timing, but adds a restriction on the common

mode characteristics of these signals.

[ Table 5 ] Single ended levels for CK, DQS, CK, DQS

DDR3-800/1066/1333/1600/1866

Symbol

Parameter

Unit

NOTE

Min

Max

(V_DD/2)+0.175

Single-ended high-level for strobes

Single-ended high-level for CK, CK

Single-ended low-level for strobes

Single-ended low-level for CK, CK

NOTE 3

V

1, 2

V_SEH

(V_DD/2)+0.175

NOTE 3

(V_DD/2)-0.175

V_SEL

NOTE 3

NOTE :

1. For CK, CK use V /V (AC) of ADD/CMD; for strobes (DQS, DQS) use V /V (AC) of DQs.

IH IL

2. V (AC)/V (AC) for DQs is based on V

; V (AC)/V (AC) for ADD/CMD is based on V

; if a reduced ac-high or ac-low level is used for a signal group, then the

REFCA

IH

IL

REFDQ

IH

IL

reduced level applies also here

3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (V (DC) max, V (DC)min) for single-ended sig-

IH

IL

nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"

- 20 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

13.3.4 Differential Input Cross Point Voltage

To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input

signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage V_IXis measured from the actual

cross point of true and complement signal to the mid level between of V_DDand V_SS

.

V_DD

CK, DQS

V_IX

V_DD/2

V_IX

CK, DQS

V_SS

Figure 4. V_IXDefinition

[ Table 6 ] Cross point voltage for differential input signals (CK, DQS)

DDR3-800/1066/1333/1600/1866

Symbol

Parameter

Unit

NOTE

Min

-150

-175

-150

Max

150

175

150

mV

2

1

2

V_IX

Differential Input Cross Point Voltage relative to V_DD/2 for CK,CK

Differential Input Cross Point Voltage relative to V_DD/2 for DQS,DQS

NOTE :

1. Extended range for V is only allowed for clock and if single-ended clock input signals CK and CK are monotonic, have a single-ended swing V

/ V

of at least V /2

SEH DD

IX

SEL

±250 mV, and the differential slew rate of CK-CK is larger than 3 V/ ns.

2. The relation between V Min/Max and V

/V

should satisfy following.

IX

SEL SEH

(V /2) + V (Min) - V ≥ 25mV

DD

IX

SEL

V

- ((V /2) + V (Max)) ≥ 25mV

DD IX

SEH

13.4 Slew Rate Definition for Single Ended Input Signals

See "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.

See "Data Setup, Hold and Slew Rate Derating" for single-ended slew rate definitions for data signals.

13.5 Slew rate definition for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in below.

[ Table 7 ] Differential input slew rate definition

Measured

Description

Defined by

From

To

V_IHdiffmin- V_ILdiffmax

Delta TRdiff

V_ILdiffmax

V_IHdiffmin

Differential input slew rate for rising edge (CK-CK and DQS-DQS)

Differential input slew rate for falling edge (CK-CK and DQS-DQS)

V_IHdiffmin- V_ILdiffmax

Delta TFdiff

V_IHdiffmin

V_ILdiffmax

NOTE : The differential signal (i.e. CK - CK and DQS - DQS) must be linear between these thresholds

V

IHdiffmin

ILdiffmax

0

V

delta TFdiff

delta TRdiff

Figure 5. Differential input slew rate definition for DQS, DQS and CK, CK

- 21 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

14. AC & DC Output Measurement Levels

14.1 Single Ended AC and DC Output Levels

[ Table 8 ] Single Ended AC and DC output levels

Symbol Parameter

DDR3-800/1066/1333/1600/1866

Units

NOTE

V_OH(DC) DC output high measurement level (for IV curve linearity)

0.8 x V_DDQ

V

_OM(DC) DC output mid measurement level (for IV curve linearity)

_OL(DC) DC output low measurement level (for IV curve linearity)

V_OH(AC) AC output high measurement level (for output SR)

0.5 x V_DDQ

0.2 x V_DDQ

V

V_TT+ 0.1 x V_DDQ

V_TT- 0.1 x V_DDQ

1

V

_OL(AC) AC output low measurement level (for output SR)

NOTE : 1. The swing of +/-0.1 x V

load of 25Ω to V =V

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

/2.

DDQ

TT

DDQ

14.2 Differential AC and DC Output Levels

[ Table 9 ] Differential AC and DC output levels

Symbol

Parameter

DDR3-800/1066/1333/1600/1866

Units

NOTE

V_OHdiff(AC)

AC differential output high measurement level (for output SR)

+0.2 x V_DDQ

V

1

V

_OLdiff(AC)

AC differential output low measurement level (for output SR)

-0.2 x V_DDQ

V

1

NOTE : 1. The swing of +/-0.2xV

load of 25Ω to V =V

is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test

/2 at each of the differential outputs.

DDQ

TT

DDQ

14.3 Single-ended Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V_OL(AC) and V_OH(AC)

for single ended signals as shown in below.

[ Table 10 ] Single ended Output slew rate definition

Measured

Description

Defined by

From

To

V_OH(AC)-V_OL(AC)

Delta TRse

V

_OL(AC)

V_OH(AC)

Single ended output slew rate for rising edge

Single ended output slew rate for falling edge

V_OH(AC)-V_OL(AC)

Delta TFse

V

_OH(AC)

V_OL(AC)

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 11 ] Single ended output slew rate

DDR3-800

Min Max

2.5

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Min Max

2.5

Parameter

Symbol

Units

Min

Max

Min

Max

Min

Max

5¹⁾

Single ended output slew rate

Description : SR : Slew Rate

SRQse

5

2.5

5

2.5

5

2.5

5

V/ns

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

se : Single-ended Signals

For Ron = RZQ/7 setting

NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ

signals in the same byte lane are static (i.e they stay at either high or low).

- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the

remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.

V

OH(AC)

V

TT

OL(AC)

delta TFse

delta TRse

Figure 6. Single-ended Output Slew Rate Definition

- 22 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

14.4 Differential Output Slew Rate

With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V_OLdiff(AC) and V_OH-

_diff(AC) for differential signals as shown in below.

[ Table 12 ] Differential Output slew rate definition

Measured

Description

Defined by

From

To

V_OHdiff(AC)-V_OLdiff(AC)

Delta TRdiff

V

_OLdiff(AC)

V_OHdiff(AC)

Differential output slew rate for rising edge

Differential output slew rate for falling edge

V_OHdiff(AC)-V_OLdiff(AC)

Delta TFdiff

V

_OHdiff(AC)

V_OLdiff(AC)

NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.

[ Table 13 ] Differential Output slew rate

DDR3-800

Min Max

10

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Parameter

Symbol

Units

Min

Max

10

Min

Max

Min

Max

10

Min

Max

Differential output slew rate

Description : SR : Slew Rate

SRQdiff

5

10

5

12

V/ns

Q : Query Output (like in DQ, which stands for Data-in, Query-Output)

diff : Differential Signals

For Ron = RZQ/7 setting

V

(AC)

OHdiff

V

TT

OLdiff

delta TFdiff

delta TRdiff

Figure 7. Differential output slew rate definition

- 23 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

15. DIMM IDD specification definition

Symbol

Description

Operating One Bank Active-Precharge Current

1)

CKE: High; External clock: On; tCK, nRC, nRAS, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between ACT and PRE;

Command, Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:

IDD0

2)

0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

tern

Operating One Bank Active-Read-Precharge Current

1)

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between ACT, RD

IDD1

and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time:

2)

0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pat-

tern

Precharge Standby Current

1)

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank

IDD2N

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode

2)

Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Precharge Power-Down Current Slow Exit

1)

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank

IDD2P0

2)

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

;

3)

ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit

Precharge Power-Down Current Fast Exit

1)

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank

IDD2P1

IDD2Q

IDD3N

IDD3P

2)

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

3)

ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit

Precharge Quiet Standby Current

1)

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank

2)

Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers

ODT Signal: stable at 0

;

Active Standby Current

1)

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank

Address Inputs: partially toggling ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode

2)

Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Active Power-Down Current

1)

CKE: Low; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: stable at 1; Command, Address, Bank

2)

Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers ; ODT

Signal: stable at 0

Operating Burst Read Current

1)

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between RD; Command, Address,

IDD4R

IDD4W

Bank Address Inputs: partially toggling ; Data IO: seamless read data burst with different data between one burst and the next one ; DM:stable at 0; Bank

2)

Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable

at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Operating Burst Write Current

1)

CKE: High; External clock: On; tCK, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between WR; Command, Address,

Bank Address Inputs: partially toggling ; Data IO: seamless write data burst with different data between one burst and the next one ; DM: stable at 0; Bank

2)

Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... ; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: stable

at HIGH; Pattern Details: Refer to Component Datasheet for detail pattern

Burst Refresh Current

1)

CKE: High; External clock: On; tCK, CL, nRFC: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS: High between REF; Command,

IDD5B

IDD6

Address, Bank Address Inputs: partially toggling ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC ; Output Buffer and

2)

RTT: Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

Self Refresh Current: Normal Temperature Range

4)

5)

TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Normal ; CKE: Low; External clock: Off; CK and CK:

1)

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

2)

Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING

6)

Self-Refresh Current: Extended Temperature Range (optional)

4)

5)

TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled ; Self-Refresh Temperature Range (SRT): Extended ; CKE: Low; External clock: Off; CK and CK:

IDD6ET

1)

LOW; CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0;

2)

Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers ; ODT Signal: FLOATING

Operating Bank Interleave Read Current

1)

CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: Refer to Component Datasheet for detail pattern ; BL: 8 ; AL: CL-1; CS: High

IDD7

IDD8

between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling ; Data IO: read data bursts with different data between one burst and

the next one ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing ; Output Buffer and RTT:

2)

Enabled in Mode Registers ; ODT Signal: stable at 0; Pattern Details: Refer to Component Datasheet for detail pattern

RESET Low Current

RESET : Low; External clock : off; CK and CK : LOW; CKE : FLOATING ; CS, Command, Address, Bank Address, Data IO : FLOATING ; ODT Signal :

FLOATING

- 24 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

NOTE :

1) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

2) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B

3) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit

4) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature

5) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range

6) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device

7) IDD current measure method and detail patterns are described on DDR3 component datasheet

8) VDD and VDDQ are merged on module PCB.

9) DIMM IDD SPEC is measured with Qoff condition

(IDDQ values are not considered)

- 25 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

16. IDD SPEC Table

M392B5773DH0 : 2GB(256Mx72) Module

CF8

Symbol

CH9

CK0

CMA

Unit

NOTE

(DDR3-1066@CL=7)

(DDR3-1333@CL=9) (DDR3-1600@CL=11) (DDR3-1866@CL=13)

IDD0

IDD1

955

1045

648

1030

1120

688

1125

1215

738

1170

1260

738

mA

IDD2P0(slow exit)

IDD2P1(fast exit)

IDD2N

675

715

765

738

763

830

870

IDD2Q

743

810

850

IDD3P

693

733

810

IDD3N

870

955

995

1013

1620

1720

1760

138

IDD4R

1225

1280

1590

138

1345

1400

1675

138

1530

1585

1760

138

IDD4W

IDD5B

IDD6

IDD7

1585

138

1885

138

1980

138

2025

138

IDD8

M392B5273DH0 : 4GB(512Mx72) Module

CF8

Symbol

CH9

CK0

CMA

Unit

NOTE

(DDR3-1066@CL=7)

(DDR3-1333@CL=9) (DDR3-1600@CL=11) (DDR3-1866@CL=13)

IDD0

IDD1

1108

1198

756

1210

1273

796

1305

1395

846

1350

1440

846

mA

1

IDD2P0(slow exit)

IDD2P1(fast exit)

IDD2N

810

850

900

936

916

1010

990

1050

1030

990

1050

1030

990

IDD2Q

896

IDD3P

846

886

IDD3N

1140

1378

1433

1743

246

1270

1525

1580

1855

246

1310

1710

1765

1940

246

1346

1800

1900

1940

246

IDD4R

1

IDD4W

IDD5B

IDD6

IDD7

1738

246

2065

246

2160

246

2205

246

1

IDD8

NOTE :

1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.

- 26 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

M392B5270DH0 : 4GB(512Mx72) Module

CF8

Symbol

CH9

CK0

CMA

Unit

NOTE

(DDR3-1066@CL=7)

(DDR3-1333@CL=9) (DDR3-1600@CL=11) (DDR3-1866@CL=13)

IDD0

IDD1

1270

1450

756

1390

1570

796

1530

1710

846

1620

1800

846

mA

IDD2P0(slow exit)

IDD2P1(fast exit)

IDD2N

810

850

900

936

916

1010

990

1050

1030

990

1050

1030

990

IDD2Q

896

IDD3P

846

886

IDD3N

1140

1540

1730

2580

246

1270

1750

1940

2710

246

1310

1980

2260

2840

246

1346

2340

2440

2840

246

IDD4R

IDD4W

IDD5B

IDD6

IDD7

2530

246

2920

246

3060

246

3150

246

IDD8

M392B1K70DM0 : 8GB(1Gx72) Module

CF8

Symbol

CH9

CK0

CMA

Unit

NOTE

(DDR3-1066@CL=7)

(DDR3-1333@CL=9) (DDR3-1600@CL=11) (DDR3-1866@CL=13)

IDD0

IDD1

1576

1756

972

1750

1876

1012

1120

1370

1350

1192

1900

2110

2300

3070

462

1890

2070

1062

1170

1410

1390

1350

1940

2340

2620

3200

462

1980

2160

1062

1242

1410

1390

1350

2012

2700

2800

3200

462

mA

1

IDD2P0(slow exit)

IDD2P1(fast exit)

IDD2N

1080

1222

1202

1152

1680

1846

2036

2886

462

IDD2Q

IDD3P

IDD3N

IDD4R

1

IDD4W

IDD5B

IDD6

IDD7

2836

462

3280

462

3420

462

3510

462

1

IDD8

NOTE :

1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.

- 27 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

M392B1K73DM0 : 8GB(1Gx72) Module

CF8

CH9

Symbol

Unit

NOTE

(DDR3-1066@CL=7)

(DDR3-1333@CL=9)

IDD0

IDD1

1414

1504

972

1570

1660

1012

1120

1370

1350

1192

1900

1750

1780

2215

462

mA

1

IDD2P0(slow exit)

IDD2P1(fast exit)

IDD2N

1080

1222

1202

1152

1680

1549

1589

2049

462

IDD2Q

IDD3P

IDD3N

IDD4R

1

IDD4W

IDD5B

IDD6

IDD7

2044

462

2335

462

1

IDD8

NOTE :

1. DIMM IDD SPEC is calculated with considering de-actived rank(IDLE) is IDD2N.

- 28 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

17. Input/Output Capacitance

[ Table 14 ] Input/Output Capacitance

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

DDR3-1866

Parameter

Symbol

Units NOTE

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Input/output capacitance

CIO

CCK

1.5

3.0

1.5

2.7

1.5

2.5

1.5

2.3

1.4

2.2

pF

1,2,3

2,3

(DQ, DM, DQS, DQS, TDQS, TDQS)

Input capacitance

(CK and CK)

0.8

0

1.6

0.15

1.5

0.2

0.3

0.5

0.8

0

1.6

0.15

1.5

0.2

0.3

0.5

0.8

0

1.4

0.15

1.3

0.8

0

1.4

0.15

1.3

0.8

0

1.3

0.15

1.2

Input capacitance delta

(CK and CK)

CDCK

CI

2,3,4

2,3,6

2,3,5

2,3,7,8

Input capacitance

0.75

0

0.75

0

0.75

0

0.75

0

0.75

0

(All other input-only pins)

Input capacitance delta

(DQS and DQS)

CDDQS

CDI_CTRL

0.15

0.2

0.15

0.2

0.15

0.2

Input capacitance delta

-0.5

-0.4

(All control input-only pins)

Input capacitance delta

CDI_ADD_CMD -0.5

0.4

pF 2,3,9,10

(all ADD and CMD input-only pins)

Input/output capacitance delta

CDIO

CZQ

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

-0.5

-

0.3

3

pF

2,3,11

(DQ, DM, DQS, DQS, TDQS, TDQS)

Input/output capacitance of ZQ pin

pF 2, 3, 12

NOTE : This parameter is Component Input/Output Capacitance so that is different from Module level Capacitance.

1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS

2. This parameter is not subject to production test. It is verified by design and characterization.

The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with

, V , V , V applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). V =V =1.5V, V =V /2 and on-die

V

DD

DDQ

SS

SSQ

DD

DDQ

BIAS

DD

termination off.

3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

4. Absolute value of CCK-CCK

5. Absolute value of CIO(DQS)-CIO(DQS)

6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE.

7. CDI_CTRL applies to ODT, CS and CKE

8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK))

9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE

10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK))

11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS))

12. Maximum external load capacitance on ZQ pin: 5pF

- 29 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

18. Electrical Characteristics and AC timing

(0 °C<T_CASE≤95 °C, V_DDQ= 1.5V ± 0.075V; V_DD= 1.5V ± 0.075V)

18.1 Refresh Parameters by Device Density

Parameter

Symbol

1Gb

110

7.8

2Gb

160

7.8

4Gb

260

7.8

8Gb

350

7.8

Units

ns

NOTE

All Bank Refresh to active/refresh cmd time

tRFC

0 °C ≤ T_CASE≤ 85°C

μs

Average periodic refresh interval

tREFI

85 °C < T_CASE≤ 95°C

3.9

μs

1

NOTE :

1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in

this material.

18.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Speed

DDR3-800

6-6-6

min

6

DDR3-1066

7-7-7

min

DDR3-1333

9-9-9

min

9

DDR3-1600

11-11-11

min

DDR3-1866

13-13-13

min

Bin (CL - tRCD - tRP)

Units

NOTE

Parameter

CL

7

11

13

tCK

ns

tRCD

tRP

15

13.13

37.5

13.5

36

13.75

35

13.91

34

15

tRAS

tRC

37.5

52.5

10

50.63

7.5

49.5

6.0

48.75

6.0

47.91

5.0

tRRD

tFAW

40

37.5

30

27

18.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.

[ Table 15 ] DDR3-800 Speed Bins

Speed

DDR3-800

6 - 6 - 6

CL-nRCD-nRP

Units

NOTE

Parameter

Symbol

tAA

min

15

max

Internal read command to first data

ACT to internal read or write delay time

PRE command period

20

ns

tRCD

tRP

15

-

15

-

ns

ACT to ACT or REF command period

ACT to PRE command period

CL = 6 / CWL = 5

tRC

52.5

37.5

2.5

ns

tRAS

9*tREFI

3.3

ns

tCK(AVG)

ns

1,2,3

Supported CL Settings

6

5

nCK

Supported CWL Settings

- 30 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

[ Table 16 ] DDR3-1066 Speed Bins

Speed

DDR3-1066

CL-nRCD-nRP

7 - 7 - 7

Units

NOTE

Parameter

Internal read command to first data

ACT to internal read or write delay time

PRE command period

Symbol

tAA

min

13.125

50.625

37.5

max

20

ns

tRCD

-

tRP

-

ns

ACT to ACT or REF command period

ACT to PRE command period

tRC

ns

tRAS

9*tREFI

3.3

ns

CWL = 5

tCK(AVG)

2.5

ns

1,2,3,5

1,2,3,4

4

CL = 6

CL = 7

CL = 8

CWL = 6

CWL = 5

CWL = 6

CWL = 5

CWL = 6

Reserved

ns

1.875

<2.5

ns

1,2,3,4,9

4

Reserved

ns

1,2,3

Supported CL Settings

Supported CWL Settings

6,7,8

5,6

nCK

[ Table 17 ] DDR3-1333 Speed Bins

Speed

DDR3-1333

9 -9 - 9

CL-nRCD-nRP

Units

NOTE

Parameter

Symbol

tAA

min

max

Internal read command to first data

13.5 (13.125)⁹

49.5 (49.125)⁹

36

20

ns

ACT to internal read or write delay time

PRE command period

tRCD

-

tRP

-

ns

ACT to ACT or REF command period

ACT to PRE command period

tRC

ns

tRAS

9*tREFI

3.3

ns

CWL = 5

tCK(AVG)

2.5

ns

1,2,3,6

1,2,3,4,6

4

CL = 6

CL = 7

CL = 8

CWL = 6

CWL = 7

CWL = 5

CWL = 6

CWL = 7

CWL = 5

CWL = 6

CWL = 7

CWL = 5,6

CWL = 7

CWL = 5,6

CWL = 7

Reserved

ns

4

1.875

1.5

<2.5

ns

1,2,3,4,6

1,2,3,4

4

Reserved

ns

1,2,3,6

1,2,3,4

4

Reserved

ns

CL = 9

<1.875

ns

1,2,3,4,9

4

Reserved

6,7,8,9

ns

CL = 10

ns

1,2,3

Supported CL Settings

Supported CWL Settings

nCK

5,6,7

- 31 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

[ Table 18 ] DDR3-1600 Speed Bins

Speed

DDR3-1600

CL-nRCD-nRP

11-11-11

Units

NOTE

Parameter

Symbol

min

max

13.75

Intermal read command to first data

tAA

20

ns

(13.125)⁹

13.75

ACT to internal read or write delay time

PRE command period

tRCD

tRP

-

(13.125)⁹

13.75

(13.125)⁹

48.75

ACT to ACT or REF command period

ACT to PRE command period

tRC

(48.125)⁹

tRAS

35

9*tREFI

3.3

ns

nCK

CWL = 5

tCK(AVG)

2.5

1,2,3,7

1,2,3,4,7

4

CL = 6

CWL = 6

CWL = 7, 8

CWL = 5

CWL = 6

CWL = 7

CWL = 8

CWL = 5

CWL = 6

CWL = 7

CWL = 8

CWL = 5,6

CWL = 7

CWL = 8

CWL = 5,6

CWL = 7

CWL = 8

CWL = 5,6,7

CWL = 8

Reserved

4

1.875

<2.5

1,2,3,4,7

4

CL = 7

Reserved

4

1,2,3,7

1,2,3,4,7

1,2,3,4

4

CL = 8

CL = 9

Reserved

1.5

<1.875

<1.5

1,2,3,4,7

1,2,3,4

4

Reserved

CL = 10

CL = 11

1,2,3,7

1,2,3,4

4

Reserved

1.25

1,2,3,9

Supported CL Settings

Supported CWL Settings

6,7,8,9,10,11

5,6,7,8

- 32 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

[ Table 19 ] DDR3-1866 Speed Bins

Speed

DDR3-1866

CL-nRCD-nRP

13-13-13

Units

NOTE

Parameter

Symbol

min

max

13.91

Internal read command to first data

tAA

20

ns

(13.125)¹⁰

13.91

ACT to internal read or write delay time

PRE command period

tRCD

tRP

-

(13.125)¹⁰

13.91

(13.125)¹⁰

47.91

ACT to ACT or REF command period

ACT to PRE command period

tRC

(47.125)¹⁰

tRAS

34

9*tREFI

3.3

ns

nCK

CWL = 5

tCK(AVG)

2.5

1,2,3,8

CL = 6

CL = 7

CWL = 6

CWL = 7,8,9

CWL = 5

Reserved

1,2,3,4,8

4

CWL = 6

1.875

2.5

1,2,3,4,8

CWL = 7,8,9

CWL = 5

Reserved

4

CWL = 6

<2.5

1,2,3,8

CL = 8

CL = 9

CWL = 7

Reserved

1,2,3,4,8

CWL = 8,9

CWL = 5,6

CWL = 7

4

1.5

1.875

1,2,3,4,8

CWL = 8

Reserved

4

CWL = 9

4

CWL = 5,6

CWL = 7

CL = 10

CL = 11

1.5

<1.875

1.5

1,2,3,8

1,2,3,4,8

4

CWL = 8

Reserved

CWL = 5,6,7

CWL = 8

1.25

1,2,3,4,8

1,2,3,4

4

CWL = 9

Reserved

CWL = 5,6,7,8

CWL = 9

CL = 12

CL = 13

1,2,3,4

4

CWL = 5,6,7,8

CWL = 9

1.07

<1.25

1,2,3,9

Supported CL Settings

Supported CWL Settings

6,7,8,9,10,11,13

5,6,7,8,9

- 33 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

18.3.1 Speed Bin Table Notes

Absolute Specification (T_OPER; V_DDQ= V_DD= 1.5V +/- 0.075 V);

NOTE :

1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements

from CL setting as well as requirements from CWL setting.

2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guar-

anteed. An application should use the next smaller JEDEC standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],

rounding up to the next "SupportedCL".

3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or

1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.

4. "Reserved" settings are not allowed. User must program a different value.

5. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

6. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

8. Any DDR3-1866 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/

Characterization.

9. For devices supporting optional downshift to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125 ns or lower. SPD settings must be programmed to match. For example,

DDR3-1333(CL9) devices supporting downshift to DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte

20). DDR3-1600(CL11) devices supporting downshift to DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in SPD bytes for tAAmin (Byte16), tRCDmin (Byte

18), and tRPmin (Byte 20). DDR3-1866(CL13) devices supporting downshift to DDR3-1600(CL11) or DDR3-1333(CL9) or DDR3-1066(CL7) should program 13.125 ns in

SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600 devices supporting down binning to DDR3-1333 or DDR3-1066 should program

13.125ns in SPD byte for tAAmin (Byte 16), tRCDmin (Byte 18) and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be

programmed accodingly. For example, 49.125ns, (tRASmin + tRPmin = 36ns + 13.125ns) for DDR3-1333 and 48.125ns (tRASmin + tRPmin = 35ns + 13.125ns) for DDR3-

1600.

10. For devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin must be 13.125ns. SPD setting must be programed to match. For example,

DDR3-1866 devices supporting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for tAAmin(byte16), tRCDmin(Byte18) and tRP-

min (byte20). Once tRP (Byte20) is programmed to 13.125ns, tRCmin (Byte21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin =

34ns + 13.125ns)

- 34 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

19. Timing Parameters by Speed Grade

[ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)

Speed

Parameter

DDR3-800

DDR3-1066

MAX

DDR3-1333

MAX

Units

NOTE

Symbol

MIN

MAX

MIN

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

Average Clock Period

tCK(DLL_OFF)

tCK(avg)

8

-

8

-

8

-

ns

ps

6

See Speed Bins Table

tCK(avg)min +

tJIT(per)min

tCK(avg)max +

tJIT(per)max

tCK(avg)min +

tJIT(per)min

tCK(avg)max +

tJIT(per)max

tCK(avg)min +

tJIT(per)min

tCK(avg)max +

tJIT(per)max

Clock Period

tCK(abs)

ps

Average high pulse width

tCH(avg)

tCL(avg)

0.47

-100

-90

0.53

100

90

0.47

-90

0.53

90

0.47

-80

0.53

80

tCK(avg)

Average low pulse width

tCK(avg)

ps

Clock Period Jitter

tJIT(per)

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter

tJIT(per, lck)

tJIT(cc)

-80

80

-70

70

ps

200

180

160

140

ps

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

tJIT(cc, lck)

tERR(2per)

tERR(3per)

tERR(4per)

tERR(5per)

tERR(6per)

tERR(7per)

tERR(8per)

tERR(9per)

tERR(10per)

tERR(11per)

tERR(12per)

ps

- 147

- 175

- 194

- 209

- 222

- 232

- 241

- 249

- 257

- 263

- 269

147

175

194

209

222

232

241

249

257

263

269

- 132

- 157

- 175

- 188

- 200

- 209

- 217

- 224

- 231

- 237

- 242

132

157

175

188

200

209

217

224

231

237

242

- 118

- 140

- 155

- 168

- 177

- 186

- 193

- 200

- 205

- 210

- 215

118

140

155

168

177

186

193

200

205

210

215

ps

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max

Cumulative error across n = 13, 14 ... 49, 50 cycles

tERR(nper)

ps

24

Absolute clock HIGH pulse width

Absolute clock Low pulse width

Data Timing

tCH(abs)

tCL(abs)

0.43

-

0.43

-

0.43

-

tCK(avg)

25

26

DQS,DQS to DQ skew, per group, per access

DQ output hold time from DQS, DQS

DQ low-impedance time from CK, CK

DQ high-impedance time from CK, CK

tDQSQ

tQH

-

200

-

150

-

125

-

ps

tCK(avg)

ps

13

0.38

-800

-

0.38

-600

-

0.38

-500

-

13, g

tLZ(DQ)

tHZ(DQ)

400

300

250

13,14, f

ps

tDS(base)

AC175

75

-

25

75

-

ps

d, 17

Data setup time to DQS, DQS referenced

to V (AC)V (AC) levels

IH

IL

tDS(base)

AC150

125

30

Data hold time to DQS, DQS referenced

to V (DC)V (DC) levels

tDH(base)

DC100

150

600

100

490

65

-

ps

d, 17

28

-

IH

IL

DQ and DM Input pulse width for each input

Data Strobe Timing

tDIPW

400

-

DQS, DQS differential READ Preamble

tRPRE

tRPST

tQSH

0.9

0.3

NOTE 19

0.9

0.3

NOTE 19

0.9

0.3

NOTE 19

tCK

13, 19, g

11, 13, b

13, g

DQS, DQS differential READ Postamble

NOTE 11

DQS, DQS differential output high time

0.38

0.9

-

0.38

0.9

-

0.4

-

tCK(avg)

tCK

DQS, DQS differential output low time

tQSL

0.4

13, g

DQS, DQS differential WRITE Preamble

tWPRE

tWPST

tDQSCK

tLZ(DQS)

tHZ(DQS)

tDQSL

tDQSH

tDQSS

tDSS

-

0.9

-

DQS, DQS differential WRITE Postamble

DQS, DQS rising edge output access time from rising CK, CK

DQS, DQS low-impedance time (Referenced from RL-1)

DQS, DQS high-impedance time (Referenced from RL+BL/2)

DQS, DQS differential input low pulse width

DQS, DQS differential input high pulse width

DQS, DQS rising edge to CK, CK rising edge

DQS,DQS falling edge setup time to CK, CK rising edge

DQS,DQS falling edge hold time to CK, CK rising edge

0.3

-

0.3

-

0.3

-

tCK

-400

-800

-

400

0.55

0.25

-

-300

-600

-

300

0.55

0.25

-

-255

-500

-

255

250

0.55

0.25

-

ps

13,f

13,14,f

12,13,14

29, 31

30, 31

c

ps

0.45

-0.25

0.2

0.45

-0.25

0.2

0.45

-0.25

0.2

tCK

tCK(avg)

c, 32

tDSH

0.2

-

0.2

-

0.2

-

c, 32

- 35 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

[ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)

Speed

Parameter

Command and Address Timing

DLL locking time

DDR3-800

DDR3-1066

MAX

DDR3-1333

MAX

Units

NOTE

Symbol

MIN

MAX

MIN

tDLLK

tRTP

512

-

512

-

512

-

nCK

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

internal READ Command to PRECHARGE Command delay

e

(4nCK,7.5ns)

Delay from start of internal write transaction to internal read com-

mand

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

tWTR

-

e,18

e

WRITE recovery time

tWR

15

4

-

15

4

-

15

4

-

ns

Mode Register Set command cycle time

tMRD

nCK

max

(12nCK,15ns)

max

(12nCK,15ns)

max

(12nCK,15ns)

Mode Register Set command update delay

tMOD

-

CAS to CAS command delay

tCCD

tDAL(min)

tMPRR

tRAS

4

nCK

ns

Auto precharge write recovery + precharge time

Multi-Purpose Register Recovery Time

ACTIVE to PRECHARGE command period

WR + roundup (tRP / tCK(AVG))

1

-

1

-

1

-

22

e

See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42

max

(4nCK,10ns)

max

(4nCK,7.5ns)

max

(4nCK,6ns)

ACTIVE to ACTIVE command period for 1KB page size

ACTIVE to ACTIVE command period for 2KB page size

tRRD

-

e

max

(4nCK,10ns)

max

(4nCK,10ns)

max

(4nCK,7.5ns)

Four activate window for 1KB page size

Four activate window for 2KB page size

tFAW

40

50

-

37.5

50

-

30

45

-

ns

e

tIS(base)

AC175

200

125

65

-

ps

b,16

-

Command and Address setup time to CK, CK referenced to

V

(AC) / V (AC) levels

IH

IL

tIS(base)

AC150

200+150

125+150

65+125

b,16,27

Command and Address hold time from CK, CK referenced to

(DC) / V (DC) levels

tIH(base)

DC100

275

900

-

200

780

-

140

620

-

ps

b,16

28

V

IH

IL

Control & Address Input pulse width for each input

Calibration Timing

tIPW

Power-up and RESET calibration time

Normal operation Full calibration time

Normal operation short calibration time

Reset Timing

tZQinitI

tZQoper

tZQCS

512

256

64

-

512

256

64

-

512

256

64

-

nCK

23

max(5nCK,

tRFC + 10ns)

max(5nCK,

tRFC + 10ns)

max(5nCK,

tRFC + 10ns)

Exit Reset from CKE HIGH to a valid command

Self Refresh Timing

tXPR

-

max(5nCK,tRF

C + 10ns)

max(5nCK,tRF

C + 10ns)

max(5nCK,tRF

C + 10ns)

Exit Self Refresh to commands not requiring a locked DLL

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

tXS

-

tXSDLL

tCKESR

tDLLK(min)

nCK

tCKE(min) +

1tCK

tCKE(min) +

1tCK

tCKE(min) +

1tCK

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-

Down Entry (PDE)

max(5nCK,

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

tCKSRE

tCKSRX

-

Valid Clock Requirement before Self Refresh Exit (SRX) or Power-

Down Exit (PDX) or Reset Exit

max(5nCK,

10ns)

max(5nCK,

10ns)

max(5nCK,

10ns)

- 36 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

[ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333

Speed

DDR3-800

DDR3-1066

DDR3-1333

MAX

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

MIN

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Pre-

charge Power Down with DLL

frozen to commands not requiring a locked DLL

max

(3nCK,

7.5ns)

max

(3nCK,

7.5ns)

max

(3nCK,6ns)

tXP

tXPDLL

tCKE

-

max

(10nCK,

24ns)

max

(10nCK,

24ns)

max

(10nCK,

24ns)

Exit Precharge Power Down with DLL frozen to commands re-

quiring a locked DLL

2

max

(3nCK,

7.5ns)

max

(3nCK,

5.625ns)

max

(3nCK,

5.625ns)

CKE minimum pulse width

Command pass disable delay

tCPDED

tPD

1

-

1

-

1

-

nCK

tCK

Power Down Entry to Exit Timing

tCKE(min)

9*tREFI

tCKE(min)

9*tREFI

tCKE(min)

9*tREFI

15

20

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power Down entry

tACTPDEN

tPRPDEN

tRDPDEN

1

-

1

-

1

-

nCK

RL + 4 +1

WL + 4

+(tWR/

tCK(avg))

WL + 4

+(tWR/

tCK(avg))

WL + 4

+(tWR/

tCK(avg))

Timing of WR command to Power Down entry

(BL8OTF, BL8MRS, BC4OTF)

tWRPDEN

tWRAPDEN

tWRPDEN

tWRAPDEN

-

nCK

9

10

9

Timing of WRA command to Power Down entry

(BL8OTF, BL8MRS, BC4OTF)

WL+4+WR +1

WL+4+WR+1

WL + 2

+(tWR/

tCK(avg))

WL + 2

+(tWR/

tCK(avg))

WL + 2

+(tWR/

tCK(avg))

Timing of WR command to Power Down entry

(BC4MRS)

Timing of WRA command to Power Down entry

(BC4MRS)

WL +2 +WR

+1

WL +2 +WR

+1

WL +2 +WR

+1

10

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry

ODT Timing

tREFPDEN

tMRSPDEN

1

-

1

-

1

-

20,21

tMOD(min)

ODT high time without write command or with write command

and BC4

ODTH4

ODTH8

tAONPD

4

6

2

-

4

6

2

-

4

6

2

-

nCK

ns

ODT high time with Write command and BL8

Asynchronous RTT turn-on delay (Power-Down with DLL fro-

zen)

8.5

Asynchronous RTT turn-off delay (Power-Down with DLL fro-

zen)

tAOFPD

2

8.5

2

8.5

2

8.5

ns

RTT turn-on

tAON

tAOF

tADC

-400

0.3

400

0.7

-300

0.3

300

0.7

-250

0.3

250

0.7

ps

7,f

8,f

f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference

RTT dynamic change skew

tCK(avg)

0.3

Write Leveling Timing

First DQS/DQS rising edge after write leveling mode is pro-

grammed

tWLMRD

tWLDQSEN

tWLS

40

25

-

40

25

-

40

25

-

tCK

ps

3

DQS/DQS delay after write leveling mode is programmed

Write leveling setup time from rising CK, CK crossing to rising

DQS, DQS crossing

325

245

195

Write leveling hold time from rising DQS, DQS crossing to rising

CK, CK crossing

tWLH

325

-

245

-

195

-

ps

Write leveling output delay

Write leveling output error

tWLO

0

9

2

0

9

2

0

9

2

ns

tWLOE

- 37 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

[ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.)

Speed

Parameter

DDR3-1600

DDR3-1866

Units

NOTE

Symbol

MIN

MAX

MIN

MAX

Clock Timing

Minimum Clock Cycle Time (DLL off mode)

Average Clock Period

tCK(DLL_OFF)

tCK(avg)

8

-

8

-

ns

ps

6

See Speed Bins Table

tCK(avg)max +

tJIT(per)max

tCK(avg)min +

tJIT(per)min

tCK(avg)max +

tJIT(per)max

tCK(avg)min + tJIT(per)min

Clock Period

tCK(abs)

ps

Average high pulse width

tCH(avg)

tCL(avg)

0.47

-70

0.53

70

0.47

-60

0.53

60

tCK(avg)

Average low pulse width

tCK(avg)

ps

Clock Period Jitter

tJIT(per)

Clock Period Jitter during DLL locking period

Cycle to Cycle Period Jitter

tJIT(per, lck)

tJIT(cc)

-60

60

-50

50

ps

140

120

100

ps

Cycle to Cycle Period Jitter during DLL locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across 6 cycles

Cumulative error across 7 cycles

Cumulative error across 8 cycles

Cumulative error across 9 cycles

Cumulative error across 10 cycles

Cumulative error across 11 cycles

Cumulative error across 12 cycles

tJIT(cc, lck)

tERR(2per)

tERR(3per)

tERR(4per)

tERR(5per)

tERR(6per)

tERR(7per)

tERR(8per)

tERR(9per)

tERR(10per)

tERR(11per)

tERR(12per)

ps

-103

-122

-136

-147

-155

-163

-169

-175

-180

-184

-188

103

122

136

147

155

163

169

175

180

184

188

-88

88

ps

-105

-117

-126

-133

-139

-145

-150

-154

-158

-161

105

117

126

133

139

145

150

154

158

161

ps

tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min

tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max

Cumulative error across n = 13, 14 ... 49, 50 cycles

tERR(nper)

ps

24

Absolute clock HIGH pulse width

Absolute clock Low pulse width

Data Timing

tCH(abs)

tCL(abs)

0.43

-

0.43

-

tCK(avg)

25

26

DQS,DQS to DQ skew, per group, per access

DQ output hold time from DQS, DQS

DQ low-impedance time from CK, CK

DQ high-impedance time from CK, CK

tDQSQ

tQH

-

100

-

85

-

ps

tCK(avg)

ps

13

0.38

-450

-

0.38

-390

-

13, g

tLZ(DQ)

tHZ(DQ)

225

195

13,14, f

ps

tDS(base)

AC150

10

-

ps

d, 17

-

Data setup time to DQS, DQS referenced to V (AC)V (AC) lev-

els

IH

IL

tDS(base)

AC135

0

tDH(base)

DC100

Data hold time to DQS, DQS referenced to V (DC)V (DC) levels

45

-

20

ps

d, 17

28

-

IH

IL

DQ and DM Input pulse width for each input

Data Strobe Timing

tDIPW

360

320

-

DQS, DQS differential READ Preamble

DQS, DQS differential READ Postamble

DQS, DQS differential output high time

DQS, DQS differential output low time

DQS, DQS differential WRITE Preamble

DQS, DQS differential WRITE Postamble

tRPRE

tRPST

tQSH

0.9

0.3

NOTE 19

0.9

0.3

NOTE 19

tCK

13, 19, g

11, 13, b

13, g

NOTE 11

0.4

-

0.4

-

tCK(avg)

tCK

tQSL

0.4

-

0.4

13, g

tWPRE

tWPST

tDQSCK

tLZ(DQS)

tHZ(DQS)

tDQSL

tDQSH

tDQSS

tDSS

0.9

-

0.3

-

0.3

-

tCK

DQS, DQS rising edge output access time from rising CK, CK

DQS, DQS low-impedance time (Referenced from RL-1)

DQS, DQS high-impedance time (Referenced from RL+BL/2)

DQS, DQS differential input low pulse width

-225

-450

-

225

-195

-390

-

195

0.55

0.27

-

ps

13,f

13,14,f

12,13,14

29, 31

30, 31

c

225

ps

225

ps

0.45

-0.27

0.9

0.55

0.27

NOTE 19

NOTE 11

0.45

-0.27

0.18

tCK

DQS, DQS differential input high pulse width

tCK

DQS, DQS rising edge to CK, CK rising edge

tCK(avg)

DQS,DQS falling edge setup time to CK, CK rising edge

DQS,DQS falling edge hold time to CK, CK rising edge

c, 32

tDSH

0.3

-

c, 32

- 38 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

[ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866 (Cont.)

Speed

Parameter

Command and Address Timing

DLL locking time

DDR3-1600

DDR3-1866

Units

NOTE

Symbol

MIN

MAX

MIN

MAX

tDLLK

tRTP

512

-

512

-

nCK

max

internal READ Command to PRECHARGE Command delay

e

(4nCK,7.5ns)

Delay from start of internal write transaction to internal read com-

mand

max

(4nCK,7.5ns)

max

(4nCK,7.5ns)

tWTR

-

e,18

e

WRITE recovery time

tWR

15

4

-

15

4

-

ns

Mode Register Set command cycle time

tMRD

nCK

max

(12nCK,15ns)

max

(12nCK,15ns)

Mode Register Set command update delay

CAS to CAS command delay

tMOD

tCCD

-

4

nCK

WR + roundup (tRP /

tCK(AVG))

Auto precharge write recovery + precharge time

tDAL(min)

Multi-Purpose Register Recovery Time

tMPRR

tRAS

1

-

1

-

nCK

ns

22

e

ACTIVE to PRECHARGE command period

See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42

max

(4nCK,6ns)

max

(4nCK, 5ns)

ACTIVE to ACTIVE command period for 1KB page size

ACTIVE to ACTIVE command period for 2KB page size

tRRD

-

e

max

(4nCK,7.5ns)

max

(4nCK, 6ns)

Four activate window for 1KB page size

Four activate window for 2KB page size

tFAW

30

40

-

27

35

-

ns

e

tIS(base)

AC175

45

-

ps

b,16

-

tIS(base)

AC150

170

Command and Address setup time to CK, CK referenced to

V

(AC) / V (AC) levels

IH

IL

tIS(base)

AC135

-

65

150

b,16

tIS(base)

AC125

b,16,27

-

Command and Address hold time from CK, CK referenced to

(DC) / V (DC) levels

tIH(base)

DC100

120

560

-

100

535

-

ps

b,16

28

V

IH

IL

Control & Address Input pulse width for each input

Calibration Timing

tIPW

Power-up and RESET calibration time

Normal operation Full calibration time

Normal operation short calibration time

Reset Timing

tZQinitI

tZQoper

tZQCS

512

256

64

-

max(512nCK,640ns)

max(256nCK,320ns)

max(64nCK,80ns)

-

nCK

23

max(5nCK, tRFC +

10ns)

max(5nCK, tRFC +

10ns)

Exit Reset from CKE HIGH to a valid command

Self Refresh Timing

tXPR

-

max(5nCK,tRFC +

10ns)

max(5nCK,tRFC +

10ns)

Exit Self Refresh to commands not requiring a locked DLL

tXS

-

Exit Self Refresh to commands requiring a locked DLL

Minimum CKE low width for Self refresh entry to exit timing

tXSDLL

tCKESR

tDLLK(min)

-

tDLLK(min)

-

nCK

tCKE(min) + 1tCK

tCKE(min) + 1nCK

Valid Clock Requirement after Self Refresh Entry (SRE) or Power-

Down Entry (PDE)

max(5nCK,

10ns)

max(5nCK,

10ns)

tCKSRE

tCKSRX

-

Valid Clock Requirement before Self Refresh Exit (SRX) or Power-

Down Exit (PDX) or Reset Exit

max(5nCK,

10ns)

max(5nCK,

10ns)

- 39 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

[ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866

Speed

DDR3-1600

DDR3-1866

Units

NOTE

Parameter

Symbol

MIN

MAX

MIN

MAX

Power Down Timing

Exit Power Down with DLL on to any valid command;Exit Pre-

charge Power Down with DLL

frozen to commands not requiring a locked DLL

max

(3nCK,6ns)

tXP

-

max(3nCK,6ns)

-

max

(10nCK,

24ns)

Exit Precharge Power Down with DLL frozen to commands re-

quiring a locked DLL

tXPDLL

tCKE

-

max(10nCK,24ns)

max(3nCK,5ns)

-

2

max

(3nCK,5ns)

CKE minimum pulse width

Command pass disable delay

tCPDED

tPD

1

-

2

-

nCK

tCK

Power Down Entry to Exit Timing

tCKE(min)

9*tREFI

tCKE(min)

9*tREFI

15

20

Timing of ACT command to Power Down entry

Timing of PRE command to Power Down entry

Timing of RD/RDA command to Power Down entry

tACTPDEN

tPRPDEN

tRDPDEN

1

-

1

-

nCK

RL + 4 +1

Timing of WR command to Power Down entry

(BL8OTF, BL8MRS, BC4OTF)

WL + 4 +(tWR/

tCK(avg))

WL + 4 +(tWR/

tCK(avg))

tWRPDEN

tWRAPDEN

tWRPDEN

tWRAPDEN

-

nCK

9

10

9

Timing of WRA command to Power Down entry

(BL8OTF, BL8MRS, BC4OTF)

WL + 4 +WR +1

Timing of WR command to Power Down entry

(BC4MRS)

WL + 2 +(tWR/

tCK(avg))

WL + 2 +(tWR/

tCK(avg))

Timing of WRA command to Power Down entry

(BC4MRS)

WL +2 +WR +1

10

Timing of REF command to Power Down entry

Timing of MRS command to Power Down entry

ODT Timing

tREFPDEN

tMRSPDEN

1

-

1

-

20,21

tMOD(min)

ODT high time without write command or with write command

and BC4

ODTH4

ODTH8

tAONPD

4

6

2

-

4

6

2

-

nCK

ns

ODT high time with Write command and BL8

Asynchronous RTT turn-on delay (Power-Down with DLL fro-

zen)

8.5

Asynchronous RTT turn-off delay (Power-Down with DLL fro-

zen)

tAOFPD

2

8.5

2

8.5

ns

RTT turn-on

tAON

tAOF

tADC

-225

0.3

225

0.7

-195

0.3

195

0.7

ps

7,f

8,f

f

RTT_NOM and RTT_WR turn-off time from ODTLoff reference

RTT dynamic change skew

tCK(avg)

0.3

Write Leveling Timing

First DQS/DQS rising edge after write leveling mode is pro-

grammed

tWLMRD

tWLDQSEN

tWLS

40

25

-

40

25

-

tCK

ps

3

DQS/DQS delay after write leveling mode is programmed

Write leveling setup time from rising CK, CK crossing to rising

DQS, DQS crossing

165

140

Write leveling hold time from rising DQS, DQS crossing to rising

CK, CK crossing

tWLH

165

-

140

-

ps

Write leveling output delay

Write leveling output error

tWLO

0

7.5

2

0

7.5

2

ns

tWLOE

- 40 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

19.1 Jitter Notes

Specific Note a

Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the

input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm,

another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.

Specific Note b

These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition

edge to its respective clock signal (CK/CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.

tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is,

these parameters should be met whether clock jitter is present or not.

Specific Note c

These parameters are measured from a data strobe signal (DQS, DQS) crossing to its respective clock signal (CK, CK) crossing.

The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the

clock signal crossing. That is, these parameters should be met whether clock jitter is present or not.

Specific Note d

Specific Note e

These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal

(DQS, DQS) crossing.

For these parameters, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock

cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)},

which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the

device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifications are met, i.e. Precharge com-

mand at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter.

Specific Note f

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input

clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.)

For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = +

193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(der-

ated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to

tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the

min/max usage!)

Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <=

12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12.

Specific Note g

When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input

clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has

tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min +

tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) =

tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/

max usage!)

- 41 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

19.2 Timing Parameter Notes

1. Actual value dependant upon measurement level definitions which are TBD.

2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.

3. The max values are system dependent.

4. WR as programmed in mode register

5. Value must be rounded-up to next higher integer value

6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.

7. For definition of RTT turn-on time tAON see "Device Operation & Timing Diagram Datasheet"

8. For definition of RTT turn-off time tAOF see "Device Operation & Timing Diagram Datasheet".

9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.

10. WR in clock cycles as programmed in MR0

11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. See "Device Operation & Timing

Diagram Datasheet.

12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated

by TBD

13. Value is only valid for RON34

14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method.

15. tREFI depends on T

OPER

16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals,

(DC) = V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).

V

REF

See "Address/Command Setup, Hold and Derating" on component datasheet.

17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals,

(DC)= V DQ(DC). For input only pins except RESET, V (DC)=V CA(DC).

V

REF

See "Data Setup, Hold and Slew Rate Derating" on component datasheet.

18. Start of internal write transaction is defined as follows ;

For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL.

For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL

For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL

19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation & Timing Diagram

Datasheet"

20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down

IDD spec will not be applied until finishing those operations.

21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time

such as tXPDLL(min) is also required. See "Device Operation & Timing Diagram Datasheet".

22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.

23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming

the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The

appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters.

One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub-

ject to in the application, is illustrated. The interval could be defined by the following formula:

ZQCorrection

(TSens x Tdriftrate) + (VSens x Vdriftrate)

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities.

For example, if TSens = 1.5% /°C, VSens = 0.15% / mV, Tdriftrate = 1°C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu-

lated as:

0.5

~

= 0.133

128ms

(1.5 x 1) + (0.15 x 15)

24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.

25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge.

26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge.

27. The tIS(base) AC150 specifications are adjusted from the tIS(base) AC175 specification by adding an additional 125 ps for DDR3-800/1066 or 100ps for DDR3-

1333/1600 of derating to accommodate for the lower alternate threshold of 150mV and another 25ps to account for the earlier reference point [(175mv - 150

mV) / 1 V/ns].

28. Pulse width of a input signal is defined as the width between the first crossing of V

(DC) and the consecutive crossing of V

(DC)

REF

29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge.

30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge.

31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

33. The tIS(base) AC125 specifications are adjusted from the tIS(base) AC135 specification by adding an additional 75ps for DDR3-1866 to accommodate for the

lower alternate threshold of 125mV and another 10ps to account for the earlier reference point [(135mv - 125mV) / 1 V/ns].

- 42 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

20. Physical Dimensions

20.1 256Mbx8 based 256Mx72 Module (1 Rank) - M392B5773DH0

Units : Millimeters

133.35 ± 0.15

128.95

C

Max 4.0

9.76

20.92

32.40

20.93

9.74

54.675

A

B

1.0 max

47.00

71.00

1.27 ± 0.10

SPD/TS

18.10

5.00

0.80 ± 0.05

9.9

3.80

0.2 ± 0.15

1.50±0.10

1.00

2.50

Detail A

Detail B

Detail C

20.1.1 x72 DIMM, populated as one physical rank of x8 DDR3 SDRAMs

Address, Command and Control lines

NOTE : DRAMs indicated with dotted outline are located on the backside of the module.

The used device is 256M x8 DDR3 SDRAM, FBGA.

DDR3 SDRAM Part NO : K4B2G0846D-HC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

- 43 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

20.2 256Mbx8 based 512Mx72 Module (2 Ranks) - M392B5273DH0

Units : Millimeters

133.35 ± 0.15

128.95

C

Max 4.0

9.76

20.92

32.40

20.93

9.74

54.675

A

B

1.0 max

47.00

71.00

1.27 ± 0.10

SPD/TS

18.10

5.00

0.80 ± 0.05

9.9

3.80

0.2 ± 0.15

1.50±0.10

1.00

2.50

Detail A

Detail B

Detail C

20.2.1 x72 DIMM, populated as two physical ranks of x8 DDR3 SDRAMs

SPD/TS

Address, Command and Control lines

The used device is 512M x4 DDR3 SDRAM, FBGA.

DDR3 SDRAM Part NO : K4B2G0846D-HC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

- 44 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

20.3 512Mbx4 based 512Mx72 Module (1 Rank) - M392B5270DH0

Units : Millimeters

133.35 ± 0.15

128.95

C

Max 4.0

9.76

20.92

32.40

20.93

9.74

54.675

A

B

1.0 max

47.00

71.00

1.27 ± 0.10

SPD/TS

18.10

5.00

0.80 ± 0.05

9.9

3.80

0.2 ± 0.15

1.50±0.10

1.00

2.50

Detail A

Detail B

Detail C

20.3.1 x72 DIMM, populated as one physical rank of x4 DDR3 SDRAMs

SPD/TS

Address, Command and Control lines

The used device is 512M x4 DDR3 SDRAM, FBGA.

DDR3 SDRAM Part NO : K4B2G0446D-HC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

- 45 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

20.4 1Gbx4(DDP) based 1Gx72 Module (2 Ranks) - M392B1K70DM0

Units : Millimeters

133.35 ± 0.15

128.95

C

Max 4.0

9.76

20.92

32.40

20.93

9.74

54.675

A

B

1.0 max

47.00

71.00

1.27 ± 0.10

SPD/TS

18.10

5.00

0.80 ± 0.05

9.9

3.80

0.2 ± 0.15

1.50±0.10

1.00

2.50

Detail A

Detail B

Detail C

20.4.1 x72 DIMM, populated as two physical ranks of x4 DDR3 SDRAMs

SPD/TS

Address, Command and Control lines

The used device is 1G x4(DDP) DDR3 SDRAM, FBGA.

DDR3 SDRAM Part NO : K4B4G0446D-MC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

- 46 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

20.5 512Mbx8(DDP) based 1Gx72 Module (4 Ranks) - M392B1K73DM0

Units : Millimeters

133.35 ± 0.15

128.95

C

Max 4.0

9.76

20.92

32.40

20.93

9.74

54.675

A

B

1.0 max

47.00

71.00

1.27 ± 0.10

SPD/TS

18.10

5.00

0.80 ± 0.05

9.9

3.80

0.2 ± 0.15

1.50±0.10

1.00

2.50

Detail A

Detail B

Detail C

20.5.1 x72 DIMM, populated as four physical ranks of x8 DDR3 SDRAMs

SPD/TS

Address, Command and Control lines

The used device is 512M x8(DDP) DDR3 SDRAM, FBGA.

DDR3 SDRAM Part NO : K4B4G0846D-MC**

* NOTE : Tolerances on all dimensions ±0.15 unless otherwise specified.

- 47 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

20.5.2 Heat Spreader Design Guide

1. FRONT PART

Outside

130.45

67

8.69

20.82

17.9

6.4

20.82

8.69

Driver

IC(DP:0.18mm)

DRIVER IC 0.18 -0/+0.1

Inside

Driver

IC(DP:0.18mm)

2. BACK PART

Outside

Driver

IC(DP:0.18mm)

Inside

Driver

IC(DP:0.18mm)

- 48 -

Rev. 1.3

VLP Registered DIMM

datasheet

DDR3 SDRAM

3. CLIP PART

35.82

7.2 ± 0.1

Clip open size

3.0~4.3

0.1

SIDE-L

FRONT

SIDE-R

4. ASS’Y VIEW

Reference thickness total (Maximum) : 7.55 (With Clip thickness)

TIM Thickness 0.25

- 49 -


型号：	M392B5270DH0-CH9
厂家：	SAMSUNG
描述：	DDR DRAM Module, 512MX72, 20ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240 时钟动态存储器双倍数据速率内存集成电路
文件：	总49页 (文件大小：1440K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M392B5270DH0-CH9 [SAMSUNG]

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