M393T2950CZA-E6 [SAMSUNG]
Cache DRAM Module, 128MX72, 0.45ns, CMOS, ROHS COMPLIANT, DIMM-240;
| 型号： | M393T2950CZA-E6 |
| 厂家： | 
SAMSUNG |
| 描述： | Cache DRAM Module, 128MX72, 0.45ns, CMOS, ROHS COMPLIANT, DIMM-240 动态存储器 |
| 文件： | 总27页 (文件大小：600K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 512Mb C-die
72-bit ECC
60FBGA with Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.6 Dec. 2006
1 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Table of Contents
1.0 DDR2 Registered DIMM Ordering Information ..........................................................................4
2.0 Features........................................................................................................................................ 4
3.0 Address Configuration ................................................................................................................4
4.0 Pin Configurations (Front side/Back side) .................................................................................5
5.0 Pin Description .............................................................................................................................5
6.0 Input/Output Function Description .............................................................................................6
7.0 Functional Block Diagram............................................................................................................7
7.1 512MB, 64Mx72 Module (M393T6553CZ3 / M393T6553CZA / M392T6553CZA) ..................................... 7
7.2 1GB, 128Mx72 Module (M393T2953CZ3 / M393T2953CZA / M392T2953CZA) .......................................8
7.3 1GB, 128Mx72 Module (M393T2950CZ3 / M393T2950CZA / M392T2950CZA)........................................9
7.4 2GB, 256Mx72 Module (M393T5750CZ3 / M393T5750CZA)...............................................................10
8.0 Absolute Maximum DC Ratings ................................................................................................11
9.0 AC & DC Operating Conditions .................................................................................................11
9.1 Operating Temperature Condition ................................................................................................12
9.2 Input DC Logic Level ..................................................................................................................12
9.3 Input AC Logic Level ..................................................................................................................12
9.4 AC Input Test Conditions ............................................................................................................12
10.0 IDD Specification Parameters Definition................................................................................13
11.0 Operating Current Table(TA=0°C, VDD= 1.9V).......................................................................14
11.1 M393T6553CZ3 / M393T6553CZA / M392T6553CZA ........................................................................14
11.2 M393T6553CZ3 / M393T6553CZA / M392T6553CZA - considering Register and PLL current value........14
11.3 M393T2953CZ3 / M393T2953CZA / M392T2953CZA ........................................................................15
11.4 M393T2953CZ3 / M393T2953CZA / M392T2953CZA - considering Register and PLL current value........15
11.5 M393T2950CZ3 / M393T2950CZA / M392T2950CZA ........................................................................16
11.6 M393T2950CZ3 / M393T2950CZA / M392T2950CZA - considering Register and PLL current value........16
11.7 M393T5750CZ3 / M393T5750CZA .................................................................................................17
11.8 M393T5750CZ3 / M393T5750CZA - considering Register and PLL current value ................................17
12.0 Input/Output Capacitance .......................................................................................................18
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400..................................... 19
13.1 Refresh Parameters by Device Density........................................................................................ 19
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .............................................19
13.3 Timing Parameters by Speed Grade ............................................................................................19
14.0 Physical Dimensions............................................................................................................... 21
14.1 64Mbx8 based 64Mx72 Module (1 Rank) .......................................................................................21
14.2 64Mbx8 based 64Mx72 Module (1 Rank) ...................................................................................... 22
14.3 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks)....................................................................23
14.4 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks)....................................................................24
14.5 128Mbx4 based 256Mx72 Module (2 Ranks) ..................................................................................25
15.0 240 Pin DDR2 Registered DIMM Clock Topology ..................................................................26
Rev. 1.6 Dec. 2006
2 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
Revision History
Revision
1.0
Month
Apr.
Year
2005
2005
2005
History
- Initial Release
- Revised the Ordering Information
- Revised the IDD Current Values
1.1
Jul.
1.2
Aug.
- Revised the IDD Current Values
- Added VLP RDIMM product
1.3
Mar.
2006
1.4
1.5
1.6
Jun.
Jul.
Dec.
2006
2006
2006
- Revised the IDD Current Format
- Added new JEDEC Gerber for high speed bin of 2GB (x4 2R)
- Added 800 CL6 speed bin
Rev. 1.6 Dec. 2006
3 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
1.0 DDR2 Registered DIMM Ordering Information
Part Number
Density Organization
Component Composition
64Mx8(K4T51083QC)*9EA
64Mx8(K4T51083QC)*9EA
64Mx8(K4T51083QC)*9EA
64Mx8(K4T51083QC)*18EA
64Mx8(K4T51083QC)*18EA
64Mx8(K4T51083QC)*18EA
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*36EA
128Mx4(K4T51043QC)*36EA
Number of Rank Parity Register
Height
M393T6553CZ3-CD5/CC
512MB
512MB
512MB
1GB
64Mx72
64Mx72
1
1
1
2
2
2
1
1
1
2
2
X
O
O
X
30.00mm
30.00mm
18.30mm
30.00mm
30.00mm
18.30mm
30.00mm
30.00mm
18.30mm
30.00mm
30.00mm
M393T6553CZA-CF7/E6/D5/CC
M392T6553CZA-CF7/E6/D5/CC
M393T2953CZ3-CD5/CC
64Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
M393T2953CZA-CF7/E6/D5/CC
M392T2953CZA-CF7/E6/D5/CC
M393T2950CZ3-CD5/CC
1GB
O
O
X
1GB
1GB
M393T2950CZA-CF7/E6/D5/CC
M392T2950CZA-CF7/E6/D5/CC
M393T5750CZ3-CD5/CC
1GB
O
O
X
1GB
2GB
M393T5750CZA-CF7/E6/D5/CC
2GB
O
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Note: "A" of Part number(12th digit) stand for Parity Register products.
Note: "92" of Part number(3~4th digit) stand for VLP(Very Low Profile) Register products.
2.0 Features
•
Performance range
F7(DDR2-800)
E6(DDR2-667)
D5(DDR2-533)
CC(DDR2-400)
Unit
Mbps
Mbps
Mbps
Mbps
CK
Speed@CL3
Speed@CL4
Speed@CL5
Speed@CL6
CL-tRCD-tRP
-
400
533
667
-
400
533
-
400
400
-
400
533
800
6-6-6
-
-
5-5-5
4-4-4
3-3-3
•
•
JEDEC standard 1.8V ± 0.1V Power Supply
= 1.8V ± 0.1V
V
DDQ
•
200 MHz f for 400Mb/sec/pin, 267MHz f for 533Mb/sec/pin, 333MHz f for 667Mb/sec/pin, 400MHz f for 800Mb/sec/pin
CK CK CK CK
•
•
•
•
•
•
•
•
•
•
•
•
4 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5, 6
Programmable Additive Latency: 0, 1 , 2 , 3 ,4 and 5
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination with selectable values(50/75/150 ohms or disable)
PASR(Partial Array Self Refresh)
Average Refresh Period 7.8us at lower than T
- support High Temperature Self-Refresh rate enable feature
85°C, 3.9us at 85°C < T
< 95 °C
CASE
CASE
•
•
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
•
All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
3.0 Address Configuration
Organization
Row Address
A0-A13
Column Address
A0-A9,A11
A0-A9
Bank Address
BA0-BA1
Auto Precharge
128Mx4(512Mb) based Module
64Mx8(512Mb) based Module
A10
A10
A0-A13
BA0-BA1
Rev. 1.6 Dec. 2006
4 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
4.0 Pin Configurations (Front side/Back side)
Pin
1
Front
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
Back
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Front
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
Back
Pin
61
62
63
64
Front
Pin
181
182
183
184
Back
Pin
91
92
93
94
95
96
97
98
Front
Pin
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
Back
V
V
V
V
V
V
DQ19
A4
DM5/DQS14
NC/DQS14
REF
SS
SS
DDQ
SS
V
V
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
DQ4
DQ5
V
DQ28
DQ29
V
A3
A1
DQS5
DQS5
SS
SS
DDQ
V
DQ0
DQ1
V
DQ24
DQ25
A2
SS
V
V
V
DQ46
DQ47
SS
SS
DD
DD
SS
V
DM0/DQS9
NC/DQS9
DM3/DQS12
NC/DQS12
KEY
DQ42
DQ43
SS
SS
V
V
DQS0
DQS0
V
DQS3
DQS3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
CK0
CK0
SS
SS
V
V
V
V
DQ52
DQ53
SS
SS
SS
SS
V
V
V
DQ6
DQ7
V
DQ30
DQ31
V
DQ48
DQ49
SS
SS
DD
DD
V
DQ2
DQ3
V
DQ26
DQ27
NC/Par_In
A0
99
SS
V
V
V
100
101
102
103
104
105
106
107
108
109
110
111
112
113
RFU
RFU
SS
SS
DD
DD
SS
V
DQ12
DQ13
V
CB4
CB5
V
A10/AP
BA0
BA1
SA2
NC(TEST)
SS
SS
V
V
DQ8
DQ9
V
CB0
CB1
DDQ
SS
V
V
RAS
S0
DM6/DQS15
NC/DQS15
SS
SS
DDQ
SS
V
DM1/DQS10
NC/DQS10
DM8/DQS17
NC/DQS17
WE
CAS
DQS6
DQS6
SS
SS
V
V
DQS1
DQS1
V
DQS8
DQS8
DDQ
SS
V
V
V
V
ODT0
A13
DQ54
DQ55
SS
SS
DDQ
SS
4
V
RFU
RFU
V
CB6
CB7
V
DQ50
DQ51
S1
SS
SS
V
V
RESET
NC
V
CB2
CB3
ODT1
DD
SS
V
V
V
DQ60
DQ61
SS
SS
DDQ
SS
SS
V
V
V
DQ14
DQ15
V
DQ36
DQ37
DQ56
DQ57
SS
SS
DDQ
SS
4
V
V
DQ10
DQ11
V
DQ32
DQ33
CKE1
DDQ
SS
V
V
V
CKE0
DM7/DQS16
NC/DQS16
SS
DD
SS
SS
V
V
DQ20
DQ21
DM4/DQS13
NC/DQS13
DQS7
DQS7
NC
NC
SS
DD
SS
V
24
25
26
27
28
29
30
DQ16
DQ17
144
145
146
147
148
149
150
54
55
56
57
58
59
60
NC
174
175
176
177
178
179
180
83
84
85
86
87
88
89
90
DQS4
DQS4
203
204
205
206
207
208
209
210
114
115
116
117
118
119
120
234
235
236
237
238
239
240
SS
V
V
V
V
NC/Err_Out
DQ62
DQ63
SS
DDQ
SS
SS
V
V
V
DM2/DQS11
NC/DQS11
A12
A9
DQ38
DQ39
DQ58
DQ59
SS
DDQ
SS
V
DQS2
DQS2
A11
A7
DQ34
DQ35
SS
V
V
V
V
VDDSPD
SA0
SA1
SS
DD
SS
SS
V
DQ18
V
A5
V
DQ22
DQ23
A8
A6
DQ44
DQ45
SDA
SCL
SS
DD
SS
DQ40
DQ41
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The TEST pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are optional function to check address and command parity.
4. CKE1,S1 Pin is used for double side Registered DIMM.
5.0 Pin Description
Pin Name
Description
Pin Name
Description
CK0
Clock Input, positive line
Clock input, negative line
Clock Enables
ODT0~ODT1
DQ0~DQ63
CB0~CB7
On die termination Inputs
Data Input/Output
CK0
CKE0, CKE1
RAS
Data check bits Input/Output
Data strobes
Row Address Strobe
Column Address Strobe
Write Enable
DQS0~DQS8
DQS0~DQS8
CAS
Data strobes, negative line
WE
DM(0~8),DQS(9~17) Data Masks / Data strobes (Read)
S0, S1
Chip Selects
DQS9~DQS17
Data strobes (Read), negative line
Reserved for Future Use
No Connect
A0~A9, A11~A15
A10/AP
Address Inputs
RFU
NC
Address Input/Autoprecharge
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
BA0, BA1
DDR2 SDRAM Bank Address
TEST
SCL
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
V
V
V
V
V
Core Power
I/O Power
DD
SDA
DDQ
SS
SA0~SA2
Par_In
Err_Out
RESET
SPD address Inputs
Ground
Parity bit for the Address and Control bus
Parity error found on the Address and Control bus
Register and PLL control pin
Input/Output Reference
SPD Power
REF
DDSPD
* The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.6 Dec. 2006
5 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
6.0 Input/Output Function Description
Symbol
CK0
Type
Input
Input
Function
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
CK0
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self Refresh mode.
CKE0~CKE1
S0~S1
Input
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled,
new commands are ignored but previous operations continue.
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are
high.
Input
ODT0~ODT1
Input
Input
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the
SDRAM.
RAS, CAS, WE
V
Supply
Supply
Input
Reference voltage for SSTL_18 inputs
REF
V
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of four is activated.
DDQ
BA0~BA1
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected
and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be pre-
charged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.
A0~A9,A10/AP
A11~A13
Input
DQ0~63,
In/Out
Input
Data and Check Bit Input/Output pins
CB0~CB7
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once
the write command is registered into the SDRAM.
DM0~DM8
V
, V
Supply
In/Out
In/Out
Input
Power and ground for the DDR SDRAM input buffers and core logic
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
DD
SS
DQS0~DQS17
DQS0~DQS17
SA0~SA2
These signals are tied at the system planar to either V or V
to configure the serial SPD EEPROM address range.
DDSPD
SS
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA
bus line to V to act as a pullup.
SDA
SCL
In/Out
Input
DDSPD
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to V to act as a pullup.
DDSPD
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6
Volt operation).
V
Supply
DDSPD
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-
nized with the input clock )
RESET
Input
Par_In
Err_Out
TEST
Input
Output
In/Out
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
Used by memory bus analysis tools (unused on memory DIMMs)
Rev. 1.6 Dec. 2006
6 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
7.0 Functional Block Diagram
7.1 512MB, 64Mx72 Module (M393T6553CZ3 / M393T6553CZA / M392T6553CZA)
(populated as 1 rank of x8 DDR2 SDRAMs)
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
NC/DQS9
DM4/DQS13
NC/DQS13
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS1
DQS5
DQS1
DQS5
DM1/DQS10
NC/DQS10
DM5/DQS14
NC/DQS14
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 0
DQ9
I/O 1
I/O 1
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS6
DQS2
DQS6
DM2/DQS11
NC/DQS11
DM6/DQS15
NC/DQS15
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
NC/DQS12
DM7/DQS16
NC/DQS16
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
V
V
Serial PD
D0 - D8
D0 - D8
D0 - D8
DDSPD
DQS8
Serial PD
DQS8
/V
DD DDQ
DM8/DQS17
NC/DQS17
SCL
SDA
VREF
DM/ NU/ CS DQS DQS
RDQS RDQS
WP A0 A1 A2
SA0 SA1 SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
V
SS
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
Signals for Address and Command Parity Function (M393T6553CZA)
Register
V
V
C0
C1
SS
SS
1:1
PPO
PAR_IN
100K ohms
PAR_IN
R
E
G
I
S0*
RSO-> CS : DDR2 SDRAMs D0-D8
QERR
Err_Out
BA0-BA1
A0-A13
RAS
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8
RRAS -> RAS : DDR2 SDRAMs D0-D8
RCAS -> CAS : DDR2 SDRAMs D0-D8
RWE -> WE : DDR2 SDRAMs D0-D8
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section: "Register
Options for Unused Address inputs"
CAS
S
T
E
R
WE
CKE0
ODT0
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
RST
RESET
* S0 connects to DCS and VDD connects to CSR on the register. S1, CKE1 and ODT1 are NC.
PCK7
PCK7
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
P
L
L
Notes :
CK0
1. DQ-to-I/O wiring may be changed within a byte.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. Unless otherwise noted, resister values are 22 Ohms
PCK7 -> CK : Register
OE
RESET
PCK7 -> CK : Register
Rev. 1.6 Dec. 2006
7 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
7.2 1GB, 128Mx72 Module (M393T2953CZ3 / M393T2953CZA / M392T2953CZA)
(populated as 2 rank of x8 DDR2 SDRAMs)
RS1
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
NC/DQS9
DM4/DQS13
NC/DQS13
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
I/O 0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
D0
D9
D4
D13
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS5
DQS1
DQS5
DM1/DQS10
NC/DQS10
DM5/DQS14
NC/DQS14
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 0
I/O 0
I/O 0
DQ9
I/O 1
I/O 1
I/O 1
I/O 1
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS6
DQS2
DQS6
DM2/DQS11
NC/DQS11
DM6/DQS15
NC/DQS15
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D11
D6
D15
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
NC/DQS12
DM7/DQS16
NC/DQS16
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D12
D7
D16
DQS8
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DDSPD
DQS8
Serial PD
DM8/DQS17
NC/DQS17
/V
DD DDQ
SCL
SDA
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
WP A0 A1 A2
SA0 SA1 SA2
VREF
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D17
V
SS
Signals for Address and Command Parity Function (M393T2953CZA)
Register A
Register B
V
V
C0
C1
V
V
C0
C1
SS
DD
DD
DD
S0*
RSO-> CS : DDR2 SDRAMs D0-D8
RS1-> CS : DDR2 SDRAMs D9-D17
PPO
S1*
1:2
PPO
PAR_IN
PAR_IN
PAR_IN
BA0-BA1
A0-A13
RAS
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
R
E
G
I
QERR
Err_Out
QERR
100K ohms
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section: "Register
Options for Unused Address inputs"
CAS
WE
CKE0
CKE1
ODT0
ODT1
S
T
E
R
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RCKE1 -> CKE : DDR2 SDRAMs D9-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
RODT1 -> ODT1 : DDR2 SDRAMs D9-D17
P
L
L
RST
RESET**
PCK7**
CK0
PCK7 -> CK : Register
PCK7**
OE
RESET
PCK7 -> CK : Register
* S0 connects to DCS and S1 connects to CSR on a Register,
S1 connects to DCS and S0 connects to CSR on another Register.
Notes :
1. DQ-to-I/O wiring may be changed within a byte.
** RESET, PCK7 and PCK7 connect to both Registers.
Other signals connect to one of two Registers.
2. Unless otherwise noted, resister values are 22 Ohms
3. RS0 and RS1 alternate between the back and front sides of the DIMM
Rev. 1.6 Dec. 2006
8 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
7.3 1GB, 128Mx72 Module (M393T2950CZ3 / M393T2950CZA / M392T2950CZA)
(populated as 1 rank of x4 DDR2 SDRAMs)
VSS
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 0
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D9
DQS1
DM1/DQS10
DQS1
NC/DQS10
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
D1
D10
DQ10
DQ11
DQS2
DM2/DQS11
DQS2
NC/DQS11
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
D2
D11
DQS3
DM3/DQS12
DQS3
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
Serial PD
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D12
SCL
SDA
WP A0 A1 A2
DQS4
DM4/DQS13
DQS4
NC/DQS13
SA0 SA1 SA2
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D13
DQS5
DM5/DQS14
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DDSPD
DQS5
NC/DQS14
DM
CS DQS DQS
DM
CS DQS DQS
/V
DD DDQ
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D14
VREF
V
DQS6
DM6/DQS15
SS
DQS6
NC/DQS15
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D15
DQS7
DM7DQS16
DQS7
NC/DQS16
DM
CS DQS DQS
DM
CS DQS DQS
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D16
DQS8
DM8/DQS17
DQS8
NC/DQS17
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D17
1:2
Signals for Address and Command Parity Function (M393T2950CZA)
R
E
G
I
S0*
RSO-> CS : DDR2 SDRAMs D0-D17
BA0-BA1
A0-A13
RAS
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
Register A
Register B
V
C0
C1
V
V
C0
C1
SS
DD
DD
DD
V
PPO
CAS
S
T
E
R
PPO
PAR_IN
100K ohms
PAR_IN
PAR_IN
WE
QERR
Err_Out
QERR
CKE0
ODT0
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section: "Register
Options for Unused Address inputs"
RST
RESET**
PCK7**
Notes :
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resister values are 22 Ohms
PCK7**
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
* S0 connects to DCS of Register1 and CSR of Register 2.
CSR of register 1 and DCS of register 2 connect to VDD.
P
L
CK0
L
OE
** RESET, PCK7 and PCK7 connect to both Registers.
PCK7 -> CK : Register
RESET
Other signals connect to one of two Registers. S1, CKE1 and ODT1 are NC.
PCK7 -> CK : Register
Rev. 1.6 Dec. 2006
9 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
7.4 2GB, 256Mx72 Module (M393T5750CZ3-CCC/D5, M393T5750CZA-CCC/D5/E6)
(populated as 2 rank of x4 DDR2 SDRAMs)
VSS
RS1
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
Serial PD
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
SCL
I/O 0
I/O 0
I/O 0
SDA
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D18
D9
D27
WP A0 A1 A2
DQS1
DM1/DQS10
SA0 SA1 SA2
Serial PD
DQS1
NC/DQS10
V
V
DDSPD
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
/V
D0 - D35
D0 - D35
D0 - D35
DQ9
DQ13
DQ14
DQ15
I/O 1
DD DDQ
D1
D19
D10
D28
DQ10
DQ11
I/O 2
I/O 3
VREF
DQS2
DM2/DQS11
DQS2
NC/DQS11
V
SS
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
I/O 1
I/O 2
I/O 3
D2
D20
D11
D29
Signals for Address and Command
Parity Function (M393T5750CZA)
DQS3
DM3/DQS12
DQS3
NC/DQS12
Register A1
V
V
C0
C1
SS
DD
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D21
D12
D30
PPO
PAR_IN
QERR
DQS4
DM4/DQS13
DQS4
NC/DQS13
Register B1
PPO
V
V
C0
C1
PAR_IN
DD
DD
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
PAR_IN
DQ33
DQ34
DQ35
D4
D22
D13
D31
Err_Out
QERR
DQS5
DM5/DQS14
100K ohms
DQS5
NC/DQS14
Register A2
V
C0
C1
SS
DD
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
V
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
PPO
PAR_IN
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D23
D14
D32
QERR
DQS6
DM6/DQS15
Register B2
DQS6
NC/DQS15
V
V
C0
C1
DD
DD
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
PPO
PAR_IN
DQ49
DQ50
DQ51
D6
D24
D15
D33
QERR
DQS7
DM7DQS16
Register A1 and A2 share the a part of Add/
Cmd input signal set.
DQS7
NC/DQS16
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
Register B1 and B2 share the rest part of Add/
Cmd input signal set.
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D25
D16
D34
DQS8
DM8/DQS17
The resistors on Par_In, A13, A14, A15, BA2
and the signal line of Err_Out refer to the sec-
tion: "Register Options for Unused Address
inputs"
DQS8
NC/DQS17
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D26
D17
D35
S0*
S1*
BA0-BA1
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
RSO-> CS : DDR2 SDRAMs D0-D17
RS1-> CS : DDR2 SDRAMs D18-D35
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35
RRAS -> RAS : DDR2 SDRAMs D0-D35
RCAS -> CAS : DDR2 SDRAMs D0-D35
RWE -> WE : DDR2 SDRAMs D0-D35
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RCKE1 -> CKE : DDR2 SDRAMs D18-D35
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
1:2
R
E
G
I
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
P
L
L
PCK7 -> CK : Register
OE
RESET
S
T
PCK7 -> CK : Register
E
R
RST
RESET**
PCK7**
PCK7**
* S0 connects to DCS and S1 connects to CSR on a pair of Registers, S1 connects to DCS and S0 connects to CSR on another pair of Registers.
** RESET, PCK7 and PCK7 connects to all Registers. Other signals connect to one pair of four Registers.
Rev. 1.6 Dec. 2006
10 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
7.5 2GB, 256Mx72 Module (M393T5750CZA-CF7)
(populated as 2 rank of x4 DDR2 SDRAMs)
VSS
RS1
RS0
Serial PD
SCL
SDA
DQS0
DQS0
DM0/DQS9
NC/DQS9
WP A0 A1 A2
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
SA0 SA1 SA2
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 0
I/O 0
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D18
D9
D27
V
V
Serial PD
D0 - D35
D0 - D35
D0 - D35
DQS1
DM1/DQS10
DDSPD
DQS1
NC/DQS10
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
/V
DM
CS DQS DQS
DD DDQ
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
I/O 1
I/O 2
I/O 3
D1
D19
D10
D28
VREF
DQ10
DQ11
V
SS
DQS2
DM2/DQS11
DQS2
NC/DQS11
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
I/O 1
I/O 2
I/O 3
D2
D20
D11
D29
DQS3
DM3/DQS12
DQS3
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D21
D12
D30
Signals for Address and Command
Parity Function (M393T5166AZA)
DQS4
DM4/DQS13
DQS4
NC/DQS13
Register
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D22
D13
D31
PAR_IN
0 ohm
PTYERR
Err_Out
PAR_IN
100K ohms
DQS5
DM5/DQS14
DQS5
NC/DQS14
Register
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
PAR_IN
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D23
D14
D32
PTYERR
DQS6
DM6/DQS15
0 Ohm resistor on Err_Out is not populated for
non-parity card.
DQS6
NC/DQS15
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D24
D15
D33
The resistors on Par_In, A13, A14, A15, BA2
and the signal line of Err_Out refer to the sec-
tion: "Register Options for Unused Address
inputs"
DQS7
DM7DQS16
DQS7
NC/DQS16
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D25
D16
D34
DQS8
DM8/DQS17
DQS8
NC/DQS17
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D26
D17
D35
S0*
S1*
RS0-> CS : DDR2 SDRAMs D0-D17
RS1-> CS : DDR2 SDRAMs D18-D35
1:2
BA0-BA2
A0-A13
RAS
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D35
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35
RRAS -> RAS : DDR2 SDRAMs D0-D35
RCAS -> CAS : DDR2 SDRAMs D0-D35
RWE -> WE : DDR2 SDRAMs D0-D35
R
E
G
I
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
CAS
WE
CKE0
CKE1
ODT0
ODT1
P
L
L
S
T
E
R
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RCKE1 -> CKE : DDR2 SDRAMs D18-D35
PCK7 -> CK : Register
OE
RESET
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
PCK7 -> CK : Register
RST
RESET**
PCK7**
PCK7**
* S0 connects to DCS0 and S1 connects to DCS1 on both Registers.
** RESET, PCK7 and PCK7 connect to all Registers. Other signals connect to two Registers.
Rev. 1.6 Dec. 2006
11 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
8.0 Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
V
Notes
Voltage on V pin relative to V
V
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
DD
SS
DD
Voltage on V
Voltage on V
pin relative to V
V
V
DDQ
DDL
SS
DDQ
pin relative to V
V
V
1
SS
DDL
Voltage on any pin relative to V
Storage Temperature
V
V
V
1
SS
IN, OUT
T
°C
1, 2
STG
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
9.0 AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
V
Supply Voltage
V
V
DD
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
DDL
V
1.7
1.8
1.9
V
DDQ
V
0.49*V
0.50*V
0.51*V
DDQ
mV
V
1,2
3
REF
DDQ
DDQ
V
V
-0.04
V
V
+0.04
REF
TT
REF
REF
Note : There is no specific device V supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
must be less than or equal
DDQ
DD
to V
.
DD
1. The value of V
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
is expected to be about 0.5
REF
REF
x V
of the transmitting device and V
is expected to track variations in V
.
DDQ
DDQ
REF
2. Peak to peak AC noise on V
may not exceed +/-2% V
(DC).
REF
REF
3. V of transmitting device must track V
of receiving device.
REF
TT
4. AC parameters are measured with V , V
and V
tied together.
DDL
DD
DDQ
Rev. 1.6 Dec. 2006
12 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
9.1 Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2
standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
9.2 Input DC Logic Level
Symbol
(DC)
Parameter
Min.
+ 0.125
Max.
V + 0.3
DDQ
Units
V
V
Notes
V
DC input logic high
DC input logic low
V
IH
REF
V (DC)
- 0.3
V
- 0.125
REF
IL
9.3 Input AC Logic Level
DDR2-400, DDR2-533
Min. Max.
+ 0.250
DDR2-667, DDR2-800
Symbol
Parameter
Units
Min.
V + 0.200
REF
Max.
V
(AC)
AC input logic high
AC input logic low
V
-
V
V
IH
REF
V (AC)
-
V
- 0.250
V
- 0.200
REF
IL
REF
9.4 AC Input Test Conditions
Symbol
Condition
Value
0.5 * V
Units
V
Notes
1
1
V
Input reference voltage
REF
DDQ
V
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
1.0
V
SWING(MAX)
SLEW
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
(AC) level applied to the device under test.
IH/IL
2. The input signal minimum slew rate is to be maintained over the range from V
to V (AC) min for rising edges and the range from V
to V (AC)
REF IL
REF
IH
max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the negative
IL
IH
IH
IL
transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
(DC) max
IL
IL
(AC) max
SS
delta TF
V
delta TR
Rising Slew =
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
delta TF
< AC Input Test Signal Waveform >
Rev. 1.6 Dec. 2006
13 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
10.0 IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol Proposed Conditions
Units
Notes
Operating one bank active-precharge current;
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
t
t
t
t
IDD0
IDD1
mA
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
mA
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as IDD4W
Precharge power-down current;
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
t
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
mA
mA
Fast PDN Exit MRS(12) = 0mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address bus
Slow PDN Exit MRS(12) = 1mA
inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP =
IDD4W
IDD4R
t
RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
mA
mA
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
IDD5B
IDD6
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal
mA
mA
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC =
t
t
t
t
t
IDD7
t
t
t
t
t
t
t
mA
RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the follow-
ing page for detailed timing conditions
Rev. 1.6 Dec. 2006
14 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
11.0 Operating Current Table (TA=0oC, VDD= 1.9V)
11.1 M393T6553CZ3 / M393T6553CZA / M392T6553CZA : 512MB(64Mx8 *9) Module
Symbol
IDD0
IDD1
F7(800@CL=6)
900
E6(667@CL=5)
765
D5(533@CL=4)
720
CC(400@CL=3)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
720
855
72
990
72
315
360
270
108
540
1,485
1,530
1,395
72
900
72
315
360
270
108
495
1,260
1,305
1,350
72
855
72
270
315
270
108
450
1,080
1,125
1,260
72
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
270
315
270
108
450
990
990
1,260
72
IDD7
2,295
1,980
1,980
1,980
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.2 M393T6553CZ3 / M393T6553CZA / M392T6553CZA : 512MB(64Mx8 *9) Module
- considering Register and PLL current value
Symbol
IDD0
IDD1
F7(800@CL=6)
1,490
1,630
552
E6(667@CL=5)
1,265
1,450
512
D5(533@CL=4)
1,130
1,315
472
CC(400@CL=3)
1,040
1,225
432
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
845
840
820
658
1,080
2,005
2,120
2,065
72
775
780
740
578
660
675
660
498
590
615
580
418
965
850
780
1,710
1,815
1,900
72
1,460
1,555
1,690
72
1,300
1,340
1,570
72
IDD7
2,985
2,560
2,450
2,340
* IDD6 : Not count Register and PLL current
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.6 Dec. 2006
15 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
11.3 M393T2953CZ3 / M393T2953CZA / M392T2953CZA : 1GB(64Mx8 *18) Module
Symbol
IDD0
IDD1
F7(800@CL=6)
1,260
1,350
144
E6(667@CL=5)
1,125
1,260
144
D5(533@CL=4)
1,035
1,170
144
CC(400@CL=3)
1,035
1,170
144
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
630
720
540
216
630
720
540
216
540
630
540
216
540
630
540
216
900
855
765
765
1,845
1,890
1,755
144
1,620
1,665
1,710
144
1,395
1,440
1,575
144
1,305
1,305
1,575
144
IDD7
2,655
2,340
2,295
2,295
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.4 M393T2953CZ3 / M393T2953CZA / M392T2953CZA : 1GB(64Mx8 *18) Module
- considering Register and PLL current value
Symbol
IDD0
IDD1
F7(800@CL=6)
1,950
2,120
784
E6(667@CL=5)
1,715
1,920
724
D5(533@CL=4)
1,525
1,720
664
CC(400@CL=3)
1,425
1,610
604
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
1,340
1,290
1,270
946
1,460
2,495
2,680
2,585
144
1,250
1,220
1,170
846
1,345
2,180
2,345
2,390
144
1,070
1,060
1,070
746
1,185
1,865
2,010
2,105
144
980
990
970
646
1,115
1,685
1,765
1,955
144
IDD7
3,685
3,210
3,005
2,845
* IDD6 : Not count Register and PLL current
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.6 Dec. 2006
16 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
11.5 M393T2950CZ3 / M393T2950CZA / M392T2950CZA : 1GB(128Mx4 *18) Module
Symbol
IDD0
IDD1
F7(800@CL=6)
1,710
1,890
144
E6(667@CL=5)
1,530
1,800
144
D5(533@CL=4)
1,440
1,710
144
CC(400@CL=3)
1,440
1,710
144
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
630
720
540
216
630
720
540
216
540
630
540
216
540
630
540
216
990
990
900
900
2,610
2,700
2,700
144
2,340
2,430
2,700
144
1,980
2,070
2,520
144
1,800
1,890
2,520
144
IDD7
4,500
3,960
3,960
3,960
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.6 M393T2950CZ3 / M393T2950CZA / M392T2950CZA : 1GB(128Mx4 *18) Module
- considering Register and PLL current value
Symbol
IDD0
IDD1
F7(800@CL=6)
2,400
2,660
784
E6(667@CL=5)
2,120
2,460
724
D5(533@CL=4)
1,930
2,260
664
CC(400@CL=3)
1,830
2,150
604
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
1,340
1,290
1,270
946
1,550
3,260
3,490
3,530
144
1,250
1,220
1,170
846
1,480
2,900
3,110
3,380
144
1,070
1,060
1,070
746
1,320
2,450
2,640
3,050
144
980
990
970
646
1,250
2,180
2,350
2,900
144
IDD7
5,530
4,830
4,670
4,510
* IDD6 : Not count Register and PLL current
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.6 Dec. 2006
17 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
11.7 M393T5750CZ3 / M393T5750CZA : 2GB(128Mx4 *36) Module
Symbol
IDD0
IDD1
F7(800@CL=6)
2,430
2,610
288
E6(667@CL=5)
2,250
2,520
288
D5(533@CL=4)
2,070
2,340
288
CC(400@CL=3)
2,070
2,340
288
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6
1,260
1,440
1,080
432
1,710
3,330
3,420
3,420
288
1,260
1,440
1,080
432
1,710
3,060
3,150
3,420
288
1,080
1,260
1,080
432
1,530
2,610
2,700
3,150
288
1,080
1,260
1,080
432
1,530
2,430
2,520
3,150
288
IDD7
5,220
4,680
4,590
4,590
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
11.8 M393T5750CZ3 / M393T5750CZA : 2GB(128Mx4 *36) Module - considering Register and PLL current value
Symbol
IDD0
IDD1
F7(800@CL=6)
3,450
E6(667@CL=5)
3,120
D5(533@CL=4)
2,790
CC(400@CL=3)
2,640
3,020
968
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
3,770
1,238
2,320
2,240
2,170
1,522
2,500
4,320
4,510
4,640
288
6,930
3,520
1,148
2,180
2,140
2,020
1,372
2,400
3,910
4,090
4,420
288
6,130
3,180
1,058
1,860
1,860
1,870
1,222
2,120
3,320
3,490
3,930
288
5,780
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
1,720
1,760
1,720
1,072
2,020
3,000
3,160
3,710
288
IDD7
5,520
* IDD6 : Not count Register and PLL current
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.6 Dec. 2006
18 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
o
(VDD=1.8V, VDDQ=1.8V, TA=25 C)
12.0 Input/Output Capacitance
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
M393T6553CZ3
M393T6553CZA
M392T6553CZA
M393T2953CZ3
M393T2953CZA
M392T2953CZA
M393T2950CZ3
M393T2950CZA
M392T2950CZA
Symbol
Units
M393T5750CZ3
M393T5750CZA
Part-Number
Input capacitance, CK and CK
CCK
-
-
-
-
11
12
12
10
-
-
-
-
11
12
12
10
-
-
-
-
11
12
12
10
-
-
-
-
11
12
12
10
Input capacitance, CKE and CS
Input capacitance, Addr,RAS,CAS,WE
CI1
CI2
pF
Input/output capacitance, DQ, DM, DQS, DQS CIO
* DM is internally loaded to match DQ and DQS identically.
Rev. 1.6 Dec. 2006
19 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400
(0 °C < T
< 95 °C; V
= 1.8V + 0.1V; V = 1.8V + 0.1V)
DDQ DD
OPER
13.1 Refresh Parameters by Device Density
Parameter
Symbol
256Mb
512Mb
1Gb
2Gb
4Gb
Units
Refresh to active/Refresh command time
tRFC
tREFI
75
105
127.5
195
327.5
ns
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
7.8
3.9
µs
µs
CASE
Average periodic refresh interval
85 °C < T
CASE
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin(CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tCK, CL=6
tRCD
DDR2-800(F7)
DDR2-667(E6)
DDR2-533(D5)
DDR2-400(CC)
3 - 3 - 3
6 - 6 - 6
5 - 5 - 5
4 - 4 - 4
Units
min
max
min
max
min
5
max
min
max
-
-
5
8
8
5
8
ns
ns
ns
ns
ns
ns
ns
ns
5
3.75
2.5
15
8
3.75
3
8
3.75
3.75
-
8
5
-
8
-
8
8
8
8
-
-
-
-
-
-
15
15
60
45
-
15
-
15
15
55
40
-
tRP
15
-
-
-
-
15
-
-
-
tRC
60
60
-
tRAS
45
70000
70000
45
70000
70000
13.3 Timing Parameters by Speed Grade
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Symbol
Units
Notes
Parameter
min
max
400
min
-450
-400
0.45
0.45
max
min
max
+500
+450
0.55
0.55
min
-600
-500
0.45
0.45
max
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
- 400
- 350
0.45
0.45
+450
+400
0.55
-500
-450
0.45
0.45
+600
+500
0.55
0.55
ps
ps
tDQSCK
tCH
350
0.55
0.55
tCK
tCK
CK low-level width
tCL
0.55
min(tCL,t
CH)
min(tCL,
tCH)
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
x
x
x
x
ps
Clock cycle time, CL=x
tCK
2500
125
50
8000
3000
175
8000
3750
225
8000
5000
275
8000
ps
ps
ps
DQ and DM input hold time
DQ and DM input setup time
tDH(base)
tDS(base)
x
x
x
x
x
x
x
x
100
100
150
Control & Address input pulse width for
each input
tIPW
0.6
x
0.6
x
0.6
x
0.6
x
tCK
DQ and DM input pulse width for each input tDIPW
Data-out high-impedance time from CK/CK tHZ
0.35
x
x
0.35
x
x
0.35
x
x
0.35
x
x
tCK
ps
tAC max
tAC max
tAC max
tAC max
DQS low-impedance time from CK/CK
tLZ(DQS)
tAC min tAC max tAC min tAC max
tAC min tAC max tAC min tAC max
ps
2* tAC
min
2*tAC
min
DQ low-impedance time from CK/CK
tLZ(DQ)
tAC max
tAC max 2* tACmin tAC max 2* tACmin tAC max
ps
DQS-DQ skew for DQS and associated DQ
signals
tDQSQ
tQHS
tQH
x
200
300
x
x
240
340
x
x
x
300
400
x
x
x
350
450
x
ps
ps
ps
DQ hold skew factor
x
x
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
tHP -
tQHS
DQ/DQS output hold time from DQS
First DQS latching transition to associated
clock edge
tDQSS
- 0.25
0.25
-0.25
0.25
-0.25
0.25
-0.25
0.25
tCK
Rev. 1.6 Dec. 2006
20 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Symbol
Units
Notes
Parameter
min
max
min
0.35
0.35
0.2
max
min
max
min
max
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
x
x
0.35
0.35
0.2
0.2
2
x
0.35
0.35
0.2
0.2
2
x
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
x
x
x
x
x
x
x
x
tDSH
x
0.2
x
x
x
tMRD
x
2
x
x
x
tWPST
tWPRE
tIH(base)
tIS(base)
tRPRE
tRPST
0.4
0.35
250
175
0.9
0.4
0.6
x
0.4
0.6
x
0.4
0.35
375
250
0.9
0.4
0.6
x
0.4
0.35
475
350
0.9
0.4
0.6
x
Write preamble
0.35
275
200
0.9
Address and control input hold time
Address and control input setup time
Read preamble
x
x
x
x
x
x
x
x
ps
1.1
0.6
1.1
0.6
1.1
0.6
1.1
0.6
tCK
tCK
Read postamble
0.4
Active to active command period for 1KB
page size products
tRRD
7.5
10
35
45
x
x
7.5
10
x
x
7.5
10
x
x
7.5
10
x
x
ns
ns
ns
ns
Active to active command period for 2KB
page size products
tRRD
tFAW
Four Activate Window for 1KB page size
products
37.5
50
37.5
50
37.5
50
Four Activate Window for 2KB page size
products
tFAW
CAS to CAS command delay
Write recovery time
tCCD
tWR
2
x
x
2
2
2
tCK
ns
15
15
x
x
x
15
x
x
x
15
x
x
x
Auto precharge write recovery + precharge
time
tDAL
WR+tRP
x
WR+tRP
WR+tRP
WR+tRP
tCK
Internal write to read command delay
tWTR
7.5
7.5
7.5
7.5
7.5
7.5
10
7.5
ns
ns
Internal read to precharge command delay tRTP
Exit self refresh to a non-read command
Exit self refresh to a read command
tXSNR
tRFC + 10
200
tRFC + 10
200
tRFC + 10
200
tRFC + 10
200
ns
tXSRD
x
x
x
tCK
Exit precharge power down to any non-
read command
tXP
2
2
2
2
x
x
2
2
x
x
2
2
x
x
tCK
tCK
tCK
Exit active power down to read command tXARD
Exit active power down to read command
tXARDS
8 - AL
7 - AL
6 - AL
6 - AL
(slow exit, lower power)
CKE minimum pulse width
tCKE
tCK
3
2
3
2
3
2
3
2
(high and low pulse width)
ODT turn-on delay
tAOND
tAON
2
2
2
2
tCK
ns
tAC(max)
+ 0.7
tAC(max)
+0.7
tAC(max)
+1
tAC(max)
+1
ODT turn-on
tAC(min)
tAC(min)
tAC(min)
tAC(min)
2tCK +
tAC(max)
+1
tAC(min)+
2
tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC
ODT turn-on(Power-Down mode)
tAONPD
ns
2
(max)+1
2
(max)+1
2
(max)+1
ODT turn-off delay
ODT turn-off
tAOFD
tAOF
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ns
tAC(max)
+ 0.6
tAC(max)
+ 0.6
tAC(max)+
0.6
tAC(max)+
0.6
tAC(min)
tAC(min)
tAC(min)
tAC(min)
2.5tCK +
tAC(max)
+1
2.5tCK+
tAC(max)
+1
2.5tCK+
tAC(max)
+1
tAC(min)+
2
tAC(min)+ 2.5tCK+tA tAC(min)+
tAC(min)+
2
ODT turn-off (Power-Down mode)
tAOFPD
ns
2
C(max)+1
2
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
3
8
0
tCK
tCK
ns
12
12
12
12
Minimum time clocks remains ON after
CKE asynchronously drops LOW
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tDelay
ns
Rev. 1.6 Dec. 2006
21 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
14.0 Physical Dimensions
14.1 64Mbx8 based 64Mx72 Module (1 Rank) - M393T6553CZ3 / M393T6553CZA
Units : Millimeters
2.70
133.35
30.00
PLL
1.0 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QC
Rev. 1.6 Dec. 2006
22 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
14.2 64Mbx8 based 64Mx72 Module (1 Rank) - M392T6553CZA
Units : Millimeters
133.35
128.95
2x 3.00 MIN
2.20
2.70
a
PLL
5.175
63
55
123
1.0 max
A
B
1.27 ± 0.10
133.35
5.00
4.00
0.80±0.05
0.20
4.00
3.80
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 64M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QC
Rev. 1.6 Dec. 2006
23 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
14.3 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks)
- M393T2953CZ3 / M393T2953CZA / M393T2950CZ3 / M393T2950CZA
Units : Millimeters
133.35
4.00
30.00
PLL
1.0 max
1.7 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QC / K4T51043QC
Rev. 1.6 Dec. 2006
24 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
14.4 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks) - M392T2953CZA / M392T2950CZA
Units : Millimeters
133.35
2x 3.00 MIN
2.20
128.95
4.00
a
PLL
5.175
63
55
123
1.0 max
A
B
1.7 max
1.27 ± 0.10
PLL
133.35
5.00
4.00
0.80±0.05
0.20
4.00
3.80
2.50
1.00
Detail B
1.50±0.10
Detail A
The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51083QC / K4T51043QC
Rev. 1.6 Dec. 2006
25 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
14.5 128Mbx4 based 256Mx72 Module (2 Ranks) - M393T5750CZ3 / M393T5750CZA
Units : Millimeters
133.35
PLL
4.00
30.00
1.0 max
1.7 max
1.27 ± 0.10
A
B
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
1.50±0.10
Detail A
Detail B
The used device is 128M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T51043QC
Rev. 1.6 Dec. 2006
26 of 27
512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
15.0 240 Pin DDR2 Registered DIMM Clock Topology
0ns (nominal)
PLL
DDR2 SDRAM
120 ohms
OUT1
CK0
120 ohms
IN
DDR2 SDRAM
Reg.A
CK0
120 ohms
OUTN
120 ohms
C
C
Feedback In
Feedback Out
Reg.B
Note:
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Rev. 1.6 Dec. 2006
27 of 27
相关型号：
M393T2953BG0-CD5/CC
DDR2 Registered SDRAM MODULE 240pin Registered Module based on 512Mb B-die 72-bit ECC
SAMSUNG
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