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M393T2953GZ3-CD5 [SAMSUNG]

DDR DRAM Module, 128MX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240;
M393T2953GZ3-CD5
型号： M393T2953GZ3-CD5
厂家： SAMSUNG    SAMSUNG
描述：

DDR DRAM Module, 128MX72, 0.5ns, CMOS, ROHS COMPLIANT, DIMM-240

动态存储器 双倍数据速率
文件： 总26页 (文件大小：534K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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RDIMM  
DDR2 SDRAM  
DDR2 Registered SDRAM MODULE  
240pin Registered Module based on 512Mb G-die  
72-bit ECC  
60FBGA with Lead-Free and Halogen-Free  
(RoHS compliant)  
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,  
AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE  
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-  
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-  
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT  
GUARANTEE OR WARRANTY OF ANY KIND.  
1. For updates or additional information about Samsung products, contact your nearest Samsung office.  
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar  
applications where Product failure could result in loss of life or personal or physical harm, or any military or  
defense application, or any governmental procurement to which special terms or provisions may apply.  
* Samsung Electronics reserves the right to change products or specification without notice.  
Rev. 1.0 July 2008  
1 of 26  
RDIMM  
DDR2 SDRAM  
Table of Contents  
1.0 DDR2 Registered DIMM Ordering Information ..........................................................................4  
2.0 Features ........................................................................................................................................4  
3.0 Address Configuration ................................................................................................................4  
4.0 Pin Configurations (Front side/Back side) ................................................................................5  
5.0 Pin Description ............................................................................................................................5  
6.0 Input/Output Functional Description .........................................................................................6  
7.0 Functional Block Diagram ...........................................................................................................7  
7.1 512MB, 64Mx72 Module - M393T6553GZ3/M393T6553GZA ...............................................................7  
7.2 1GB, 128Mx72 Module - M393T2953GZ3/M393T2953GZA ..................................................................8  
7.3 1GB, 128Mx72 Module - M393T2950GZ3/M393T2950GZA ..................................................................9  
7.4 2GB, 256Mx72 Module - M393T5750GZ3/M393T5750GZA ................................................................10  
8.0 Absolute Maximum DC Ratings ................................................................................................11  
9.0 AC & DC Operating Conditions ................................................................................................11  
9.1 Recommended DC Operating Conditions (SSTL - 1.8) ....................................................................11  
9.2 Operating Temperature Condition ...............................................................................................12  
9.3 Input DC Logic Level .................................................................................................................12  
9.4 Input AC Logic Level ..................................................................................................................12  
9.5 AC Input Test Conditions ...........................................................................................................12  
10.0 IDD Specification Parameters Definition ...............................................................................13  
11.0 Operating Current Table : .......................................................................................................14  
11.1 M393T6553GZ3 / M393T6553GZA : 512MB(64Mx8 *9) Module ....................................................14  
11.2 M393T6553GZ3 / M393T6553GZA : 512MB(64Mx8 *9) Module ....................................................14  
11.3 M393T2953GZ3 / M393T2953GZA : 1GB(64Mx8 *18) Module ......................................................15  
11.4 M393T2953GZ3 / M393T2953GZA : 1GB(64Mx8 *18) Module ......................................................15  
11.5 M393T2950GZ3 / M393T2950GZA : 1GB(128Mx4 *18) Module ....................................................16  
11.6 M393T2950GZ3 / M393T2950GZA : 1GB(128Mx4 *18) Module ....................................................16  
11.7 M393T5750GZ3 / M393T5750GZA : 2GB(128Mx4 *36) Module ....................................................17  
11.8 M393T5750GZ3 / M393T5750GZA : 2GB(128Mx4 *36) Module ....................................................17  
12.0 Input/Output Capacitance .......................................................................................................18  
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400 .....................................18  
13.1 Refresh Parameters by Device Density ...................................................................................18  
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .........................................18  
13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)....................................................19  
13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)....................................................21  
14.0 Physical Dimensions ...............................................................................................................23  
14.1 64Mbx8 based 64Mx72 Module (1 Rank) ..................................................................................23  
14.2 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks) ...............................................................24  
14.3 128Mbx4 based 256Mx72 Module (2 Ranks) .............................................................................25  
15.0 240 Pin DDR2 Registered DIMM Clock Topology .................................................................26  
Rev. 1.0 July 2008  
2 of 26  
RDIMM  
DDR2 SDRAM  
Revision History  
Revision  
Month  
July  
Year  
2008  
History  
1.0  
- Initial Release  
Rev. 1.0 July 2008  
3 of 26  
RDIMM  
DDR2 SDRAM  
1.0 DDR2 Registered DIMM Ordering Information  
Part Number  
M393T6553GZ3-CD5/CC  
M393T6553GZA-CF7/E6  
M393T2953GZ3-CD5/CC  
M393T2953GZA-CF7/E6  
M393T2950GZ3-CD5/CC  
M393T2950GZA-CF7/E6  
M393T5750GZ3-CD5/CC  
M393T5750GZA-CF7/E6  
Note :  
Density Organization  
Component Composition  
64Mx8(K4T51083QG)*9EA  
64Mx8(K4T51083QG)*9EA  
64Mx8(K4T51083QG)*18EA  
64Mx8(K4T51083QG)*18EA  
128Mx4(K4T51043QG)*18EA  
128Mx4(K4T51043QG)*18EA  
128Mx4(K4T51043QG)*36EA  
128Mx4(K4T51043QG)*36EA  
Number of Rank Parity Register  
Height  
512MB  
512MB  
1GB  
64Mx72  
64Mx72  
1
1
2
2
1
1
2
2
X
O
X
O
X
O
X
O
30.00mm  
30.00mm  
30.00mm  
30.00mm  
30.00mm  
30.00mm  
30.00mm  
30.00mm  
128Mx72  
128Mx72  
128Mx72  
128Mx72  
256Mx72  
256Mx72  
1GB  
1GB  
1GB  
2GB  
2GB  
1. “Z” of Part number(11th digit) stands for Lead-Free and RoHS compliant products.  
2. “3” of Part number(12th digit) stands for Dummy Pad PCB products.  
3. “A” of Part number(12th digit) stands for Parity Register products.  
2.0 Features  
•
Performance range  
F7(DDR2-800)  
E6(DDR2-667)  
D5(DDR2-533)  
CC(DDR2-400)  
Unit  
Mbps  
Mbps  
Mbps  
Mbps  
CK  
Speed@CL3  
Speed@CL4  
Speed@CL5  
Speed@CL6  
CL-tRCD-tRP  
-
400  
533  
667  
-
400  
533  
533  
-
400  
400  
-
533  
667  
800  
6-6-6  
-
5-5-5  
4-4-4  
3-3-3  
•
•
•
JEDEC standard VDD = 1.8V ± 0.1V Power Supply  
DDQ = 1.8V ± 0.1V  
V
200 MHz fCK for 400Mb/sec/pin, 267MHz fCK for 533Mb/sec/pin, 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin  
•
•
•
•
•
•
•
•
•
•
•
4 Banks  
Posted CAS  
Programmable CAS Latency: 3, 4, 5, 6  
Programmable Additive Latency: 0, 1 , 2 , 3, 4 and 5  
Write Latency(WL) = Read Latency(RL) -1  
Burst Length: 4 , 8(Interleave/Nibble sequential)  
Programmable Sequential / Interleave Burst Mode  
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)  
Off-Chip Driver(OCD) Impedance Adjustment  
On Die Termination with selectable values(50/75/150 ohms or disable)  
Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C  
- Support High Temperature Self-Refresh rate enable feature  
Serial presence detect with EEPROM  
•
•
DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8  
•
All of base components are Lead-Free, Halogen-Free, and RoHS compliant  
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.  
3.0 Address Configuration  
Organization  
Row Address  
A0-A13  
Column Address  
A0-A9,A11  
A0-A9  
Bank Address  
BA0-BA1  
Auto Precharge  
128Mx4(512Mb) based Module  
64Mx8(512Mb) based Module  
A10  
A10  
A0-A13  
BA0-BA1  
Rev. 1.0 July 2008  
4 of 26  
RDIMM  
DDR2 SDRAM  
4.0 Pin Configurations (Front side/Back side)  
Pin  
1
Front  
VREF  
VSS  
Pin  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
Back  
Pin  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
Front  
DQ19  
VSS  
Pin  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
Back  
Pin  
61  
62  
63  
64  
Front  
A4  
VDDQ  
Pin  
181  
182  
183  
184  
Back  
Pin  
91  
92  
93  
94  
95  
96  
97  
98  
Front  
Pin  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
Back  
DM5/DQS14  
NC/DQS14  
VSS  
VSS  
VSS  
VDDQ  
VSS  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
DQ4  
DQ5  
VSS  
DQ28  
DQ29  
VSS  
A3  
A1  
VDD  
DQS5  
DQS5  
VSS  
DQ0  
DQ1  
VSS  
DQ24  
DQ25  
VSS  
A2  
VDD  
DQ46  
DQ47  
VSS  
DM0/DQS9  
NC/DQS9  
VSS  
DM3/DQS12  
NC/DQS12  
VSS  
KEY  
DQ42  
DQ43  
VSS  
VSS  
VSS  
VDD  
DQS0  
DQS0  
VSS  
DQS3  
DQS3  
VSS  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
CK0  
CK0  
VDD  
DQ52  
DQ53  
VSS  
DQ6  
DQ7  
VSS  
DQ30  
DQ31  
VSS  
DQ48  
DQ49  
VSS  
DQ2  
DQ3  
VSS  
DQ26  
DQ27  
VSS  
NC/Par_In  
VDD  
A0  
VDD  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
RFU  
RFU  
VSS  
DQ12  
DQ13  
VSS  
CB4  
CB5  
VSS  
A10/AP  
BA0  
VDDQ  
BA1  
VDDQ  
SA2  
NC(TEST)  
VSS  
DQ8  
DQ9  
VSS  
CB0  
CB1  
VSS  
RAS  
S0  
VDDQ  
DM6/DQS15  
NC/DQS15  
VSS  
DM1/DQS10  
NC/DQS10  
VSS  
DM8/DQS17  
NC/DQS17  
VSS  
WE  
CAS  
VDDQ  
S14  
ODT1  
VDDQ  
VSS  
DQS6  
DQS6  
VSS  
DQS1  
DQS1  
VSS  
DQS8  
DQS8  
VSS  
ODT0  
A13  
VDD  
DQ54  
DQ55  
VSS  
RFU  
RFU  
VSS  
CB6  
CB7  
VSS  
VDDQ  
CKE14  
VDD  
DQ50  
DQ51  
VSS  
RESET  
NC  
VSS  
CB2  
CB3  
VSS  
VSS  
DQ60  
DQ61  
VSS  
DQ14  
DQ15  
VSS  
DQ36  
DQ37  
VSS  
DQ56  
DQ57  
VSS  
VDDQ  
DQ10  
DQ11  
VSS  
DQ32  
DQ33  
VSS  
CKE0  
VDD  
DM7/DQS16  
NC/DQS16  
VSS  
DQ20  
DQ21  
VSS  
DM4/DQS13  
NC/DQS13  
VSS  
DQS7  
DQS7  
VSS  
NC  
24  
25  
26  
27  
28  
29  
30  
DQ16  
DQ17  
VSS  
144  
145  
146  
147  
148  
149  
150  
54  
55  
56  
57  
58  
59  
60  
NC  
NC/Err_Out  
VDDQ  
174  
175  
176  
177  
178  
179  
180  
83  
84  
85  
86  
87  
88  
89  
90  
DQS4  
DQS4  
VSS  
203  
204  
205  
206  
207  
208  
209  
210  
114  
115  
116  
117  
118  
119  
120  
234  
235  
236  
237  
238  
239  
240  
NC  
VDDQ  
DQ62  
DQ63  
VSS  
DM2/DQS11  
NC/DQS11  
VSS  
A12  
A9  
VDD  
DQ38  
DQ39  
VSS  
DQ58  
DQ59  
VSS  
DQS2  
DQS2  
VSS  
A11  
A7  
VDD  
A5  
DQ34  
DQ35  
VSS  
DQ40  
DQ41  
VDDSPD  
DQ22  
DQ23  
A8  
A6  
DQ44  
DQ45  
VSS  
SDA  
SCL  
SA0  
SA1  
DQ18  
NC = No Connect, RFU = Reserved for Future Use  
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.  
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)  
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.  
4. CKE1,S1 Pin is used for double side Registered DIMM.  
5.0 Pin Description  
Pin Name  
Description  
Clock Inputs, positive line  
Pin Name  
ODT0~ODT1  
DQ0~DQ63  
CB0~CB7  
DQS0~DQS8  
DQS0~DQS8  
Description  
CK0  
CK0  
CKE0, CKE1  
RAS  
On die termination  
Data Input/Output  
Clock inputs, negative line  
Clock Enables  
Row Address Strobe  
Column Address Strobe  
Write Enable  
Data check bits Input/Output  
Data strobes  
Data strobes, negative line  
CAS  
WE  
DM(0~8),DQS(9~17) Data Masks / Data strobes (Read)  
S0, S1  
A0~A9, A11~A13  
A10/AP  
Chip Selects  
Address Inputs  
Address Input/Autoprecharge  
DQS9~DQS17  
RFU  
NC  
Data strobes (Read), negative line  
Reserved for Future Use  
No Connect  
Memory bus test tool  
(Not Connect and Not Useable on DIMMs)  
BA0, BA1  
DDR2 SDRAM Bank Address  
TEST  
SCL  
SDA  
SA0~SA2  
Par_In  
Err_Out  
RESET  
Serial Presence Detect (SPD) Clock Input  
SPD Data Input/Output  
SPD address  
Parity bit for the Address and Control bus  
Parity error found in the Address and Control bus VDDSPD  
Register and PLL control pin  
VDD  
VDDQ  
VSS  
Core Power  
I/O Power  
Ground  
Input/Output Reference  
SPD Power  
VREF  
*The VDD and VDDQ pins are tied to the single power-plane on PCB.  
Rev. 1.0 July 2008  
5 of 26  
RDIMM  
DDR2 SDRAM  
6.0 Input/Output Functional Description  
Symbol  
CK0  
Type  
Input  
Input  
Function  
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.  
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.  
CK0  
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low  
initiates the Power Down mode, or the Self Refresh mode.  
CKE0~CKE1  
S0~S1  
Input  
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled,  
new commands are ignored but previous operations continue.  
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are  
high.  
Input  
ODT0~ODT1  
Input  
Input  
I/O bus impedance control signals.  
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the  
SDRAM.  
RAS, CAS, WE  
VREF  
VDDQ  
Supply  
Supply  
Input  
Reference voltage for SSTL_18 inputs  
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity  
Selects which SDRAM bank of four is activated.  
BA0~BA1  
During a Bank Activate command cycle, Address defines the row address.  
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is  
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected  
and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command  
cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be pre-  
charged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge.  
A0~A9,A10/AP  
A11~A13  
Input  
DQ0~63,  
In/Out  
Input  
Data and Check Bit Input/Output pins  
CB0~CB7  
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once  
the write command is registered into the SDRAM.  
DM0~DM8  
V
DD, VSS  
Supply  
In/Out  
In/Out  
Input  
Power and ground for the DDR SDRAM input buffers and core logic  
DQS0~DQS17  
DQS0~DQS17  
SA0~SA2  
Positive line of the differential data strobe for input and output data.  
Negative line of the differential data strobe for input and output data.  
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.  
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA  
bus line to VDDSPD to act as a pullup.  
SDA  
SCL  
In/Out  
Input  
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time  
to VDDSPD to act as a pullup.  
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6  
Volt operation).  
VDDSPD  
Supply  
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs  
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-  
nized with the input clock )  
RESET  
Input  
Par_In  
Err_Out  
TEST  
Input  
Input  
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)  
Parity error found in the Address and Control bus  
In/Out  
Used by memory bus analysis tools (unused on memory DIMMs)  
Rev. 1.0 July 2008  
6 of 26  
RDIMM  
DDR2 SDRAM  
7.0 Functional Block Diagram  
7.1 512MB, 64Mx72 Module - M393T6553GZ3/M393T6553GZA  
(populated as 1 rank of x8 DDR2 SDRAMs)  
RS0  
DQS0  
DQS4  
DQS0  
DQS4  
DM0/DQS9  
NC/DQS9  
DM4/DQS13  
NC/DQS13  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D0  
D4  
DQS1  
DQS5  
DQS1  
DQS5  
DM1/DQS10  
NC/DQS10  
DM5/DQS14  
NC/DQS14  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ8  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
I/O 0  
I/O 0  
DQ9  
I/O 1  
I/O 1  
D1  
D5  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS2  
DQS6  
DQS2  
DQS6  
DM2/DQS11  
NC/DQS11  
DM6/DQS15  
NC/DQS15  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D2  
D6  
DQS3  
DQS7  
DQS3  
DQS7  
DM3/DQS12  
NC/DQS12  
DM7/DQS16  
NC/DQS16  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D3  
D7  
V
V
V
V
Serial PD  
D0 - D8  
D0 - D8  
D0 - D8  
DDSPD  
DQS8  
Serial PD  
DQS8  
/V  
DD DDQ  
DM8/DQS17  
NC/DQS17  
SCL  
SDA  
REF  
SS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
WP A0 A1 A2  
SA0 SA1 SA2  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D8  
Signals for Address and Command Parity Function (M393T6553GZA)  
Register  
V
V
C0  
C1  
SS  
SS  
1:1  
PPO  
PAR_IN  
100K ohms  
PAR_IN  
R
E
G
I
S0*  
RSO-> CS : DDR2 SDRAMs D0-D8  
QERR  
Err_Out  
BA0-BA1  
A0-A13  
RAS  
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D8  
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8  
RRAS -> RAS : DDR2 SDRAMs D0-D8  
RCAS -> CAS : DDR2 SDRAMs D0-D8  
RWE -> WE : DDR2 SDRAMs D0-D8  
The resistors on Par_In, A13, A14, A15, BA2 and the  
signal line of Err_Out refer to the section: "Register  
Options for Unused Address inputs"  
CAS  
S
T
E
R
WE  
CKE0  
ODT0  
RCKE0 -> CKE : DDR2 SDRAMs D0-D8  
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8  
RST  
RESET  
* S0 connects to DCS and VDD connects to CSR on the register. S1, CKE1 and ODT1 are NC.  
PCK7  
PCK7  
Note :  
CK0  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8  
P
L
L
CK0  
1. DQ-to-I/O wiring may be changed within a byte.  
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.  
3. Unless otherwise noted, resister values are 22 Ohms ± 5%  
PCK7 -> CK : Register  
OE  
RESET  
PCK7 -> CK : Register  
Rev. 1.0 July 2008  
7 of 26  
RDIMM  
DDR2 SDRAM  
7.2 1GB, 128Mx72 Module - M393T2953GZ3 / M393T2953GZA  
(populated as 2 rank of x8 DDR2 SDRAMs)  
RS1  
RS0  
DQS0  
DQS4  
DQS0  
DQS4  
DM0/DQS9  
NC/DQS9  
DM4/DQS13  
NC/DQS13  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
I/O 0  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
D0  
D9  
D4  
D13  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS1  
DQS5  
DQS1  
DQS5  
DM1/DQS10  
NC/DQS10  
DM5/DQS14  
NC/DQS14  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ8  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
DQ9  
I/O 1  
I/O 1  
I/O 1  
I/O 1  
D1  
D10  
D5  
D14  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQS2  
DQS6  
DQS2  
DQS6  
DM2/DQS11  
NC/DQS11  
DM6/DQS15  
NC/DQS15  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D2  
D11  
D6  
D15  
DQS3  
DQS7  
DQS3  
DQS7  
DM3/DQS12  
NC/DQS12  
DM7/DQS16  
NC/DQS16  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O 0  
I/O 0  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D3  
D12  
D7  
D16  
DQS8  
V
V
V
V
Serial PD  
D0 - D17  
D0 - D17  
D0 - D17  
DDSPD  
DQS8  
Serial PD  
DM8/DQS17  
NC/DQS17  
/V  
DD DDQ  
SCL  
SDA  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
DM/ NU/ CS DQS DQS  
RDQS RDQS  
WP A0 A1 A2  
SA0 SA1 SA2  
REF  
SS  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
I/O 0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D8  
D17  
Signals for Address and Command Parity Function (M393T2953GZA)  
Register A  
Register B  
V
V
C0  
C1  
V
V
C0  
C1  
SS  
DD  
DD  
DD  
S0*  
RSO-> CS : DDR2 SDRAMs D0-D8  
RS1-> CS : DDR2 SDRAMs D9-D17  
PPO  
S1*  
1:2  
PPO  
PAR_IN  
PAR_IN  
PAR_IN  
BA0-BA1  
A0-A13  
RAS  
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17  
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17  
RRAS -> RAS : DDR2 SDRAMs D0-D17  
RCAS -> CAS : DDR2 SDRAMs D0-D17  
RWE -> WE : DDR2 SDRAMs D0-D17  
R
E
G
I
QERR  
Err_Out  
QERR  
100K ohms  
The resistors on Par_In, A13, A14, A15, BA2 and the  
signal line of Err_Out refer to the section: "Register  
Options for Unused Address inputs"  
CAS  
WE  
CKE0  
CKE1  
ODT0  
ODT1  
S
T
E
R
RCKE0 -> CKE : DDR2 SDRAMs D0-D8  
RCKE1 -> CKE : DDR2 SDRAMs D9-D17  
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8  
CK0  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17  
RODT1 -> ODT1 : DDR2 SDRAMs D9-D17  
P
L
L
RST  
RESET**  
PCK7**  
CK0  
PCK7 -> CK : Register  
PCK7**  
OE  
RESET  
PCK7 -> CK : Register  
* S0 connects to DCS and S1 connects to CSR on a Register,  
S1 connects to DCS and S0 connects to CSR on another Register.  
Note :  
1. DQ-to-I/O wiring may be changed per nibble.  
** RESET, PCK7 and PCK7 connects to both Registers.  
Other signals connect to one of two Registers.  
2. Unless otherwise noted, resister values are 22 Ohms ± 5%  
3. RS0 and RS1 alternate between the back and front sides of the DIMM  
Rev. 1.0 July 2008  
8 of 26  
RDIMM  
DDR2 SDRAM  
7.3 1GB, 128Mx72 Module - M393T2950GZ3/M393T2950GZA  
(populated as 1 rank of x4 DDR2 SDRAMs)  
V
SS  
RS0  
DQS0  
DQS0  
DM0/DQS9  
NC/DQS9  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ0  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 0  
I/O 0  
DQ1  
DQ2  
DQ3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D0  
D9  
DQS1  
DM1/DQS10  
DQS1  
NC/DQS10  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ8  
DQ12  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ9  
DQ13  
DQ14  
DQ15  
D1  
D10  
DQ10  
DQ11  
DQS2  
DQS2  
DM2/DQS11  
NC/DQS11  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ16  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ17  
DQ18  
DQ19  
D2  
D11  
DQS3  
DM3/DQS12  
DQS3  
NC/DQS12  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ24  
DQ28  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ25  
DQ26  
DQ27  
DQ29  
DQ30  
DQ31  
D3  
D12  
DQS4  
DM4/DQS13  
DQS4  
NC/DQS13  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ32  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ33  
DQ34  
DQ35  
D4  
D13  
DQS5  
DM5/DQS14  
DQS5  
NC/DQS14  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ40  
DQ44  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ41  
DQ42  
DQ43  
DQ45  
DQ46  
DQ47  
D5  
D14  
DQS6  
DM6/DQS15  
DQS6  
NC/DQS15  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
Serial PD  
DQ48  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ49  
DQ50  
DQ51  
D6  
D15  
SCL  
SDA  
WP A0 A1 A2  
SA0 SA1 SA2  
DQS7  
DM7DQS16  
DQS7  
NC/DQS16  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ56  
DQ60  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ57  
DQ58  
DQ59  
DQ61  
DQ62  
DQ63  
D7  
D16  
DQS8  
DM8/DQS17  
V
V
V
V
Serial PD  
D0 - D17  
D0 - D17  
D0 - D17  
DDSPD  
DQS8  
NC/DQS17  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
/V  
DD DDQ  
CB0  
CB4  
CB5  
CB6  
CB7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
CB1  
CB2  
CB3  
D8  
D17  
REF  
SS  
1:2  
Signals for Address and Command Parity Function (M393T2950GZA)  
R
E
G
I
S0*  
RSO-> CS : DDR2 SDRAMs D0-D17  
BA0-BA1  
A0-A13  
RAS  
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D17  
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17  
RRAS -> RAS : DDR2 SDRAMs D0-D17  
RCAS -> CAS : DDR2 SDRAMs D0-D17  
RWE -> WE : DDR2 SDRAMs D0-D17  
Register A  
Register B  
V
C0  
C1  
V
V
C0  
C1  
SS  
DD  
DD  
DD  
V
PPO  
CAS  
S
T
E
R
PPO  
PAR_IN  
100K ohms  
PAR_IN  
PAR_IN  
WE  
QERR  
Err_Out  
QERR  
CKE0  
ODT0  
RCKE0 -> CKE : DDR2 SDRAMs D0-D17  
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17  
The resistors on Par_In, A13, A14, A15, BA2 and the  
signal line of Err_Out refer to the section: "Register  
Options for Unused Address inputs"  
RST  
RESET**  
PCK7**  
Note :  
1. DQ-to-I/O wiring may be changed per nibble.  
2. Unless otherwise noted, resister values are 22 Ohms ± 5%  
PCK7**  
CK0  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8  
* S0 connects to DCS of Register1 and CSR of Register2. CSR of  
register 1 and DCS of register 2 connects to VDD.  
P
L
L
CK0  
** RESET, PCK7 and PCK7 connects to both Registers. Other  
PCK7 -> CK : Register  
OE  
RESET  
signals connect to one of two Registers. S1, CKE1 and ODT1 are NC.  
PCK7 -> CK : Register  
Rev. 1.0 July 2008  
9 of 26  
RDIMM  
DDR2 SDRAM  
7.4 2GB, 256Mx72 Module - M393T5750GZ3/M393T5750GZA  
(populated as 2 rank of x4 DDR2 SDRAMs)  
VSS  
RS1  
RS0  
DQS0  
DQS0  
DM0/DQS9  
NC/DQS9  
DM  
CS DQS DQS  
DM/ CS DQS DQS  
I/O 0  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ0  
DQ4  
DQ5  
DQ6  
DQ7  
I/O 0  
I/O 0  
I/O 0  
DQ1  
DQ2  
DQ3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
I/O 1  
I/O 2  
I/O 3  
D0  
D18  
D9  
D27  
DQS1  
DM1/DQS10  
DQS1  
NC/DQS10  
DM  
CS DQS DQS  
DM/ CS DQS DQS  
I/O 0  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ8  
DQ12  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ9  
DQ13  
DQ14  
DQ15  
I/O 1  
I/O 2  
I/O 3  
D1  
D19  
D10  
D28  
DQ10  
DQ11  
DQS2  
DQS2  
DM2/DQS11  
NC/DQS11  
DM  
CS DQS DQS  
DM/ CS DQS DQS  
I/O 0  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ16  
DQ20  
DQ21  
DQ22  
DQ23  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ17  
DQ18  
DQ19  
I/O 1  
I/O 2  
I/O 3  
D2  
D20  
D11  
D29  
DQS3  
DM3/DQS12  
DQS3  
NC/DQS12  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ24  
DQ28  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ25  
DQ26  
DQ27  
DQ29  
DQ30  
DQ31  
D3  
D21  
D12  
D30  
DQS4  
DM4/DQS13  
DQS4  
NC/DQS13  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ32  
DQ36  
DQ37  
DQ38  
DQ39  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ33  
DQ34  
DQ35  
D4  
D22  
D13  
D31  
DQS5  
DM5/DQS14  
DQS5  
NC/DQS14  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ40  
DQ44  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ41  
DQ42  
DQ43  
DQ45  
DQ46  
DQ47  
D5  
D23  
D14  
D32  
DQS6  
DM6/DQS15  
DQS6  
NC/DQS15  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DQ48  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ49  
DQ50  
DQ51  
D6  
D24  
D15  
D33  
Serial PD  
DQS7  
DM7DQS16  
SCL  
DQS7  
NC/DQS16  
SDA  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
WP A0 A1 A2  
DQ56  
DQ60  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
DQ57  
DQ58  
DQ59  
DQ61  
DQ62  
DQ63  
D7  
D25  
D16  
D34  
SA0 SA1 SA2  
Serial PD  
V
V
V
V
DDSPD  
DQS8  
DM8/DQS17  
DQS8  
NC/DQS17  
/V  
D0 - D35  
D0 - D35  
D0 - D35  
DD DDQ  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
DM  
CS DQS DQS  
CB0  
CB4  
CB5  
CB6  
CB7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
REF  
SS  
CB1  
CB2  
CB3  
D8  
D26  
D17  
D35  
S0*  
S1*  
BA0-BA1  
A0-A13  
RAS  
CAS  
WE  
CKE0  
CKE1  
ODT0  
ODT1  
RSO-> CS : DDR2 SDRAMs D0-D17  
RS1-> CS : DDR2 SDRAMs D18-D35  
RBA0-RBA1 -> BA0-BA1 : DDR2 SDRAMs D0-D35  
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35  
RRAS -> RAS : DDR2 SDRAMs D0-D35  
RCAS -> CAS : DDR2 SDRAMs D0-D35  
RWE -> WE : DDR2 SDRAMs D0-D35  
RCKE0 -> CKE : DDR2 SDRAMs D0-D17  
RCKE1 -> CKE : DDR2 SDRAMs D18-D35  
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17  
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35  
1:2  
R
E
G
I
Signals for Address and Command Parity Function (M393T5750GZA)  
Register A  
Register B  
V
C0  
C1  
V
V
C0  
C1  
SS  
DD  
DD  
DD  
V
PPO  
PPO  
PAR_IN  
PAR_IN  
PAR_IN  
S
T
QERR  
Err_Out  
QERR  
100K ohms  
E
R
The resistors on Par_In, A13, A14, A15, BA2 and the  
signal line of Err_Out refer to the section: "Register  
Options for Unused Address inputs"  
RST  
RESET**  
PCK7**  
PCK7**  
CK0  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35  
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35  
* S0 connects to DCS and S1 connects to CSR on a pair of Registers,  
S1 connects to DCS and S0 connects to CSR on another pair of Registers.  
P
L
L
CK0  
** RESET, PCK7 and PCK7 connects to all Registers.  
Other signals connect to one pair of four Registers.  
PCK7 -> CK : Register  
OE  
RESET  
PCK7 -> CK : Register  
Rev. 1.0 July 2008  
10 of 26  
RDIMM  
DDR2 SDRAM  
8.0 Absolute Maximum DC Ratings  
Symbol  
Parameter  
Rating  
Units  
V
Notes  
Voltage on VDD pin relative to VSS  
VDD  
- 1.0 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
- 0.5 V ~ 2.3 V  
-55 to +100  
1
1
Voltage on VDDQ pin relative to VSS  
Voltage on VDDL pin relative to VSS  
Voltage on any pin relative to VSS  
Storage Temperature  
VDDQ  
VDDL  
V
V
1
V
IN, VOUT  
TSTG  
Note :  
V
1
°C  
1, 2  
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and  
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2  
standard.  
9.0 AC & DC Operating Conditions  
9.1 Recommended DC Operating Conditions (SSTL - 1.8)  
Rating  
Typ.  
1.8  
Symbol  
Parameter  
Units  
Notes  
Min.  
1.7  
Max.  
1.9  
VDD  
VDDL  
VDDQ  
VREF  
VTT  
Supply Voltage  
V
V
Supply Voltage for DLL  
Supply Voltage for Output  
Input Reference Voltage  
Termination Voltage  
1.7  
1.8  
1.9  
4
4
1.7  
1.8  
1.9  
V
0.49*VDDQ  
VREF-0.04  
0.50*VDDQ  
VREF  
0.51*VDDQ  
VREF+0.04  
mV  
V
1,2  
3
Note : There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must be less than or equal  
to VDD  
.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5  
x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ  
2. Peak to peak AC noise on VREF may not exceed +/-2% VREF(DC).  
3. VTT of transmitting device must track VREF of receiving device.  
.
4. AC parameters are measured with VDD, VDDQ and VDDL tied together.  
Rev. 1.0 July 2008  
11 of 26  
RDIMM  
DDR2 SDRAM  
9.2 Operating Temperature Condition  
Symbol  
TOPER  
Parameter  
Operating Temperature  
Rating  
0 to 95  
Units  
°C  
Notes  
1, 2  
Note :  
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2  
standard.  
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self  
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.  
9.3 Input DC Logic Level  
Symbol  
VIH(DC)  
VIL(DC)  
Parameter  
DC input logic high  
DC input logic low  
Min.  
VREF + 0.125  
- 0.3  
Max.  
VDDQ + 0.3  
VREF - 0.125  
Units  
V
V
Notes  
9.4 Input AC Logic Level  
DDR2-400, DDR2-533  
DDR2-667, DDR2-800  
Symbol  
Parameter  
Units  
Min.  
Max.  
Min.  
VREF + 0.200  
Max.  
VIH(AC)  
VIL(AC)  
AC input logic high  
AC input logic low  
VREF + 0.250  
-
-
V
V
VREF - 0.250  
VREF - 0.200  
9.5 AC Input Test Conditions  
Symbol  
Condition  
Value  
Units  
Notes  
VREF  
VSWING(MAX)  
SLEW  
Input reference voltage  
0.5 * VDDQ  
1.0  
V
V
1
1
Input signal maximum peak to peak swing  
Input signal minimum slew rate  
1.0  
V/ns  
2, 3  
Note :  
1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the device under test.  
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising edges and the range from VREF to VIL(AC)  
max for falling edges as shown in the below figure.  
3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative  
transitions.  
V
V
V
V
V
V
V
DDQ  
(AC) min  
IH  
IH  
(DC) min  
V
SWING(MAX)  
REF  
(DC) max  
IL  
IL  
(AC) max  
SS  
delta TF  
V
delta TR  
Rising Slew =  
- V (AC) max  
IL  
V
(AC) min - V  
delta TR  
REF  
IH  
REF  
Falling Slew =  
delta TF  
< AC Input Test Signal Waveform >  
Rev. 1.0 July 2008  
12 of 26  
RDIMM  
DDR2 SDRAM  
10.0 IDD Specification Parameters Definition  
(IDD values are for full operating range of Voltage and Temperature)  
Symbol  
Proposed Conditions  
Units  
Note  
Operating one bank active-precharge current;  
IDD0  
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands;  
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
mA  
Operating one bank active-read-precharge current;  
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =  
tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern  
is same as IDD4W  
IDD1  
mA  
Precharge power-down current;  
IDD2P  
IDD2Q  
IDD2N  
IDD3P  
IDD3N  
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are  
FLOATING  
mA  
mA  
mA  
Precharge quiet standby current;  
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data  
bus inputs are FLOATING  
Precharge standby current;  
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING;  
Data bus inputs are SWITCHING  
Active power-down current;  
Fast PDN Exit MRS(12) = 0mA  
mA  
mA  
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus  
inputs are STABLE; Data bus inputs are FLOATING  
Slow PDN Exit MRS(12) = 1mA  
Active standby current;  
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid  
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
mA  
mA  
Operating burst write current;  
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP  
= tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus  
inputs are SWITCHING  
IDD4W  
IDD4R  
Operating burst read current;  
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRAS-  
max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-  
ING; Data pattern is same as IDD4W  
mA  
mA  
Burst auto refresh current;  
IDD5B  
IDD6  
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands;  
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING  
Self refresh current;  
Normal  
mA  
mA  
CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are  
FLOATING; Data bus inputs are FLOATING  
Low Power  
Operating bank interleave read current;  
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC =  
tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid  
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the fol-  
lowing page for detailed timing conditions  
IDD7  
mA  
Rev. 1.0 July 2008  
13 of 26  
RDIMM  
DDR2 SDRAM  
11.0 Operating Current Table :  
11.1 M393T6553GZ3 / M393T6553GZA : 512MB(64Mx8 *9) Module  
(TA=0oC, VDD= 1.9V)  
Symbol  
IDD0  
IDD1  
F7(800@CL=6)  
E6(667@CL=5)  
D5(533@CL=4)  
CC(400@CL=3)  
Units  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Notes  
765  
855  
72  
675  
810  
72  
675  
765  
72  
630  
765  
72  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6*  
315  
360  
270  
108  
540  
990  
1260  
990  
72  
315  
360  
270  
108  
495  
900  
1170  
945  
72  
270  
315  
270  
108  
450  
765  
945  
945  
72  
270  
315  
270  
108  
450  
720  
855  
900  
72  
IDD7  
1890  
1575  
1575  
1575  
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
11.2 M393T6553GZ3 / M393T6553GZA : 512MB(64Mx8 *9) Module  
- considering Register and PLL current value  
(TA=0oC, VDD= 1.9V)  
Symbol  
IDD0  
IDD1  
F7(800@CL=6)  
1355  
1495  
552  
E6(667@CL=5)  
1175  
1360  
512  
D5(533@CL=4)  
1085  
1225  
472  
CC(400@CL=3)  
950  
Units  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Notes  
1135  
432  
590  
615  
580  
418  
780  
1030  
1205  
1210  
72  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6*  
845  
840  
820  
658  
1080  
1510  
1850  
1660  
72  
775  
780  
740  
578  
660  
675  
660  
498  
965  
850  
1350  
1680  
1495  
72  
1145  
1375  
1375  
72  
IDD7  
2580  
2155  
2045  
1935  
* IDD6 = DRAM current + standby current of PLL and Register  
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
Rev. 1.0 July 2008  
14 of 26  
RDIMM  
DDR2 SDRAM  
(TA=0oC, VDD= 1.9V)  
11.3 M393T2953GZ3 / M393T2953GZA : 1GB(64Mx8 *18) Module  
Symbol  
IDD0  
IDD1  
F7(800@CL=6)  
1125  
1215  
144  
E6(667@CL=5)  
1035  
1170  
144  
D5(533@CL=4)  
990  
CC(400@CL=3)  
945  
Units  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Notes  
1080  
144  
540  
630  
540  
216  
765  
1080  
1260  
1260  
144  
1080  
144  
540  
630  
540  
216  
765  
1035  
1170  
1215  
144  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6*  
630  
720  
540  
216  
630  
720  
540  
216  
900  
855  
1350  
1620  
1350  
144  
1260  
1530  
1305  
144  
IDD7  
2250  
1935  
1890  
1890  
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
11.4 M393T2953GZ3 / M393T2953GZA : 1GB(64Mx8 *18) Module  
- considering Register and PLL current value  
(TA=0oC, VDD= 1.9V)  
Symbol  
IDD0  
IDD1  
F7(800@CL=6)  
1815  
1985  
784  
E6(667@CL=5)  
1625  
1830  
724  
D5(533@CL=4)  
1480  
1630  
664  
CC(400@CL=3)  
1335  
1520  
604  
Units  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Notes  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6*  
1340  
1290  
1270  
946  
1460  
2000  
2410  
2180  
144  
1250  
1220  
1170  
1070  
1060  
1070  
746  
980  
990  
970  
646  
846  
1345  
1820  
2210  
1985  
144  
1185  
1115  
1550  
1830  
1790  
144  
1415  
1630  
1595  
144  
IDD7  
3280  
2805  
2600  
2440  
* IDD6 = DRAM current + standby current of PLL and Register  
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
Rev. 1.0 July 2008  
15 of 26  
RDIMM  
DDR2 SDRAM  
(TA=0oC, VDD= 1.9V)  
11.5 M393T2950GZ3 / M393T2950GZA : 1GB(128Mx4 *18) Module  
Symbol  
IDD0  
IDD1  
F7(800@CL=6)  
1440  
1620  
144  
E6(667@CL=5)  
1350  
1530  
144  
D5(533@CL=4)  
1350  
1530  
144  
CC(400@CL=3)  
1350  
1530  
144  
Units  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Notes  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6*  
630  
720  
540  
216  
630  
720  
540  
216  
540  
630  
540  
216  
540  
630  
540  
216  
990  
990  
900  
900  
2070  
2250  
2070  
144  
1800  
1980  
1980  
144  
1350  
1530  
1890  
144  
1350  
1530  
1890  
144  
IDD7  
3780  
3150  
3150  
3150  
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
11.6 M393T2950GZ3 / M393T2950GZA : 1GB(128Mx4 *18) Module  
- considering Register and PLL current value  
(TA=0oC, VDD= 1.9V)  
Symbol  
IDD0  
IDD1  
F7(800@CL=6)  
2130  
2390  
784  
E6(667@CL=5)  
1940  
2190  
724  
D5(533@CL=4)  
1840  
CC(400@CL=3)  
1740  
1970  
604  
Units  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Notes  
2080  
664  
1070  
1060  
1070  
746  
1320  
1820  
2100  
2420  
144  
3860  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6*  
1340  
1290  
1270  
946  
1550  
2720  
3040  
2900  
144  
1250  
1220  
1170  
980  
990  
970  
646  
1250  
1730  
1990  
2270  
144  
846  
1480  
2360  
2660  
2660  
144  
IDD7  
4810  
4020  
3700  
* IDD6 = DRAM current + standby current of PLL and Register  
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
Rev. 1.0 July 2008  
16 of 26  
RDIMM  
DDR2 SDRAM  
(TA=0oC, VDD= 1.9V)  
11.7 M393T5750GZ3 / M393T5750GZA : 2GB(128Mx4 *36) Module  
Symbol  
IDD0  
IDD1  
F7(800@CL=6)  
2160  
2340  
288  
E6(667@CL=5)  
2070  
D5(533@CL=4)  
1980  
CC(400@CL=3)  
1980  
Units  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Notes  
2250  
288  
1260  
1440  
1080  
432  
1710  
2520  
2700  
2700  
288  
3870  
2160  
288  
1080  
1260  
1080  
432  
1530  
1980  
2160  
2520  
288  
3780  
2160  
288  
1080  
1260  
1080  
432  
1530  
1980  
2160  
2520  
288  
3780  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6*  
1260  
1440  
1080  
432  
1710  
2790  
2970  
2790  
288  
IDD7  
4500  
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
11.8 M393T5750GZ3 / M393T5750GZA : 2GB(128Mx4 *36) Module  
- considering Register and PLL current value  
(TA=0oC, VDD= 1.9V)  
Symbol  
IDD0  
IDD1  
F7(800@CL=6)  
3180  
E6(667@CL=5)  
2940  
D5(533@CL=4)  
2700  
CC(400@CL=3)  
2550  
Units  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
Notes  
3500  
1238  
2320  
2240  
2170  
1522  
2500  
3780  
4060  
4010  
288  
6210  
3250  
1148  
2180  
2140  
2020  
1372  
2400  
3370  
3640  
3700  
288  
5320  
3000  
1058  
1860  
1860  
1870  
1222  
2120  
2690  
2950  
3300  
288  
4970  
2840  
968  
1720  
1760  
1720  
1072  
2020  
2550  
2800  
3080  
288  
4710  
IDD2P  
IDD2Q  
IDD2N  
IDD3P-F  
IDD3P-S  
IDD3N  
IDD4W  
IDD4R  
IDD5B  
IDD6*  
IDD7  
* IDD6 = DRAM current + standby current of PLL and Register  
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.  
Rev. 1.0 July 2008  
17 of 26  
RDIMM  
DDR2 SDRAM  
12.0 Input/Output Capacitance  
(VDD=1.8V, VDDQ=1.8V, TA=25oC)  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Symbol  
CCK  
Units  
M393T6553GZ3  
M393T6553GZA  
M393T2953GZ3  
M393T2953GZA  
M393T2950GZ3  
M393T2950GZA  
M393T5750GZ3  
M393T5750GZA  
Part-Number  
Input capacitance, CK and CK  
-
-
-
-
11  
12  
12  
10  
-
-
-
-
11  
12  
12  
10  
-
-
-
-
11  
12  
12  
10  
-
-
-
-
11  
12  
12  
10  
Input capacitance, CKE and CS  
Input capacitance, Address, RAS,CAS,WE  
CI1  
CI2  
pF  
Input/output capacitance, DQ, DM, DQS, DQS CIO  
* DM is internally loaded to match DQ and DQS identically.  
13.0 Electrical Characteristics & AC Timing for DDR2-800/667/533/400  
(0 °C < TOPER < 95 °C; VDDQ = 1.8V + 0.1V; VDD = 1.8V + 0.1V)  
13.1 Refresh Parameters by Device Density  
Parameter  
Symbol  
256Mb  
512Mb  
1Gb  
2Gb  
4Gb  
Units  
Refresh to active/Refresh command time  
tRFC  
75  
105  
127.5  
7.8  
195  
327.5  
7.8  
ns  
0 °C ≤ TCASE ≤ 85°C  
7.8  
3.9  
7.8  
3.9  
7.8  
3.9  
µs  
µs  
Average periodic refresh interval  
tREFI  
85 °C < TCASE ≤ 95°C  
3.9  
3.9  
13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin  
Speed  
Bin(CL - tRCD - tRP)  
Parameter  
tCK, CL=3  
tCK, CL=4  
tCK, CL=5  
tCK, CL=6  
tRCD  
DDR2-800(F7)  
6 - 6 - 6  
DDR2-667(E6)  
5 - 5 - 5  
DDR2-533(D5)  
4 - 4 - 4  
DDR2-400(CC)  
3 - 3 - 3  
Units  
min  
max  
min  
max  
min  
5
max  
8
min  
max  
-
-
5
8
5
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
3.75  
3
8
3.75  
3
8
3.75  
3.75  
-
8
5
-
8
-
8
8
8
2.5  
15  
15  
60  
45  
8
-
-
-
-
-
-
15  
15  
60  
45  
-
15  
-
15  
15  
55  
40  
-
tRP  
-
-
-
-
15  
-
-
-
tRC  
60  
-
tRAS  
70000  
70000  
45  
70000  
70000  
Rev. 1.0 July 2008  
18 of 26  
RDIMM  
DDR2 SDRAM  
13.3 Timing parameters by speed grade (DDR2-800 and DDR2-667)  
(Refer to notes for informations related to this table at the component datasheet)  
DDR2-800  
DDR2-667  
Parameter  
Symbol  
Units  
Notes  
min  
-400  
-350  
0.48  
0.48  
max  
400  
min  
max  
450  
DQ output access time from CK/CK  
DQS output access time from CK/CK  
Average clock HIGH pulse width  
Average clock LOW pulse width  
tAC  
-450  
-400  
0.48  
0.48  
ps  
40  
40  
tDQSCK  
tCH(avg)  
tCL(avg)  
350  
400  
ps  
0.52  
0.52  
0.52  
0.52  
tCK(avg)  
tCK(avg)  
35,36  
35,36  
Min(tCL(abs),  
tCH(abs))  
Min(tCL(abs),  
tCH(abs))  
CK half pulse period  
tHP  
x
x
ps  
37  
Average clock period  
tCK(avg)  
tDH(base)  
tDS(base)  
tIPW  
2500  
8000  
3000  
8000  
ps  
ps  
35,36  
DQ and DM input hold time  
125  
x
175  
x
6,7,8,21,28,31  
6,7,8,20,28,31  
DQ and DM input setup time  
50  
x
100  
x
ps  
Control & Address input pulse width for each input  
DQ and DM input pulse width for each input  
Data-out high-impedance time from CK/CK  
DQS/DQS low-impedance time from CK/CK  
DQ low-impedance time from CK/CK  
DQS-DQ skew for DQS and associated DQ signals  
DQ hold skew factor  
0.6  
x
0.6  
x
tCK(avg)  
tCK(avg)  
ps  
tDIPW  
tHZ  
0.35  
x
0.35  
x
x
tAC(max)  
x
tAC(max)  
18,40  
18,40  
18,40  
13  
tLZ(DQS)  
tLZ(DQ)  
tDQSQ  
tQHS  
tAC(min)  
tAC(max)  
tAC(min)  
tAC(max)  
ps  
2* tAC(min)  
tAC(max)  
2* tAC(min)  
tAC(max)  
ps  
x
x
200  
300  
x
x
x
240  
340  
x
ps  
ps  
38  
DQ/DQS output hold time from DQS  
DQS latching rising transitions to associated clock edges  
DQS input HIGH pulse width  
tQH  
tHP - tQHS  
- 0.25  
0.35  
0.35  
0.2  
tHP - tQHS  
-0.25  
0.35  
0.35  
0.2  
ps  
39  
tDQSS  
tDQSH  
tDQSL  
tDSS  
0.25  
x
0.25  
x
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
tCK(avg)  
nCK  
30  
DQS input LOW pulse width  
x
x
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Mode register set command cycle time  
MRS command to ODT update delay  
Write postamble  
x
x
30  
30  
tDSH  
0.2  
x
0.2  
x
tMRD  
2
x
2
x
tMOD  
0
12  
0.6  
x
0
12  
0.6  
x
ns  
32  
10  
tWPST  
tWPRE  
tIH(base)  
tIS(base)  
tRPRE  
tRPST  
0.4  
0.4  
tCK(avg)  
tCK(avg)  
ps  
Write preamble  
0.35  
250  
175  
0.9  
0.35  
275  
200  
0.9  
Address and control input hold time  
Address and control input setup time  
Read preamble  
x
x
5,7,9,23,29  
5,7,9,22,29  
19,41  
x
x
ps  
1.1  
0.6  
x
1.1  
0.6  
x
tCK(avg)  
tCK(avg)  
ns  
Read postamble  
0.4  
0.4  
19,42  
Activate to activate command period for 1KB page size products tRRD  
Activate to activate command period for 2KB page size products tRRD  
7.5  
7.5  
4,32  
10  
x
10  
x
ns  
4,32  
Rev. 1.0 July 2008  
19 of 26  
RDIMM  
DDR2 SDRAM  
DDR2-800  
DDR2-667  
Notes  
Parameter  
Symbol  
Units  
min  
max  
min  
max  
Four Activate Window for 1KB page size products  
Four Activate Window for 2KB page size products  
CAS to CAS command delay  
tFAW  
tFAW  
tCCD  
tWR  
35  
x
x
x
x
x
x
x
x
x
x
x
37.5  
x
x
x
x
x
x
x
x
x
x
x
ns  
ns  
32  
32  
45  
50  
2
2
nCK  
ns  
Write recovery time  
15  
15  
32  
33  
Auto precharge write recovery + precharge time  
Internal write to read command delay  
Internal read to precharge command delay  
Exit self refresh to a non-read command  
Exit self refresh to a read command  
tDAL  
WR + tnRP  
WR + tnRP  
nCK  
ns  
tWTR  
tRTP  
tXSNR  
tXSRD  
tXP  
7.5  
7.5  
24,32  
3,32  
32  
7.5  
7.5  
ns  
tRFC + 10  
tRFC + 10  
ns  
200  
2
200  
2
nCK  
nCK  
nCK  
Exit precharge power down to any command  
Exit active power down to read command  
tXARD  
2
2
1
Exit active power down to read command  
(slow exit, lower power)  
tXARDS  
8 - AL  
x
7 - AL  
x
nCK  
1,2  
CKE minimum pulse width (HIGH and LOW pulse width)  
tCKE  
3
2
x
3
2
x
nCK  
nCK  
ns  
27  
16  
ODT turn-on delay  
ODT turn-on  
tAOND  
tAON  
2
2
tAC(min)  
tAC(max)+0.7  
tAC(min)  
tAC(max)+0.7  
6,16,40  
2*tCK(avg)  
2*tCK(avg)  
ODT turn-on (Power-Down mode)  
tAONPD  
tAC(min)+2  
tAC(min)+2  
ns  
+tAC(max)+1  
+tAC(max)+1  
ODT turn-off delay  
ODT turn-off  
tAOFD  
tAOF  
2.5  
2.5  
2.5  
2.5  
nCK  
ns  
17,45  
tAC(min)  
tAC(max)+0.6  
tAC(min)  
tAC(max)+0.6  
17,43,45  
2.5*tCK(avg)+  
tAC(max)+1  
2.5*tCK(avg)+  
tAC(max)+1  
ODT turn-off (Power-Down mode)  
tAOFPD  
tAC(min)+2  
tAC(min)+2  
ns  
ODT to power down entry latency  
ODT power down exit latency  
OCD drive mode output delay  
tANPD  
tAXPD  
tOIT  
3
8
0
x
x
3
8
0
x
x
nCK  
nCK  
ns  
12  
12  
32  
15  
Minimum time clocks remains ON after CKE asynchronously  
drops LOW  
tIS+tCK(avg)  
+tIH  
tIS+tCK(avg)  
+tIH  
tDelay  
x
x
ns  
Rev. 1.0 July 2008  
20 of 26  
RDIMM  
DDR2 SDRAM  
13.4 Timing parameters by speed grade (DDR2-533 and DDR2-400)  
(Refer to notes for informations related to this table at the component datasheet)  
DDR2-533  
DDR2-400  
Parameter  
Symbol  
Units  
Notes  
min  
max  
min  
-600  
-500  
0.45  
0.45  
max  
DQ output access time from CK/CK  
DQS output access time from CK/CK  
CK HIGH pulse width  
tAC  
-500  
500  
600  
ps  
ps  
tDQSCK  
tCH  
-450  
450  
500  
0.45  
0.55  
0.55  
tCK  
tCK  
ps  
CK LOW pulse width  
tCL  
0.45  
0.55  
0.55  
CK half pulse period  
tHP  
Min(tCL, tCH)  
x
Min(tCL, tCH)  
x
11,12  
15  
Clock cycle time, CL=x  
tCK  
3750  
8000  
5000  
275  
8000  
ps  
DQ and DM input hold time (differential strobe)  
DQ and DM input setup time (differential strobe)  
DQ and DM input hold time (single-ended strobe)  
DQ and DM input setup time (single-ended strobe)  
Control & Address input pulse width for each input  
DQ and DM input pulse width for each input  
Data-out high-impedance time from CK/CK  
DQS(/DQS) low-impedance time from CK/CK  
DQ low-impedance time from CK/CK  
DQS-DQ skew for DQS and associated DQ signals  
DQ hold skew factor  
tDH(base)  
tDS(base)  
tDH1(base)  
tDS1(base)  
tIPW  
225  
x
x
ps  
6,7,8,21,28  
6,7,8,20,28  
6,7,8,26  
6,7,8,25  
100  
x
150  
x
ps  
-25  
x
25  
x
ps  
-25  
x
25  
x
ps  
0.6  
x
0.6  
x
tCK  
tCK  
ps  
tDIPW  
tHZ  
0.35  
x
0.35  
x14  
x
x
tAC(max)  
tAC(max)  
18  
18  
18  
13  
12  
tLZ(DQS)  
tLZ(DQ)  
tDQSQ  
tQHS  
tAC(min)  
tAC(max)  
tAC(min)  
2* tAC(min)  
x
tAC(max)  
ps  
2* tAC(min)  
tAC(max)  
tAC(max)  
ps  
x
x
300  
400  
x
350  
450  
x
ps  
x
ps  
DQ/DQS output hold time from DQS  
DQS latching rising transitions to associated clock edges  
DQS input HIGH pulse width  
tQH  
tHP - tQHS  
-0.25  
0.35  
0.35  
0.2  
tHP - tQHS  
-0.25  
0.35  
0.35  
0.2  
ps  
tDQSS  
tDQSH  
tDQSL  
tDSS  
0.25  
x
0.25  
x
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
ns  
DQS input LOW pulse width  
x
x
DQS falling edge to CK setup time  
DQS falling edge hold time from CK  
Mode register set command cycle time  
MRS command to ODT update delay  
Write postamble  
x
x
tDSH  
0.2  
x
0.2  
x
tMRD  
2
x
2
x
tMOD  
0
12  
0.6  
x
0
12  
0.6  
x
tWPST  
tWPRE  
tIH(base)  
tIS(base)  
tRPRE  
tRPST  
tRRD  
0.4  
0.4  
tCK  
tCK  
ps  
10  
Write preamble  
0.35  
375  
250  
0.9  
0.35  
475  
Address and control input hold time  
Address and control input setup time  
Read preamble  
x
x
5,7,9,23  
x
350  
x
ps  
5,7,9,22  
1.1  
0.6  
x
0.9  
1.1  
0.6  
x
tCK  
tCK  
ns  
19  
19  
4
Read postamble  
0.4  
0.4  
Active to active command period for 1KB page size products  
Active to active command period for 2KB page size products  
7.5  
7.5  
tRRD  
10  
x
10  
x
ns  
4
Rev. 1.0 July 2008  
21 of 26  
RDIMM  
DDR2 SDRAM  
DDR2-533  
DDR2-400  
Parameter  
Symbol  
tFAW  
Units  
Notes  
min  
37.5  
50  
max  
min  
37.5  
50  
max  
Four Activate Window for 1KB page size products  
Four Activate Window for 2KB page size products  
CAS to CAS command delay  
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
ns  
ns  
tFAW  
tCCD  
tWR  
2
2
tCK  
ns  
Write recovery time  
15  
15  
Auto precharge write recovery + precharge time  
Internal write to read command delay  
Internal read to precharge command delay  
Exit self refresh to a non-read command  
Exit self refresh to a read command  
tDAL  
WR+tRP  
WR+tRP  
tCK  
ns  
14  
24  
3
tWTR  
tRTP  
tXSNR  
tXSRD  
tXP  
7.5  
10  
7.5  
7.5  
ns  
tRFC + 10  
tRFC + 10  
ns  
200  
2
200  
2
tCK  
tCK  
tCK  
Exit precharge power down to any non-read command  
Exit active power down to read command  
tXARD  
2
2
1
Exit active power down to read command  
(slow exit, lower power)  
tXARDS  
6 - AL  
x
6 - AL  
x
tCK  
1,2  
CKE minimum pulse width (HIGH and LOW pulse width)  
tCKE  
3
2
x
3
2
x
tCK  
tCK  
ns  
27  
16  
16  
ODT turn-on delay  
ODT turn-on  
tAOND  
tAON  
2
2
tAC(min)  
tAC(max)+1  
tAC(min)  
tAC(max)+1  
2tCK+  
2tCK+  
ODT turn-on (Power-Down mode)  
ODT turn-off delay  
tAONPD  
tAOFD  
tAOF  
tAC(min)+2  
2.5  
tAC(min)+2  
2.5  
ns  
tCK  
ns  
tAC(max)+1  
tAC(max)+1  
2.5  
2.5  
17,44  
17,44  
tAC(max)  
+ 0.6  
tAC(max)  
+ 0.6  
ODT turn-off  
tAC(min)  
tAC(min)  
2.5tCK+  
2.5tCK+  
ODT turn-off (Power-Down mode)  
tAOFPD  
tAC(min)+2  
tAC(min)+2  
ns  
tAC(max)+1  
tAC(max)+1  
ODT to power down entry latency  
ODT power down exit latency  
OCD drive mode output delay  
tANPD  
tAXPD  
tOIT  
3
8
0
x
x
3
8
0
x
x
tCK  
tCK  
ns  
12  
12  
32  
15  
Minimum time clocks remains ON after CKE asynchronously  
drops LOW  
tDelay  
tIS+tCK+tIH  
x
tIS+tCK+tIH  
x
ns  
Rev. 1.0 July 2008  
22 of 26  
RDIMM  
DDR2 SDRAM  
14.0 Physical Dimensions  
14.1 64Mbx8 based 64Mx72 Module (1 Rank)  
Units : Millimeters  
2.70  
- M393T6553GZ3 / M393T6553GZA  
133.35  
30.00  
PLL  
1.0 max  
1.27 ± 0.10  
A
B
63.00  
55.00  
3.00  
5.00  
4.00  
0.80±0.05  
0.20  
4.00  
3.80  
4.00  
2.50  
1.00  
1.50±0.10  
Detail A  
Detail B  
The used device is 64M x8 DDR2 SDRAM, FBGA.  
DDR2 SDRAM Part NO : K4T51083QG  
Rev. 1.0 July 2008  
23 of 26  
RDIMM  
DDR2 SDRAM  
14.2 64Mbx8/128Mbx4 based 128Mx72 Module (2/1 Ranks)  
Units : Millimeters  
- M393T2953GZ3 / M393T2953GZA / M393T2950GZ3 / M393T2950GZA  
133.35  
4.00  
30.00  
PLL  
1.0 max  
1.7 max  
1.27 ± 0.10  
A
B
63.00  
55.00  
3.00  
5.00  
4.00  
0.80±0.05  
0.20  
4.00  
3.80  
4.00  
2.50  
1.00  
1.50±0.10  
Detail A  
Detail B  
The used device is 64M x8 / 128M x4 DDR2 SDRAM, FBGA.  
DDR2 SDRAM Part NO : K4T51083QG / K4T51043QG  
Rev. 1.0 July 2008  
24 of 26  
RDIMM  
DDR2 SDRAM  
14.3 128Mbx4 based 256Mx72 Module (2 Ranks)  
- M393T5750GZ3/M393T5750GZA  
Units : Millimeters  
133.35  
PLL  
4.00  
30.00  
1.0 max  
1.7 max  
1.27 ± 0.10  
A
B
63.00  
55.00  
3.00  
5.00  
4.00  
0.80±0.05  
0.20  
4.00  
3.80  
4.00  
2.50  
1.00  
1.50±0.10  
Detail A  
Detail B  
The used device is 128M x4 DDR2 SDRAM, FBGA.  
DDR2 SDRAM Part NO : K4T51043QG  
Rev. 1.0 July 2008  
25 of 26  
RDIMM  
DDR2 SDRAM  
15.0 240 Pin DDR2 Registered DIMM Clock Topology  
0ns (nominal)  
PLL  
DDR2 SDRAM  
120 ohms  
OUT1  
CK0  
120 ohms  
IN  
DDR2 SDRAM  
Reg.A  
CK0  
120 ohms  
OUTN  
120 ohms  
C
C
Feedback In  
Feedback Out  
Reg.B  
Note:  
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).  
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.  
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.  
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.  
Rev. 1.0 July 2008  
26 of 26  

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