M393T5168AZA-CCC [SAMSUNG]
DDR DRAM Module, 512MX72, 0.6ns, CMOS, ROHS COMPLIANT, DIMM-240;
| 型号： | M393T5168AZA-CCC |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 512MX72, 0.6ns, CMOS, ROHS COMPLIANT, DIMM-240 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总21页 (文件大小：521K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered SDRAM MODULE
240pin Registered Module based on 1Gb A-die
72-bit ECC
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Revision History
Revision
1.0
Month
July
Year
2005
2005
History
- Initial Release
- Revised IDD Current Values
1.1
Aug.
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
DDR2 Unbuffered DIMM Ordering Information
Part Number
Density Organization
Component Composition
128Mx8(K4T1G084QA)*9EA
128Mx8(K4T1G084QA)*9EA
128Mx8(K4T1G084QA)*18EA
128Mx8(K4T1G084QA)*18EA
256Mx4(K4T1G044QA)*18EA
256Mx4(K4T1G044QA)*18EA
st.512Mx4(K4T2G064QA)*18EA
st.512Mx4(K4T2G064QA)*18EA
Number of Rank
Parity Register Height
M393T2863AZ3-CD5/CC
M393T2863AZA-CE6/D5/CC
M393T5663AZ3-CD5/CC
M393T5663AZA-CE6/D5/CC
M393T5660AZ3-CD5/CC
M393T5660AZA-CE6/D5/CC
M393T5168AZ0-CD5/CC
M393T5168AZA-CE6/D5/CC
1GB
1GB
2GB
2GB
2GB
2GB
4GB
4GB
128Mx72
128Mx72
256Mx72
256Mx72
256Mx72
256Mx72
512Mx72
512Mx72
1
1
2
2
1
1
2
2
X
O
X
O
X
O
X
O
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Note: "A" of Part number(12th digit) stand for Parity Register products.
Features
• Performance range
E6(DDR2-667)
D5(DDR2-533)
CC(DDR2-400)
Unit
Mbps
Mbps
Mbps
CK
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
400
533
400
400
-
667
533
5-5-5
4-4-4
3-3-3
• JEDEC standard 1.8V ± 0.1V Power Supply
• V = 1.8V ± 0.1V
DDQ
• 200 MHz f for 400Mb/sec/pin, 267MHz f for 533Mb/sec/pin, 333MHz f for 667Mb/sec/pin
CK
CK
CK
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 3, 4, 5
• Programmable Additive Latency: 0, 1 , 2 , 3 and 4
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8 (Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination with selectable values(50/75/150 ohms or disable)
• PASR(Partial Array Self Refresh)
• Average Refresh Period 7.8us at lower than a T
85°C, 3.9us at 85°C < T
< 95 °C
CASE
CASE
- support High Temperature Self-Refresh rate enable feature
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 68ball FBGA - 256Mx4/128Mx8, 56ball BGA - st.512Mbx4
• All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram..
Address Configuration
Organization
Row Address
A0-A13
Column Address
A0-A9
Bank Address
BA0-BA2
BA0-BA2
Auto Precharge
128Mx8(1Gb) based Module
64Mx16(1Gb) based Module
A10
A10
A0-A12
A0-A9
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Pin Configurations (Front side/Back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
SS
Pin
61
Front
A4
Pin
181
Back
DDQ
Pin
91
Front
SS
Pin
Back
1
V
121
V
31
DQ19
151
V
V
V
211 DM5/DQS14
REF
SS
2
3
4
5
6
7
8
9
V
DQ0
DQ1
122
123
124
DQ4
DQ5
32
33
34
35
36
37
38
39
40
41
42
43
V
DQ24
DQ25
152
153
154
DQ28
DQ29
62
63
64
V
DDQ
A2
182
183
184
A3
A1
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
DQS5
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC(TEST)
V
SS
DQS6
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
212 NC/DQS14
SS
SS
213
214
215
216
217
218
219
220
221
222
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
RFU
RFU
V
V
V
V
SS
SS
DD
DD
V
125 DM0/DQS9
V
155 DM3/DQS12
156 NC/DQS12
KEY
SS
SS
DQS0
DQS0
126
127
128
129
130
131
132
133
NC/DQS9
DQS3
DQS3
V
DQ26
DQ27
V
CB0
CB1
V
DQS8
DQS8
V
65
66
67
68
69
70
71
72
V
V
V
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
CK0
CK0
SS
SS
DD
V
157
158
159
160
161
162
163
V
SS
SS
V
DQ6
DQ7
DQ30
DQ31
V
SS
SS
DD
DQ2
DQ3
NC/Par_In
A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
V
V
SS
SS
DD
DD
V
DQ12
DQ13
CB4
CB5
A10/AP
BA0
BA1
SS
SS
DQ8
DQ9
V
V
SS
DDQ
V
V
V
RAS
S0
223 DM6/DQS15
224 NC/DQS15
SS
SS
DDQ
V
134 DM1/DQS10 44
135 NC/DQS10
164 DM8/DQS17 73
165 NC/DQS17
WE
CAS
SS
SS
DQS1
DQS1
45
46
47
48
49
50
51
52
53
54
55
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
V
225
226
227
228
229
230
231
V
SS
DQ54
DQ55
DDQ
136
137
138
139
140
141
142
143
144
145
V
166
167
168
169
170
171
172
173
174
V
V
ODT0
A13
SS
SS
DDQ
4
V
RFU
RFU
CB6
CB7
SS
SS
S1
RESET
NC
CB2
CB3
V
ODT1
V
V
SS
DQ60
DQ61
DD
V
V
V
V
SS
SS
DDQ
SS
V
DQ14
DQ15
V
V
SS
DQ32
DQ33
V
SS
DQS4
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
DQ36
DQ37
SS
SS
DDQ
4
DQ10
DQ11
V
V
SS
DDQ
CKE1
V
CKE0
V
V
V
SS
DQS7
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
232 DM7/DQS16
233 NC/DQS16
SS
DD
SS
V
DQ20
DQ21
V
NC
NC
202 DM4/DQS13 113
203 NC/DQS13
SS
DD
DQ16
DQ17
BA2
114
115
116
117
118
119
120
234
235
236
237
238
239
240
V
SS
DQ62
DQ63
V
SS
VDDSPD
SA0
V
NC/Err_Out 175
V
204
205
206
207
208
V
SS
DDQ
A12
SS
V
146 DM2/DQS11 56
V
176
177
178
179
180
DQ38
DQ39
SS
DDQ
DQS2
DQS2
147
148
149
150
NC/DQS11
57
58
59
60
A11
A7
A9
V
V
V
SS
DD
SS
V
DQ22
DQ23
V
A8
A6
DQ44
DQ45
SS
DD
DQ18
A5
89
90
209
210
SA1
V
SS
NC = No Connect, RFU = Reserved for Future Use
1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.
2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)
3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.
4. CKE1,S1 Pin is used for double side Registered DIMM.
Pin Description
Pin Name
CK0
Description
Pin Name
Description
Clock Inputs, positive line
Clock inputs, negative line
Clock Enables
ODT0~ODT1
DQ0~DQ63
CB0~CB7
On die termination
Data Input/Output
Data check bits Input/Output
Data strobes
CK0
CKE0, CKE1
RAS
Row Address Strobe
Column Address Strobe
Write Enable
DQS0~DQS8
DQS0~DQS8
CAS
Data strobes, negative line
WE
DM(0~8), DQS(9~17) Data Masks / Data strobes (Read)
S0, S1
Chip Selects
DQS9~DQS17
Data strobes (Read), negative line
Reserved for Future Use
No Connect
A0~A9, A11~A13 Address Inputs
RFU
NC
A10/AP
Address Input/Autoprecharge
Memory bus test tool
(Not Connect and Not Useable on DIMMs)
BA0~BA2
DDR2 SDRAM Bank Address
TEST
V
SCL
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
Core Power
I/O Power
DD
V
SDA
DDQ
V
SA0~SA2
Par_In
Err_Out
RESET
SPD address
Ground
SS
V
Parity bit for the Address and Control bus
Parity error found in the Address and Control bus
Register and PLL control pin
Input/Output Reference
SPD Power
REF
V
DDSPD
* The VDD and VDDQ pins are tied to the single power-plane on PCB.
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Input/Output Function Description
Symbol
CK0
Type
Input
Input
Description
Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.
CK0
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low
initiates the Power Down mode, or the Self Refresh mode.
Input
CKE0~CKE1
Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-
abled, new commands are ignored but previous operations continue.
Input
S0~S1
These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are
high.
Input
Input
ODT0~ODT1
I/O bus impedance control signals.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the
SDRAM.
RAS, CAS, WE
V
Supply
Reference voltage for SSTL_18 inputs
REF
V
Supply
Input
Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity
Selects which SDRAM bank of eight is activated.
DDQ
BA0~BA2
During a Bank Activate command cycle, Address defines the row address.
During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is
used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected
and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge com-
mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks
will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define
which bank to precharge.
A0~A9,A10/AP
A11~A13
Input
DQ0~63,
In/Out
Input
Data and Check Bit Input/Output pins
CB0~CB7
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once
the write command is registered into the SDRAM.
DM0~DM8
V
, V
SS
Supply
In/Out
In/Out
Power and ground for the DDR SDRAM input buffers and core logic
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
DD
DQS0~DQS17
DQS0~DQS17
SA0~SA2
These signals are tied at the system planar to either V or V
to configure the serial SPD EEPROM address range.
DDSPD
Input
SS
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA
bus line to V to act as a pullup.
SDA
SCL
In/Out
DDSPD
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time
to V to act as a pullup.
Input
DDSPD
Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6
Volt operation).
V
Supply
DDSPD
The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs
will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-
nized with the input clock )
RESET
Input
Par_In
Err_Out
TEST
Input
Input
Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even)
Parity error found in the Address and Control bus
In/Out
Used by memory bus analysis tools (unused on memory DIMMs)
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Functional Block Diagram
1GB, 128Mx72 Module (M393T2863AZ3/M393T2863AZA)
(populated as 1 rank of x8 DDR2 SDRAMs)
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
NC/DQS9
DM4/DQS13
NC/DQS13
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
DQS1
DQS5
DQS1
DQS5
DM1/DQS10
NC/DQS10
DM5/DQS14
NC/DQS14
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
V
V
Serial PD
D0 - D8
D0 - D8
D0 - D8
DDSPD
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 0
/V
DD DDQ
DQ9
I/O 1
I/O 1
D1
D5
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
VREF
V
SS
DQS2
DQS6
DQS2
DQS6
Serial PD
DM2/DQS11
NC/DQS11
DM6/DQS15
NC/DQS15
SCL
SDA
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
WP A0 A1 A2
SA0 SA1 SA2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D6
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
NC/DQS12
DM7/DQS16
NC/DQS16
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D7
Notes :
DQS8
DQS8
1. DQ-to-I/O wiring may be changed within a byte.
DM8/DQS17
NC/DQS17
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. Unless otherwise noted, resister values are 22 Ohms
DM/ NU/ CS DQS DQS
RDQS RDQS
Signals for Address and Command Parity Function (M393T2863AZA)
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
Register
V
V
C0
C1
SS
SS
PPO
PAR_IN
100K ohms
PAR_IN
QERR
Err_Out
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section: "Register
Options for Unused Address inputs"
1:1
R
E
G
I
S0*
RSO-> CS : DDR2 SDRAMs D0-D8
BA0-BA2
A0-A13
RAS
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D8
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8
RRAS -> RAS : DDR2 SDRAMs D0-D8
RCAS -> CAS : DDR2 SDRAMs D0-D8
RWE -> WE : DDR2 SDRAMs D0-D8
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
P
L
L
CAS
S
T
E
R
WE
PCK7 -> CK : Register
CKE0
ODT0
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
OE
RESET
PCK7 -> CK : Register
RST
RESET
* S0 connects to DCS and VDD connects to CSR on the register.
PCK7
PCK7
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
2GB, 256Mx72 Module (M393T5663AZ3/M393T5663AZA)
(populated as 2 rank of x8 DDR2 SDRAMs)
RS1
RS0
DQS0
DQS4
DQS0
DQS4
DM0/DQS9
NC/DQS9
DM4/DQS13
NC/DQS13
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
I/O 0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
D0
D9
D4
D13
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS1
DQS5
DQS1
DQS5
DM1/DQS10
NC/DQS10
DM5/DQS14
NC/DQS14
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 0
I/O 0
I/O 0
DQ9
I/O 1
I/O 1
I/O 1
I/O 1
D1
D10
D5
D14
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DQS6
DQS2
DQS6
DM2/DQS11
NC/DQS11
DM6/DQS15
NC/DQS15
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
D11
D6
D15
DQS3
DQS7
DQS3
DQS7
DM3/DQS12
NC/DQS12
DM7/DQS16
NC/DQS16
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 0
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
D12
D7
D16
Serial PD
DQS8
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DDSPD
DQS8
SCL
SDA
DM8/DQS17
NC/DQS17
/V
DD DDQ
WP A0 A1 A2
SA0 SA1 SA2
DM/ NU/ CS DQS DQS
RDQS RDQS
DM/ NU/ CS DQS DQS
RDQS RDQS
VREF
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D8
D17
V
SS
Notes :
1. DQ-to-I/O wiring may be changed per nibble.
2. Unless otherwise noted, resister values are 22 Ohms
3. RS0 and RS1 alternate between the back and front sides of the DIMM
S0*
RSO-> CS : DDR2 SDRAMs D0-D8
S1*
RS1-> CS : DDR2 SDRAMs D9-D17
Signals for Address and Command Parity Function (M393T5663AZA)
1:2
R
E
G
I
BA0-BA2
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
RBA0-RBA2 -> BA0-BA2: DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
RCKE0 -> CKE : DDR2 SDRAMs D0-D8
RCKE1 -> CKE : DDR2 SDRAMs D9-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D8
RODT1 -> ODT1 : DDR2 SDRAMs D9-D17
Register A
Register B
V
C0
C1
V
V
C0
C1
SS
DD
DD
DD
V
PPO
PPO
PAR_IN
100K ohms
PAR_IN
PAR_IN
QERR
Err_Out
S
T
QERR
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section: "Register
Options for Unused Address inputs"
E
R
RST
RESET**
PCK7**
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17
PCK7**
P
L
* S0 connects to DCS and S0 connects to CSR on a Register,
S1 connects to DCS and S0 connects to CSR on another Register.
** RESET, PCK7 and PCK7 connects to both Registers.
Other signals connect to one of two Registers.
CK0
L
OE
PCK7 -> CK : Register
RESET
PCK7 -> CK : Register
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
2GB, 256Mx72 Module (M393T5660AZ3/M393T5660AZA)
(populated as 1 rank of x4 DDR2 SDRAMs)
VSS
RS0
DQS0
DQS0
DM0/DQS9
NC/DQS9
DM
CS DQS DQS
DM
CS DQS DQS
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 0
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D9
DQS1
DM1/DQS10
DQS1
NC/DQS10
DM
CS DQS DQS
DM
CS DQS DQS
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
D1
D10
DQ10
DQ11
DQS2
DM2/DQS11
DQS2
NC/DQS11
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
D2
D11
DQS3
DM3/DQS12
DQS3
NC/DQS12
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D12
DQS4
DM4/DQS13
DQS4
NC/DQS13
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
D4
D13
DQS5
DM5/DQS14
DQS5
NC/DQS14
DM
CS DQS DQS
DM
CS DQS DQS
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D14
Serial PD
SCL
SDA
DQS6
DM6/DQS15
WP A0 A1 A2
SA0 SA1 SA2
DQS6
NC/DQS15
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
D6
D15
DQS7
DM7DQS16
DQS7
NC/DQS16
V
V
Serial PD
D0 - D17
D0 - D17
D0 - D17
DDSPD
DM
CS DQS DQS
DM
CS DQS DQS
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
/V
D7
D16
DD DDQ
VREF
DQS8
DM8/DQS17
DQS8
NC/DQS17
V
SS
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D17
Signals for Address and Command Parity Function (M393T5660AZA)
Register A
Register B
V
C0
C1
V
V
C0
C1
SS
DD
DD
DD
V
PPO
PPO
PAR_IN
PAR_IN
PAR_IN
QERR
Err_Out
QERR
100K ohms
1:2
R
E
G
I
The resistors on Par_In, A13, A14, A15, BA2 and the
signal line of Err_Out refer to the section: "Register
Options for Unused Address inputs"
S0*
RSO-> CS : DDR2 SDRAMs D0-D17
BA0-BA2
A0-A13
RAS
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D17
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17
RRAS -> RAS : DDR2 SDRAMs D0-D17
RCAS -> CAS : DDR2 SDRAMs D0-D17
RWE -> WE : DDR2 SDRAMs D0-D17
CAS
S
T
E
R
WE
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8
CKE0
ODT0
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
P
L
L
RST
RESET**
PCK7 -> CK : Register
OE
PCK7**
RESET
PCK7 -> CK : Register
PCK7**
Notes :
1. DQ-to-I/O wiring may be changed per nibble.
* S0 connects to DCS of Register1, CSR of Register2. CSR of reg-
ister 1 and DCS of register 2 connects to VDD.
2. Unless otherwise noted, resister values are 22 Ohms
** RESET, PCK7 and PCK7 connects to both Registers. Other sig-
nals connect to one of two Registers.
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
4GB, 512Mx72 Module (M393T5168AZ0/M393T5168AZA)
(populated as 2 rank of x4 DDR2 SDRAMs)
VSS
RS1
RS0
Serial PD
SCL
SDA
DQS0
DQS0
DM0/DQS9
NC/DQS9
WP A0 A1 A2
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
SA0 SA1 SA2
DQ0
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 0
I/O 0
DQ1
DQ2
DQ3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
D0
D18
D9
D27
V
V
Serial PD
D0 - D35
D0 - D35
D0 - D35
DQS1
DM1/DQS10
DDSPD
DQS1
NC/DQS10
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
/V
DM
CS DQS DQS
DD DDQ
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
I/O 1
I/O 2
I/O 3
D1
D19
D10
D28
VREF
DQ10
DQ11
V
SS
DQS2
DM2/DQS11
DQS2
NC/DQS11
DM
CS DQS DQS
DM/ CS DQS DQS
I/O 0
DM
CS DQS DQS
DM
CS DQS DQS
DQ16
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
I/O 1
I/O 2
I/O 3
D2
D20
D11
D29
Signals for Address and Command
Parity Function (M393T5168AZA)
DQS3
DM3/DQS12
DQS3
NC/DQS12
Register A1
V
V
C0
C1
SS
DD
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
D3
D21
D12
D30
PPO
PAR_IN
QERR
DQS4
DM4/DQS13
DQS4
NC/DQS13
Register B1
PPO
V
V
C0
C1
PAR_IN
DD
DD
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ32
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
PAR_IN
DQ33
DQ34
DQ35
D4
D22
D13
D31
Err_Out
QERR
DQS5
DM5/DQS14
100K ohms
DQS5
NC/DQS14
Register A2
V
C0
C1
SS
DD
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
V
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
PPO
PAR_IN
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
D5
D23
D14
D32
QERR
DQS6
DM6/DQS15
Register B2
DQS6
NC/DQS15
V
V
C0
C1
DD
DD
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ48
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
PPO
PAR_IN
DQ49
DQ50
DQ51
D6
D24
D15
D33
QERR
DQS7
DM7DQS16
Register A1 and A2 share the a part of Add/
Cmd input signal set.
DQS7
NC/DQS16
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
Register B1 and B2 share the rest part of Add/
Cmd input signal set.
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
D7
D25
D16
D34
DQS8
DM8/DQS17
The resistors on Par_In, A13, A14, A15, BA2
and the signal line of Err_Out refer to the sec-
tion: "Register Options for Unused Address
inputs"
DQS8
NC/DQS17
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
DM
CS DQS DQS
CB0
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
D8
D26
D17
D35
S0*
S1*
RSO-> CS : DDR2 SDRAMs D0-D17
RS1-> CS : DDR2 SDRAMs D18-D35
1:2
BA0-BA2
A0-A13
RAS
RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D35
RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35
RRAS -> RAS : DDR2 SDRAMs D0-D35
RCAS -> CAS : DDR2 SDRAMs D0-D35
RWE -> WE : DDR2 SDRAMs D0-D35
R
E
G
I
CK0
CK0
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35
CAS
WE
CKE0
CKE1
ODT0
ODT1
P
L
L
S
T
E
R
RCKE0 -> CKE : DDR2 SDRAMs D0-D17
RCKE1 -> CKE : DDR2 SDRAMs D18-D35
PCK7 -> CK : Register
OE
RESET
RODT0 -> ODT0 : DDR2 SDRAMs D0-D17
RODT1 -> ODT1 : DDR2 SDRAMs D18-D35
PCK7 -> CK : Register
RST
RESET**
PCK7**
PCK7**
* S0 connects to DCS and S0 connects to CSR on a Register,
S1 connects to DCS and S0 connects to CSR on another Register.
** RESET, PCK7 and PCK7 connects to both Registers.
Other signals connect to one of two Registers.
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
V
Notes
Voltage on V pin relative to V
V
- 1.0 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
- 0.5 V ~ 2.3 V
-55 to +100
1
1
DD
SS
DD
Voltage on V
Voltage on V
pin relative to V
V
V
DDQ
DDL
SS
SS
DDQ
pin relative to V
V
V
1
DDL
Voltage on any pin relative to V
Storage Temperature
V
V
V
1
SS
IN, OUT
T
°C
1, 2
STG
Note :
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2
standard.
AC & DC Operating Conditions
Recommended DC Operating Conditions (SSTL - 1.8)
Rating
Symbol
Parameter
Units
Notes
Min.
1.7
Typ.
1.8
Max.
1.9
V
Supply Voltage
V
V
DD
V
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
1.7
1.8
1.9
4
4
DDL
V
1.7
1.8
1.9
V
DDQ
V
0.49*V
0.50*V
0.51*V
DDQ
mV
V
1,2
3
REF
DDQ
DDQ
V
V
-0.04
V
V
+0.04
TT
REF
REF
REF
Note : There is no specific device V supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
must be less than or equal
DD
DDQ
to V
.
DD
1. The value of V
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
is expected to be about 0.5
REF
REF
x V
of the transmitting device and V
is expected to track variations in V
.
DDQ
DDQ
REF
2. Peak to peak AC noise on V
may not exceed +/-2% V
(DC).
REF
REF
3. V of transmitting device must track V
of receiving device.
REF
TT
4. AC parameters are measured with V , V
and V
tied together.
DDL
DD
DDQ
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Operating Temperature Condition
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 95
°C
1, 2, 3
Note :
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to
JESD51.2 standard.
2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self
refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.
Input DC Logic Level
Symbol
(DC)
Parameter
Min.
+ 0.125
Max.
V + 0.3
DDQ
Units
Notes
V
DC input logic high
V
V
IH
REF
V (DC)
DC input logic low
- 0.3
V
- 0.125
REF
V
IL
Input AC Logic Level
DDR2-400, DDR2-533
Min. Max.
+ 0.250
DDR2-667
Symbol
Parameter
Units
Min.
Max.
V
(AC)
(AC)
AC input logic high
AC input logic low
V
-
V + 0.200
REF
-
V
V
IH
REF
V
-
V
- 0.250
-
V
- 0.200
REF
IL
REF
AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
V
Input reference voltage
0.5 * V
V
1
REF
DDQ
V
Input signal maximum peak to peak swing
Input signal minimum slew rate
1.0
V
1
SWING(MAX)
SLEW
1.0
V/ns
2, 3
Notes:
1. Input waveform timing is referenced to the input signal crossing through the V
(AC) level applied to the device under test.
IH/IL
2. The input signal minimum slew rate is to be maintained over the range from V
max for falling edges as shown in the below figure.
to V (AC) min for rising edges and the range from V
to V (AC)
REF IL
REF
IH
3. AC timings are referenced with input waveforms switching from V (AC) to V (AC) on the positive transitions and V (AC) to V (AC) on the negative
IL
IH
IH
IL
transitions.
V
V
V
V
V
V
V
DDQ
(AC) min
IH
IH
(DC) min
V
SWING(MAX)
REF
(DC) max
IL
IL
(AC) max
SS
delta TF
V
delta TR
Rising Slew =
- V (AC) max
IL
V
(AC) min - V
delta TR
REF
IH
REF
Falling Slew =
delta TF
< AC Input Test Signal Waveform >
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
IDD Specification Parameters Definition
(IDD values are for full operating range of Voltage and Temperature)
Symbol Proposed Conditions
Units
Note
Operating one bank active-precharge current;
CK = CK(IDD), RC = RC(IDD), RAS = RASmin(IDD); CKE is HIGH, CS\ is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
t
t
t
t
t
t
IDD0
IDD1
mA
Operating one bank active-read-precharge current;
t
t
t
t
t
t
t
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RC = RC (IDD), RAS = RASmin(IDD), RCD =
mA
t
RCD(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern
is same as IDD4W
Precharge power-down current;
All banks idle; CK = CK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
t
IDD2P
IDD2Q
IDD2N
IDD3P
IDD3N
t
mA
mA
mA
Precharge quiet standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge standby current;
t
t
All banks idle; CK = CK(IDD); CKE is HIGH, CS\ is HIGH; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
Active power-down current;
Fast PDN Exit MRS(12) = 0mA
Slow PDN Exit MRS(12) = 1mA
mA
mA
t
t
All banks open; CK = CK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Active standby current;
t
t
t
t
t
t
mA
mA
All banks open; CK = CK(IDD), RAS = RASmax(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
t
t
t
t
t
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RASmax(IDD), RP =
IDD4W
IDD4R
t
RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
Operating burst read current;
t
t
t
t
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; CK = CK(IDD), RAS = RAS-
mA
mA
t
t
max(IDD), RP = RP(IDD); CKE is HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCH-
ING; Data pattern is same as IDD4W
Burst auto refresh current;
t
t
t
IDD5B
IDD6
CK = CK(IDD); Refresh command at every RFC(IDD) interval; CKE is HIGH, CS\ is HIGH between valid commands;
Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK\ at 0V; CKE ≤ 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
Normal
mA
mA
Low Power
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = RCD(IDD)-1* CK(IDD); CK = CK(IDD), RC =
t
t
t
t
t
IDD7
t
t
t
t
t
t
t
mA
RC(IDD), RRD = RRD(IDD), FAW = FAW(IDD), RCD = 1* CK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the follow-
ing page for detailed timing conditions
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Operating Current Table(1-1)
(TA=0oC, VDD= 1.9V)
M393T2863AZ3/M393T2863AZA : 1GB(128Mx8 *9) Module
Symbol
IDD0
IDD1
E6 (DDR2-667@CL=5)
D5 (DDR2-533@CL=4)
CC (DDR2-400@CL=3)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1,285
1,405
625
895
865
1,175
1,285
585
800
760
765
392
975
1,455
1,385
2,350
135
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
795
402
1,090
1,710
1,570
2,455
135
IDD6*
Normal
IDD7
3,200
2,930
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M393T5663AZ3/M393T5663AZA : 2GB(128Mx8 *18) Module
(TA=0oC, VDD= 1.9V)
Unit Notes
Symbol
IDD0
IDD1
E6 (DDR2-667@CL=5)
D5 (DDR2-533@CL=4)
CC (DDR2-400@CL=3)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1,790
1,920
910
1,470
1,360
1,280
654
1,525
2,245
2,105
2,980
270
1,665
1,815
850
1,310
1,240
1,220
624
1,415
1,955
1,875
2,800
270
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
Normal
IDD7
3,965
3,500
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
M393T5660AZ3/M393T5660AZA : 2GB(256Mx4 *18) Module
(TA=0oC, VDD= 1.9V)
Symbol
IDD0
IDD1
E6 (DDR2-667@CL=5)
D5 (DDR2-533@CL=4)
CC (DDR2-400@CL=3)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2,150
2,370
910
1,470
1,360
1,280
654
1,660
2,830
2,690
4,510
270
2,070
2,310
850
1,310
1,240
1,220
624
1,550
2,360
2,280
4,330
270
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
Normal
IDD7
6,080
5,480
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M393T5168AZ0/M393T5168AZA : 4GB(st.512Mx4 *18) Module
(TA=0oC, VDD= 1.9V)
Unit Notes
Symbol
IDD0
IDD1
E6 (DDR2-667@CL=5)
D5 (DDR2-533@CL=4)
CC (DDR2-400@CL=3)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3,170
3,420
1,480
2,600
2,360
2,240
1,138
2,590
3,920
3,770
5,550
540
3,040
3,370
1,380
2,320
2,210
2,140
1,088
2,330
3,360
3,260
5,230
540
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2Q
IDD2N
IDD3P-F
IDD3P-S
IDD3N
IDD4W
IDD4R
IDD5B
IDD6*
Normal
IDD7
7,610
6,630
* IDD6 = DRAM current + standby current of PLL and Register
** Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
(VDD=1.8V, VDDQ=1.8V, TA=25oC)
Input/Output Capacitance
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Symbol
Units
M393T2863AZ3
M393T2863AZA
M393T5663AZ3
M393T5663AZA
M393T5660AZ3
M393T5660AZA
M393T5168AZ0
M393T5168AZA
Part-Number
Input capacitance, CK and CK
CCK
CI1
-
-
-
-
11
12
12
10
-
-
-
-
11
12
12
10
-
-
-
-
11
12
12
10
-
-
-
-
11
12
12
10
Input capacitance, CKE and CS
pF
Input capacitance, Addr,RAS,CAS,WE
Input/output capacitance, DQ, DM, DQS, DQS
CI2
CIO
* DM is internally loaded to match DQ and DQS identically.
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Electrical Characteristics & AC Timing for DDR2-667/533/400
(0 °C < T
< 95 °C; V
= 1.8V + 0.1V; V = 1.8V + 0.1V)
DDQ DD
OPER
Refresh Parameters by Device Density
Parameter
Symbol
256Mb
75
512Mb
105
1Gb
127.5
7.8
2Gb
195
7.8
4Gb
327.5
7.8
Units
ns
Refresh to active/Refresh command time
tRFC
tREFI
0 °C ≤ T
≤ 85°C
≤ 95°C
7.8
7.8
µs
CASE
Average periodic refresh interval
85 °C < T
3.9
3.9
3.9
3.9
3.9
µs
CASE
Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin
Speed
Bin(CL - tRCD - tRP)
Parameter
tCK, CL=3
tCK, CL=4
tCK, CL=5
tRCD
DDR2-667(E6)
5 - 5 - 5
DDR2-533(D5)
4 - 4 - 4
DDR2-400(CC)
3 - 3 - 3
Units
min
5
max
min
max
min
max
8
8
8
-
5
3.75
-
8
5
5
8
ns
ns
ns
ns
ns
ns
ns
3.75
3
8
8
-
-
-
15
15
54
39
15
15
55
40
-
15
15
55
40
-
tRP
-
-
-
-
-
tRC
-
tRAS
70000
70000
70000
Timing Parameters by Speed Grade
(Refer to notes for informations related to this table at the bottom)
DDR2-667
DDR2-533
DDR2-400
Parameter
Symbol
Units Notes
min
max
+450
+400
0.55
0.55
min
-500
-450
0.45
0.45
max
+500
+450
0.55
0.55
min
-600
-500
0.45
0.45
max
+600
+500
0.55
0.55
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
tAC
-450
-400
0.45
0.45
ps
ps
tDQSCK
tCH
tCK
tCK
CK low-level width
tCL
min(tCL,
tCH)
min(tCL,
tCH)
min(tCL,
tCH)
CK half period
tHP
x
x
x
ps
Clock cycle time, CL=x
tCK
tDH
tDS
3000
175
100
0.6
8000
3750
225
100
0.6
8000
5000
275
8000
ps
ps
DQ and DM input hold time
DQ and DM input setup time
x
x
x
x
x
x
x
150
x
ps
Control & Address input pulse width for each input tIPW
x
x
0.6
x
tCK
tCK
ps
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
tDIPW
tHZ
0.35
x
0.35
x
0.35
x
x
tAC max
tAC max
tAC max
tAC max
tLZ(DQS) tAC min tAC max
tAC min tAC max
tAC min
ps
tLZ(DQ) 2*tAC min tAC max 2* tACmin tAC max 2* tACmin tAC max
ps
DQS-DQ skew for DQS and associated DQ signals tDQSQ
x
x
240
340
x
x
x
300
400
x
x
x
350
450
x
ps
DQ hold skew factor
tQHS
tQH
ps
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
tHP - tQHS
-0.25
tHP - tQHS
-0.25
tHP - tQHS
-0.25
ps
tDQSS
0.25
0.25
0.25
tCK
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
DDR2-667
DDR2-533
DDR2-400
Parameter
Symbol
Units Notes
min
max
x
min
max
x
min
0.35
0.35
0.2
max
x
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
tDQSH
tDQSL
tDSS
0.35
0.35
0.2
0.2
2
0.35
0.35
0.2
0.2
2
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
x
x
x
x
x
x
tDSH
tMRD
tWPST
tWPRE
tIH
x
x
0.2
x
x
x
2
x
0.4
0.35
275
200
0.9
0.4
0.6
x
0.4
0.35
375
250
0.9
0.4
0.6
x
0.4
0.6
x
Write preamble
0.35
475
350
0.9
Address and control input hold time
Address and control input setup time
Read preamble
x
x
x
tIS
x
x
x
ps
tRPRE
tRPST
1.1
0.6
1.1
0.6
1.1
0.6
tCK
tCK
Read postamble
0.4
Active to active command period for 1KB page size
products
tRRD
tRRD
7.5
10
x
x
7.5
10
x
x
7.5
10
x
x
ns
ns
Active to active command period for 2KB page size
products
Four Activate Window for 1KB page size products tFAW
Four Activate Window for 2KB page size products tFAW
37.5
50
37.5
37.5
ns
ns
50
2
50
CAS to CAS command delay
tCCD
tWR
2
2
15
tCK
ns
Write recovery time
15
x
x
x
15
x
x
x
x
x
x
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
tDAL
WR+tRP
7.5
tWR+tRP
7.5
tWR+tRP
10
tCK
ns
tWTR
tRTP
7.5
7.5
7.5
ns
tXSNR
tXSRD
tRFC + 10
200
tRFC + 10
200
tRFC + 10
200
ns
tCK
Exit precharge power down to any non-read com-
mand
tXP
2
2
x
x
2
2
x
x
2
2
x
x
tCK
tCK
tCK
Exit active power down to read command
tXARD
tXARDS
Exit active power down to read command (Slow
exit, Lower power)
7 - AL
6 - AL
6 - AL
CKE minimum pulse width(high and low pulse
width)
tCKE
3
2
3
2
3
2
tCK
tCK
ns
ODT turn-on delay
tAOND
tAON
2
2
2
tAC(max)
+0.7
tAC(max)
+1
tAC(max)+
1
ODT turn-on
tAC(min)
tAC(min)
tAC(min)
tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC tAC(min)+ 2tCK+tAC
ODT turn-on(Power-Down mode)
ODT turn-off delay
tAONPD
tAOFD
tAOF
ns
tCK
ns
2
(max)+1
2.5
2
(max)+1
2.5
2
(max)+1
2.5
2.5
2.5
2.5
tAC(max)
+ 0.6
tAC(max)
+ 0.6
tAC(max)+
0.6
ODT turn-off
tAC(min)
tAC(min)
tAC(min)
2.5tCK+
tAC(max)
+1
2.5tCK+
tAC(max)+
1
tAC(min)+ 2.5tCK+tA tAC(min)+
tAC(min)+
2
ODT turn-off (Power-Down mode)
tAOFPD
ns
2
C(max)+1
2
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
tANPD
tAXPD
tOIT
3
8
0
3
8
0
3
8
0
tCK
tCK
ns
12
12
12
Minimum time clocks remains ON after CKE asyn-
chronously drops LOW
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
tDelay
ns
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
Physical Dimensions
128Mbx8 based 128Mx72 Module(1 Rank) (M393T2863AZ3/M393T2863AZA)
133.35
131.35
128.95
Units : Millimeters
2.7 mm
N/A
(for x64)
ECC
(for x72)
30.00
PLL
1.0 max
(2)
2.50
1.27 ± 0.10
B
A
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
Detail B
1.50±0.10
Detail A
The used device is 128M x8 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G084QA
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
128Mbx8/256Mbx4 based 256Mx72 Module(2/1 Ranks)
(M393T5663AZ3 / M393T5663AZA / M393T5660AZ3 / M393T5660AZA)
Units : Millimeters
4.0 mm
133.35
131.35
128.95
N/A
(for x64)
ECC
(for x72)
30.00
PLL
1.0 max
(2)
2.50
1.27 ± 0.10
B
A
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
Detail B
1.50±0.10
Detail A
The used device is 128M x8 / 256M x4 DDR2 SDRAM, FBGA.
DDR2 SDRAM Part NO : K4T1G084QA / K4T1G044QA
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
st.512Mbx4 based 512Mx72 Module(2 Ranks) (M393T5168AZ0/M393T5168AZA)
Units : Millimeters
133.35
131.35
128.95
6.75 mm
30.00
PLL
4.05 max
(2)
2.50
1.27 ± 0.10
B
A
63.00
55.00
3.00
5.00
4.00
0.80±0.05
0.20
4.00
3.80
4.00
2.50
1.00
Detail B
1.50±0.10
Detail A
The used device is st.512M x4 DDR2 SDRAM.
DDR2 SDRAM Part NO : K4T2G064QA
Rev. 1.1 Aug. 2005
1GB, 2GB, 4GB Registered DIMMs
DDR2 SDRAM
240 Pin DDR2 Registered DIMM Clock Topology
0ns (nominal)
PLL
DDR2 SDRAM
120 ohms
OUT1
CK0
120 ohms
IN
DDR2 SDRAM
Reg.A
CK0
120 ohms
OUTN
120 ohms
C
C
Feedback In
Feedback Out
Reg.B
Note :
1. The clock delay from the input of the PLL clock to the input of any DDR2 SDRAM or register will be set to 0ns (nominal).
2. Input, output, and feedback clock lines are terminated from line to line as shown, and not from line to ground.
3. Only one PLL output is shown per output type. Any additional PLL outputs will be wired in a similar manner.
4. Termination resistors for the PLL feedback path clocks are located as close to the input pin of the PLL as possible.
Rev. 1.1 Aug. 2005
相关型号：
M393T5660FBA-CF7
DDR DRAM Module, 256MX72, 0.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, DIMM-240
SAMSUNG
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