M463L0914BT0-CA0 [SAMSUNG]
DDR DRAM Module, 8MX64, 0.8ns, CMOS, DIMM-172;
| 型号： | M463L0914BT0-CA0 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 8MX64, 0.8ns, CMOS, DIMM-172 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总14页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
172pin DDR Micro DIMM
M463L0914BT0
64MB DDR SDRAM MODULE
(8Mx64 based on 8Mx16 DDR SDRAM)
172pin Micro DIMM
64-bit Non-ECC/Parity
Revision 0.3
July. 2001
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
Revision History
Revision 0.0 (Apr. 2001)
1. First release
Revision 0.1 (May. 2001)
Changed the Package Dimension.
Revision 0.2 (June. 2001)
1. Changed module current speificaton
2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).
3. Changed AC parameter table.
Revision 0.3 (July. 2001)
1. Changed typo size on module PCB in package dimesions.
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
M463L0914BT0 172pin DDR Micro DIMM
8Mx64 172pin DDR Micro DIMM based on 8Mx16
FEATURE
GENERAL DESCRIPTION
• Performance range
The Samsung M463L0914BT0 is 8M bit x 64 Double Data
Rate SDRAM high density memory modules based on first gen
of 128Mb DDR SDRAM respectively.
Part No.
Max Freq.
Interface
M463L0914BT0-C(L)A2 133MHz(7.5ns@CL=2)
M463L0914BT0-C(L)B0 133MHz(7.5ns@CL=2.5)
SSTL_2
The Samsung M463L0914BT0 consists of four CMOS 8M x 16
bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 172pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M463L0914BT0 is Dual In-line Memory Modules and
intended for mounting into 172pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
100MHz(10ns@CL=2)
M463L0914BT0-C(L)A0
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
• Serial presence detect with EEPROM
• PCB:Height1200(mil),double sided component
PIN DESCRIPTION
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin
Front Pin
Front
Pin Back
Pin
Back
Pin
Back
Pin Name
A0 ~ A11
Function
1
3
5
7
V
V
DQ0
DQ1
V
DQS0
DQ2
V
DQ3
DQ8
V
DQ9
DQS1
V
DQ10
DQ11
V
CK0
CK0
V
DQ16
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQ25 117
V
2
V
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
DQ29
DM3
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
V
Address input (Multiplexed)
Bank Select Address
Data input/output
REF
DD
REF
DD
DQS3
119
121
123
4
DQ41
DQS5
V
DQ45
DM5
SS
SS
BA0 ~ BA1
V
V
6
8
SS
SS
DQ4
DQ5
V
V
DQ26
DQ30
DQ31
DQ0 ~ DQ63
DQS0 ~ DQS7
SS
SS
9
DQ27 125
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
DQ42
DQ43
V
DM0
DQ6
V
DQ7
DQ46
DQ47
DD
DD
Data Strobe input/output
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
V
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
V
DD
DD
V
V
CKE1
A12
A9
A7
V
CKE0
A11
A8
CK0~ CK1,
CK0~ CK1
DD
DD
Clock input
V
CK1
CK1
SS
DD
SS
V
V
SS
CKE0
CS0
Clock enable input
Chip select input
A6
V
DQ12
SS
SS
V
V
DQ52
DQ53
SS
SS
DD
DD
DQ48
DQ49
A5
A3
A1
A10/AP
V
BA0
WE
S0
A13
V
A4
A2
A0
DQ13
DM1
V
DQ14
DQ15
RAS
Row address strobe
Column address strobe
Write enable
V
V
DD
DD
DM6
DQ54
SS
SS
DQS6
DQ50
CAS
BA1
V
WE
V
DD
DD
V
SS
SS
V
RAS
CAS
S1
DD
DD
DQ55
DQ60
DQ51
DQ56
DM0 ~ DM7
VDD
Data - in mask
94
96
98
V
DD
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
V
V
V
V
DQ20
DQ21
DD
DD
SS
RFU
SS
DQ61
DM7
DQ57
DQS7
SS
VDDQ
VSS
V
100
102
104
106
108
110
112
114
116
SS
SS
43 DQ17 101
DQ32
DQ36
DQ37
V
V
SS
SS
V
45
47 DQS2 105
103 DQ33 161
DD
DQ62
DQ63
DQ58
DQ59
V
DD
VREF
VDDSPD
Power supply for reference
V
V
163
165
167
169
171
DD
DD
DM2
DQ22
V
DQ23
DQ28
DQ18
Serial EEPROM Power
Supply (2.3V to 3.6V)
49
51
53
55
57
107
109
111
113
115
DQS4
DQ34
V
DM4
DQ38
V
V
DD
DD
V
SS
SDA
SCL
SA0
SA1
SA2
SS
DQ19
DQ24
V
SS
SS
SDA
Serial data I/O
V
SPD
DQ35
DQ40
DQ39
DQ44
DD
V
DD
V
SCL
Serial clock
DD
SA0 ~ 2
VDDID
NC
Address in EEPROM
VDD identification flag
No connection
*
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
FUNCTIONAL BLOCK DIAGRAM
N.C.
CKE1
N.C.
S1
CKE0
S0
X pF
CKE
CKE
CS
CS
Load matching
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS4
DM4
Capacitors on
DQS0
DM0
LDQS
LDM
Raw card A Raw card B
DQ32
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
A0-AN
RAS
CAS
WE
CKE0
S0
10 pF
10 pF
UDQS
UDM
DQS5
UDQS
UDM
I/O 8
DQS1
DM1
DM5
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 8
DQ9
I/O 9
I/O 9
D0
D2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DRAM
MicroDIMM
Connector
DRAM
Cap
CKE
CS
CKE
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
CK
CK
DQS6
DM6
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Cap
Two Loads (Raw card A)
UDQS
UDM
DQS3
DM3
UDQS
UDM
DQS7
DM7
CK
CK
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 8
DQ56
I/O 8
Raw card A: 0.5 pF
Raw card B: 1.0 pF
I/O 9
D1
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 9
D3
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
BA0-BA1: DDR SDRAMs D0 - D3
A0-A11: DDR SDRAMs D0 - D3
RAS: SDRAMs D0 - D3
BA0 - BA1
A0 - A11
RAS
Clock Wiring
SDRAMs
Clock
Input
CAS
CAS: SDRAMs D0 - D3
CK0/CK0
CK1/CK1
2 SDRAMs + 2Caps
2 SDRAMs + 2Caps
CKE0
WE
CKE: SDRAMs D0 - D3
Notes:
WE: SDRAMs D0 - D3
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ¹ VDDQ.
V
DDSPD
SPD
V
/V
DD DDQ
D0 - D3
D0 - D3
Serial PD
SCL
WP
VREF
SDA
D0 - D3
D0 - D3
A0
A1
A2
V
SS
V
DDID
SA0 SA1
Strap: see Note 4
SA2
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
4
Unit
V
V
V
VDDQ
TSTG
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V)
I/O Supply voltage
Symbol
VDD
Min
2.3
Max
2.7
Unit
Note
VDDQ
VREF
2.3
2.7
V
V
I/O Reference voltage
VDDQ/2-50mV VDDQ/2+50mV
1
2
4
4
I/O Termination voltage(system)
Input logic high voltage
V
VREF-0.04
VREF+0.04
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.35
V
TT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
II
VREF+0.15
-0.3
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
-0.3
V
0.3
V
3
5
1.15
-2
V
2
uA
uA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver)
IOH
IOL
IOH
IOL
-16.8
16.8
-9
mA
mA
mA
mA
;V
= V + 0.84V
OUT
TT
Output High Current(Normal strengh driver)
;V = V - 0.84V
OUT
TT
Output High Current(Half strengh driver)
;V = V + 0.45V
OUT
TT
Output High Current(Half strengh driver)
;V = V - 0.45V
9
OUT
TT
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.
2.V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to
TT
TT
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
DDR SDRAM SPEC Items and Test Conditions
Recommended operating conditions Unless Otherwise Noted, TA=0 to 70°C)
Conditions
Symbol
IDD0
Typical
Worst
Operating current - One bank Active-Precharge;
-
-
tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
IDD1
-
-
-
-
Percharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD2P
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
IDD2F
IDD2Q
-
-
-
-
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD3P
IDD3N
-
-
-
-
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once
per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst;
One bank active; address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =
133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A
IDD4R
IDD4W
-
-
-
-
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,
CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh
IDD5
-
-
-
-
-
-
Self refresh current; CKE =< 0.2V; External clock should be on;
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B
IDD6
Orerating current - Four bank operation ; Four bank interleaving with BL=4
IDD7A
-Refer to the following page for detailed test condition
Typical case: VDD = 2.5V, T = 25C’
Worst case : VDD = 2.7V, T = 10C’
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
DDR SDRAM module I spec table
DD
A2(DDR266@CL=2)
Symbol
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
Unit
Notes
typical
400
500
100
200
160
140
220
720
760
760
8
worst
460
580
120
240
180
160
260
840
900
860
8
typical
400
500
100
200
160
140
220
720
760
760
8
worst
460
580
120
240
180
160
260
840
900
860
8
typical
360
460
80
worst
400
540
100
200
160
140
220
740
800
800
8
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
180
140
120
180
600
640
720
8
Normal
Low power
IDD7A
IDD6
4
4
4
4
4
4
Optional
1380
1600
1380
1600
1120
1320
* Module I
was calculated on the basis of component I
DD
and can be differently measured according to DQ loading cap.
DD
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
IDD7A : Operating current: Four bank operation
1. Typical Case : Vdd = 2.5V, T=25’C
2. Worst Case : Vdd = 2.7V, T= 10’C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
AC Operating Conditions
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC) VREF + 0.31
VIL(AC)
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
VID(AC) 0.7
Input Crossing Point Voltage, CK and CK inputs
VIX(AC) 0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
Input Levels(VIH/VIL)
1.5
VREF+0.31/VREF-0.31
VREF
V
V
V
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Vtt
See Load Circuit
Vtt=0.5*VDDQ
RT=50W
Output
Z0=50W
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS, WE )
CIN1
29
34
34
30
32
pF
pF
pF
pF
Input capacitance(CKE0)
Input capacitance( CS0 )
CIN2
CIN3
CIN4
29
26
30
Input capacitance( CLK0, CLK1)
Data & DQS input/output capacitance(DQ0~DQ63)
Input capacitance(DM0~DM8)
COUT
CIN5
8
8
9
9
pF
pF
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)
-TCA2(DDR266A) -TCB0(DDR266B) -TCA0 (DDR200)
Parameter
Symbol
Unit
Note
Min
65
Max
Min
65
Max
Min
70
80
48
20
20
15
2
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
Refresh row cycle time
Row active time
75
75
45
120K
45
120K
120K
ns
RAS to CAS delay
20
20
ns
Row precharge time
20
20
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
15
15
ns
2
2
tCK
tCK
tCK
ns
Last data in to Read command
Col. address to Col. address delay
tCDLR
tCCD
1
1
1
1
1
1
CL=2.0
CL=2.5
7.5
7.5
0.45
0.45
-0.75
-0.75
-
12
12
10
12
12
10
12
5
5
Clock cycle time
tCK
7.5
0.45
0.45
-0.75
-0.75
-
12
ns
Clock high level width
tCH
tCL
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.45
0.45
-0.8
-0.8
-
0.55
0.55
+0.8
+0.8
+0.6
1.1
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
tDQSCK
tAC
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tDSS
ns
5
2
0.9
0.4
0.75
0
0.9
0.4
0.75
0
0.9
0.4
0.75
0
tCK
tCK
tCK
ns
Read Postamble
0.6
0.6
0.6
CK to valid DQS-in
1.25
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.25
0.2
0.2
0.35
0.25
0.2
0.2
0.35
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tDSH
tDQSH
DQS-in low level width
tDQSL
tDSC
tIS
0.35
0.9
0.35
0.9
0.9
0.9
0.35
0.9
DQS-in cycle time
1.1
1.1
1.1
Address and Control Input setup time
Address and Control Input hold time
Data-out high impedence time from CK/CK
0.9
1.1
6
6
tIH
0.9
1.1
ns
tHZ
tACmin- tACmax tACmin tACmax tACmin tACmax
400ps - 400ps - 400ps - 400ps - 400ps - 400ps
ps
ps
Data-out low impedence time from CK/CK
tLZ
tACmin- tACmax tACmin tACmax tACmin tACmax
400ps
- 400ps - 400ps - 400ps - 400ps - 400ps
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
tSL(I)
tSL(IO)
tSL(O)
0.5
0.5
0.5
1.0
0.7
0.5
0.5
1.0
0.7
V/ns
V/ns
V/ns
V/ns
6
7
0.5
1.0
4.5
5
4.5
5
4.5
5
10
10
Output Slew Rate(x16)
tSL
(O)
0.7
Output Slew Rate Matching Ratio(rise to fall)
t
0.67
1.5
0.67
1.5
0.67
1.5
SLMR
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
-TCA2(DDR266A)
-TCB0(DDR266B)
-TCA0 (DDR200)
Parameter
Symbol
Unit Note
Min
15
Max
Min
15
Max
Min
16
Max
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tMRD
tDS
ns
0.5
0.5
1.75
10
0.5
0.5
1.75
10
0.6
0.6
2
ns
ns
7,8,9
7,8,9
tDH
DQ & DM input pulse width
tDIPW
tPDEX
tXSW
tXSA
ns
ns
Power down exit time
10
Exit self refresh to write command
Exit self refresh to bank active command
Exit self refresh to read command
95
116
80
ns
75
75
200
15.6
7.8
ns
4
tXSR
tREF
200
15.6
7.8
200
15.6
7.8
Cycle
us
64Mb, 128Mb
Refresh interval time
256Mb
1
1
us
tHPmin
-tQHS
tHPmin
-tQHS
tHPmin
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
ns
ns
5
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
Data hold skew factor
tQHS
0.75
0.75
0.8
ns
DQS write postamble time
tWPST
0.25
0.25
0.25
tCK
3
Note : 1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DINNs, tCL and tCH are ³ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half
period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
DtIS
(ps)
0
DtIH
(ps)
0
(V/ns)
0.5
0.4
+50
+100
+50
+100
0.3
This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
IS IH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
DtDS
(ps)
0
DtDH
(ps)
0
(V/ns)
0.5
0.4
+75
+150
+75
+150
0.3
This derating table is used to increase t /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
DS DH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
8. I/O Setup/Hold Plateau Derating
I/O Input Level
(mV)
DtDS
(ps)
DtDH
(ps)
± 280
+50
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
DtDS
(ps)
0
DtDH
(ps)
0
(ns/V)
0
±0.25
±0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
Command Truth Table
COMMAND
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
A11
A9 ~ A0
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Column
Address
(A0~A8)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
L
H
L
H
Column
Address
(A0~A8)
Write &
Column Address
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.3 July. 2001
172pin DDR Micro DIMM
M463L0914BT0
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
Front
1.79(45.50)
DDR SDRAMs
DDR SDRAMs
1.18(30.0)
0.59(15.00)
1
171
0.04(1.00)
DDR SDRAMs
DDR SDRAMs
0.06(1.45)
max.
0.015(0.37)
0.01(2.50)
min
0.01(0.25)
max
0.02(0.50)
0.06(1.45)
max.
Tolerances : ±.01(.25) unless otherwise specified
The used device is 8Mx16 SDRAM, TSOP
SDRAM Part No. : K4H281638B-TC/L
Rev. 0.3 July. 2001
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