M464S3254CTS-L1H_技术文档

PC133/PC100 SODIMM

M464S3254CTS

M464S3254CTS SDRAM SODIMM

32Mx64 SDRAM SODIMM based on 16Mx16, 4Banks, 8K Refresh,3.3V Synchronous DRAMs with SPD

GENERAL DESCRIPTION

FEATURE

• Performance range

The Samsung M464S3254CTS is a 32M bit x 64 Synchronous

Dynamic RAM high density memory module. The Samsung

M464S3254CTS consists of eight CMOS 16M x 16 bit with

4banks Synchronous DRAMs in TSOP-II 400mil package and a

2K EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy

substrate. Three 0.1uF decoupling capacitors are mounted on

the printed circuit board in parallel for each SDRAM. The

M464S3254CTS is a Small Outline Dual In-line Memory Module

and is intended for mounting into 144-pin edge connector sock-

ets.

Part No.

Max Freq. (Speed)

133MHz@CL=2

133MHz@CL=3

100MHz @ CL=2

100MHz @ CL=3

M464S3254CTS-L7C/C7C

M464S3254CTS-L7A/C7A

M464S3254CTS-L1H/C1H

M464S3254CTS-L1L/C1L

• Burst mode operation

• Auto & self refresh capability (8192 Cycles/64ms)

• LVTTL compatible inputs and outputs

• Single 3.3V ± 0.3V power supply

Synchronous design allows precise cycle control with the use of

system clock. I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable latencies allows

the same device to be useful for a variety of high bandwidth,

high performance memory system applications.

• MRS cycle with address key programs

Latency (Access from column address)

Burst length (1, 2, 4, 8 & Full page)

Data scramble (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the

system clock

• Serial presence detect with EEPROM

• PCB : Height (1,250mil), double sided component

PIN CONFIGURATIONS (Front side/back side)

PIN NAMES

Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back

Pin Name

A0 ~ A12

Function

Address input (Multiplexed)

Select bank

1

3

VSS

DQ0

DQ1

DQ2

2

4

6

8

VSS

51 DQ14 52 DQ46 95 DQ21 96 DQ53

DQ32 53 DQ15 54 DQ47 97 DQ22 98 DQ54

BA0 ~ BA1

5

DQ33 55

DQ34 57

VSS

NC

56

58

60

VSS

99 DQ23 100 DQ55

DQ0 ~ DQ63 Data input/output

CLK0 ~ CLK1 Clock input

7

NC 101

NC 103

105

VDD

A6

102 VDD

104 A7

9

DQ3 10 DQ35 59

12

CKE0 ~ CKE1 Clock enable input

11

VDD

A8

106 BA0

108 VSS

110 BA1

CS0 ~ CS1

RAS

Chip select input

Row address strobe

Column address strobe

Write enable

13 DQ4 14 DQ36

15 DQ5 16 DQ37

107

VSS

A9

Voltage Key

109

17 DQ6 18 DQ38 61 CLK0 62 CKE0 111 A10/AP 112 A11

19 DQ7 20 DQ39 63 64 VDD 113 114 VDD

21 22 65 RAS 66 CAS 115 DQM2 116 DQM6

23 DQM0 24 DQM4 67 WE 68 CKE1 117 DQM3 118 DQM7

25 DQM1 26 DQM5 69 CS0 70 A12 119 120 VSS

71 CS1 72 *A13 121 DQ24 122 DQ56

CAS

VDD

WE

VSS

DQM0 ~ 7

VDD

DQM

Power supply (3.3V)

Ground

VSS

27

29

31

33

35

VDD

A0

28

30

32

34

36

VDD

A3

SDA

Serial data I/O

Serial clock

73

75

77

79

DU

VSS

NC

74 CLK1 123 DQ25 124 DQ57

SCL

A1

A4

76

78

80

82

VSS 125 DQ26 126 DQ58

NC 127 DQ27 128 DQ59

A2

A5

DU

Don¢t use

VSS

NC

NC 129

VDD

130 VDD

NC

No connection

37 DQ8 38 DQ40 81

VDD

VDD 131 DQ28 132 DQ60

*

These pins are not used in this module.

39 DQ9 40 DQ41 83 DQ16 84 DQ48 133 DQ29 134 DQ61

41 DQ10 42 DQ42 85 DQ17 86 DQ49 135 DQ30 136 DQ62

43 DQ11 44 DQ43 87 DQ18 88 DQ50 137 DQ31 138 DQ63

** These pins should be NC in the system

which does not support SPD.

45

47 DQ12 48 DQ44 91

49 DQ13 50 DQ45 93 DQ20 94 DQ52 143

VDD

46

VDD

89 DQ19 90 DQ51 139

92 VSS 141 **SDA 142 **SCL

144 VDD

VSS

140 VSS

VSS

VDD

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

PIN CONFIGURATION DESCRIPTION

Name

System clock

Input Function

CLK

CS

Active on the positive going edge to sample all inputs.

Disables or enables device operation by masking or enabling all inputs except

CLK, CKE and DQM

Chip select

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

CKE

Clock enable

CKE should be enabled 1CLK+tSS prior to valid command.

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA12, Column address : CA0 ~ CA8

A0 ~ A12

BA0 ~ BA1

RAS

Address

Selects bank to be activated during row address latch time.

Selects bank for read/write during column address latch time.

Bank select address

Row address strobe

Column address strobe

Write enable

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

CAS

Enables write operation and row precharge.

Latches data in starting from CAS, WE active.

WE

Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active. (Byte masking)

DQM0 ~ 7

Data input/output mask

DQ0 ~ 63

VDD/VSS

Data input/output

Data inputs/outputs are multiplexed on the same pins.

Power and ground for the input buffers and the core logic.

Power supply/ground

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

FUNCTIONAL BLOCK DIAGRAM

CS1

CS0

DQM0

DQM4

LDQM CS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ32

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

U0

U4

U2

U6

UDQM

DQM1

DQM5

DQ8

DQ9

DQ8

DQ9

DQ8

DQ9

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

DQ9

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQM6

DQM2

LDQM CS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ0

DQ1

DQ0

DQ1

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

U1

U5

U3

U7

UDQM

DQM3

DQM7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ8

DQ9

DQ8

DQ9

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ8

DQ9

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

SDRAM U0 ~ U7

SDRAM U0 ~ U3

SDRAM U4 ~ U7

A0 ~ A12, BA0 & 1

RAS

CAS

Serial PD

SDA

WP

SCL

·

WE

A0

A1

A2

47KW

CKE0

CKE1

SA0 SA1 SA2

10W

DQn

Every DQ pin of SDRAM

U0/U4

U1/U5

U2/U6

U3/U7

VDD

Vss

CLK0/1

Three 0.1 uF X7R 0603 Capacitors

per each SDRAM

To all SDRAMs

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply relative to Vss

Storage temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

Unit

V

-1.0 ~ 4.6

-55 ~ +150

8

V

°C

W

Power dissipation

PD

Short circuit current

IOS

50

mA

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter

Supply voltage

Symbol

VDD

VIH

Min

3.0

2.0

-0.3

2.4

-

Typ

Max

Unit

V

Note

3.3

3.6

Input high voltage

Input low voltage

3.0

VDDQ+0.3

V

1

VIL

0

-

0.8

-

V

2

Output high voltage

Output low voltage

Input leakage current

VOH

VOL

ILI

V

IOH = -2mA

IOL = 2mA

3

-

0.4

10

V

-10

-

uA

Notes :

1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.

3. Any input 0V £ VIN £ VDDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

Parameter

Symbol

Min

Max

Unit

Input capacitance (A0 ~ A12, BA0 ~ BA1)

Input capacitance (RAS, CAS, WE)

Input capacitance (CKE0 ~ CKE1)

Input capacitance (CLK0 ~ CLK1)

Input capacitance (CS0 ~ CS1)

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

COUT

25

15

10

13

45

25

21

25

12

18

pF

Input capacitance (DQM0 ~ DQM7)

Data input/output capacitance (DQ0 ~ DQ63)

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)

Version

Parameter

Symbol

Test Condition

Unit Note

-7C

-7A

-1H

-1L

Burst length = 1

tRC ³ tRC(min)

IO = 0 mA

Operating current

(One bank active)

ICC1

640

600

560

mA

1

ICC2P

16

CKE £ VIL(max), tCC = 10ns

Precharge standby cur-

rent in power-down mode

ICC2PS

CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns

ICC2N

160

80

Precharge standby cur-

rent in non power-down

mode

mA

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC2NS

ICC3P

48

CKE £ VIL(max), tCC = 10ns

Active standby current in

power-down mode

mA

ICC3PS

CKE & CLK £ VIL(max), tCC = ¥

CKE ³ VIH(min), CS ³ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns

ICC3N

240

200

Active standby current in

non power-down mode

(One bank active)

CKE ³ VIH(min), CLK £ VIL(max), tCC = ¥

Input signals are stable

ICC3NS

IO = 0 mA

Page burst

4banks Activated.

tCCD = 2CLKs

Operating current

(Burst mode)

ICC4

720

640

880

640

880

mA

1

2

Refresh current

ICC5

ICC6

tRC ³ tRC(min)

1,000 920

mA

C

24

12

Self refresh current

CKE £ 0.2V

L

Notes :

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ).

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter

AC input levels (Vih/Vil)

Value

2.4/0.4

1.4

Unit

V

Input timing measurement reference level

Input rise and fall time

V

tr/tf = 1/1

1.4

ns

V

Output timing measurement reference level

Output load condition

See Fig. 2

3.3V

Vtt = 1.4V

1200W

50W

VOH (DC) = 2.4V, IOH = -2mA

VOL (DC) = 0.4V, IOL = 2mA

Z0 = 50W

Output

50pF

870W

(Fig. 1) DC output load circuit

(Fig. 2) AC output load circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter

Symbol

Unit

Note

-7C

15

45

-7A

-1H

20

50

-1L

20

50

Row active to row active delay

RAS to CAS delay

tRRD(min)

tRCD(min)

tRP(min)

15

20

45

ns

us

ns

CLK

-

1

Row precharge time

Row active time

tRAS(min)

tRAS(max)

tRC(min)

100

2

Row cycle time

60

65

70

1

2, 5

5

Last data in to row precharge

Last data in to Active delay

tRDL(min)

tDAL(min)

2 CLK + tRP

Last data in to new col. address delay

Last data in to burst stop

tCDL(min)

tBDL(min)

tCCD(min)

1

2

1

CLK

ea

2

3

4

Col. address to col. address delay

Number of valid output data

CAS latency=3

CAS latency=2

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported .

SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

-7C

-7A

-1H

-1L

Parameter

Symbol

tCC

Unit Note

Min

7.5

Max

Min

7.5

10

Max

Min

10

Max

Min

10

Max

CAS latency=3

CLK cycle time

1000

ns

1

1,2

2

CAS latency=2

CAS latency=3

CAS latency=2

CAS latency=3

CAS latency=2

10

12

5.4

6

7

CLK to valid

output delay

tSAC

3

2

1

3

2

1

Output data

hold time

tOH

3

CLK high pulse width

CLK low pulse width

Input setup time

tCH

tCL

2.5

1.5

0.8

1

2.5

1.5

0.8

1

ns

3

2

tSS

tSH

tSLZ

Input hold time

CLK to output in Low-Z

CAS latency=3

CAS latency=2

5.4

6

7

CLK to output

in Hi-Z

tSHZ

ns

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

SIMPLIFIED TRUTH TABLE

A12, A11

A9 ~ A0

Command

CKEn-1

CKEn

CS

RAS

CAS

WE

DQM BA0,1

A10/AP

Note

Register

Refresh

Mode register set

Auto refresh

H

X

H

L

X

OP code

1,2

3

H

L

H

X

Entry

3

Self

L

H

L

H

X

L

H

X

H

X

H

3

refresh

Exit

H

3

Bank active & row addr.

H

X

V

Row address

Column

address

(A0 ~ A8)

Read &

column address

Auto precharge disable

Auto precharge enable

Auto precharge disable

Auto precharge enable

L

H

L

4

4,5

4

L

H

L

H

L

Column

address

(A0 ~ A8)

Write &

column address

H

X

V

H

X

L

4,5

6

Burst stop

Precharge

H

X

L

H

L

H

L

X

Bank selection

All banks

V

X

H

L

X

V

X

H

X

V

X

V

X

H

X

V

X

V

X

H

X

V

Entry

H

L

X

Clock suspend or

active power down

X

Exit

L

H

L

X

H

L

X

Entry

H

Precharge power down mode

H

L

Exit

L

H

X

DQM

H

V

X

7

H

L

X

H

X

H

X

H

No operation command

(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code

A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.

A new command can be issued after 2 clock cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

PACKAGE DIMENSIONS

Units : Inches (Millimeters)

2.66

(67.56)

2.50

(63.60)

2-R 0.078 Min

(2.00 Min)

0.16 ± 0.039

(4.00 ± 0.10)

1

59

61

143

0.91

(23.20)

1.29

(32.80)

0.13

(3.30)

2-f 0.07

(1.80)

0.18

(4.60)

0.083

(2.10)

0.10

(2.50)

Z

Y

0.15

(3.70)

2

60

62

144

0.150 Max

(3.80 Max)

0.024 ± 0.001

(0.600 ± 0.050)

0.16 ± 0.0039

(4.00 ± 0.10)

0.008 ±0.006

(0.200 ±0.150)

0.06 ± 0.0039

(1.50 ± 0.1)

0.03 TYP

(0.80 TYP)

0.04 ± 0.0039

(1.00 ± 0.10)

Detail Y

Detail Z

Tolerances : ±.006(.15) unless otherwise specified

The used device is 16Mx16 SDRAM, TSOP

SDRAM Part No. : K4S561632C

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

M464S3254CTS-L7C/L7A/L1H/L1L, C7C/C7A/C1H/C1L

• Organization : 32MX64

• Composition : 16MX16 *8

• Used component part # : K4S561632C-TL7C/7A/1H/1L,TC7C/7A/1H/1L

• # of rows in module : 2row

• # of banks in component : 4 banks

• Feature : 1,250 mil height & double sided component

• Refresh : 8K/64ms

• Contents :

Function Supported

-7A -1H

128bytes

Hex value

Note

Byte#.

Function described

-7C

-1L

-7C

-7A

-1H

-1L

0

1

# of bytes written into serial memory at module manufacturer

Total # of bytes of SPD memory device

Fundamental memory type

80h

08h

04h

0Dh

09h

02h

40h

00h

01h

256bytes (2K-bit)

2

SDRAM

13

3

# of row address on this assembly

1

4

# of column address on this assembly

# of module Rows on this assembly

Data width of this assembly

9

5

2 Row

64 bits

-

6

7

...... Data width of this assembly

8

Voltage interface standard of this assembly

SDRAM cycle time from clock @CAS latency of 3

SDRAM access time from clock @CAS latency of 3

DIMM configuration type

LVTTL

9

7.5ns 7.5ns

5.4ns 5.4ns

10ns

6ns

10ns

6ns

75h

54h

75h

54h

A0h

60h

A0h

60h

2

10

11

12

13

14

15

16

17

18

19

20

Non parity

00h

82h

10h

00h

01h

8Fh

04h

06h

01h

Refresh rate & type

7.8us, support self refresh self

Primary SDRAM width

x16

None

Error checking SDRAM width

Minimum clock delay for back-to-back random column

SDRAM device attributes : Burst lengths supported

SDRAM device attributes : # of banks on SDRAM device

SDRAM device attributes : CAS latency

SDRAM device attributes : CS latency

SDRAM device attributes : Write latency

tCCD = 1CLK

1, 2, 4, 8 & full page

4 banks

2 & 3

0 CLK

Non-buffered/Non-Registered &

redundant addressing

21

SDRAM module attributes

00h

+/- 10% voltage tolerance,

Burst Read Single bit Write

precharge all, auto precharge

22

SDRAM device attributes : General

0Eh

23

24

25

26

27

28

29

30

31

32

33

34

SDRAM cycle time @CAS latency of 2

SDRAM access time @CAS latency of 2

SDRAM cycle time @CAS latency of 1

SDRAM access time @CAS latency of 1

Minimum row precharge time (=tRP)

Minimum row active to row active delay (tRRD)

Minimum RAS to CAS delay (=tRCD)

Minimum activate precharge time (=tRAS)

Module Row density

7.5ns

5.4ns

10ns

6ns

10ns

6ns

12ns

7ns

75h

54h

A0h

60h

A0h

60h

C0h

70h

2

-

00h

15ns

45ns

20ns

15ns

20ns

45ns

20ns

50ns

20ns

50ns

0Fh

2Dh

14h

0Fh

14h

2Dh

14h

32h

14h

32h

2 Row of 128MB

20h

Command and Address signal input setup time

Command and Address signal input hold time

Data signal input setup time

1.5ns 1.5ns

0.8ns 0.8ns

1.5ns 1.5ns

2ns

1ns

2ns

1ns

2ns

15h

08h

15h

08h

15h

20h

10h

20h

10h

20h

Rev. 0.0 May 2001

PC133/PC100 SODIMM

M464S3254CTS

SERIAL PRESENCE DETECT INFORMATION

Function Supported

Hex value

Note

Byte #

Function described

-7C

-7A

-1H

-1L

-7C

-7A

-1H

-1L

35

Data signal input hold time

0.8ns 0.8ns

1ns

08h

10h

36~61 Superset information (maybe used in future)

-

00h

12h

62

63

64

SPD data revision code

Current release Intel spd 1.2B/A

Checksum for bytes 0 ~ 62

Manufacturer JEDEC ID code

-

79h

BAh

21h

51h

Samsung

CEh

00h

01h

4Dh

34h

20h

36h

34h

53h

33h

32h

35h

34h

43h

54h

53h

2Dh

65~71 ...... Manufacturer JEDEC ID code

Samsung

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

Manufacturing location

Onyang Korea

Manufacturer part # (Memory module)

Manufacturer part # (DIMM configuration)

Manufacturer part # (Data bits)

M

4

Blank

...... Manufacturer part # (Data bits)

Manufacturer part # (Mode & operating voltage)

Manufacturer part # (Module depth)

...... Manufacturer part # (Module depth)

Manufacturer part # (Refresh, # of banks in Comp. & inter-

Manufacturer part # (Composition component)

Manufacturer part # (Component revision)

Manufacturer part # (Package type)

Manufacturer part # (PCB revision & type)

Manufacturer part # (Hyphen)

6

4

S

3

2

5

4

C

T

S

" - "

L / C

Manufacturer part # (Power)

4Ch / 43h

Manufacturer part # (Minimum cycle time)

Manufacturer part # (TBD)

7

1

L

37h

43h

37h

31h

48h

31h

4Ch

C

A

H

41h

Blank

S

20h

Manufacturer revision code (For PCB)

...... Manufacturer revision code (For component)

Manufacturing date (Week)

53h

C-die (4th Gen.)

43h

-

3

4

5

Manufacturing date (Year)

-

95~98 Assembly serial #

-

99~12 Manufacturer specific data (may be used in future)

Undefined

100MHz

126

127

System frequency for 100MHz

Intel Specification details

64h

Detailed 100MHz Information

Undefined

CFh

CDh

128+ Unused storage locations

-

5

Note :

1. The bank select address is excluded in counting the total # of addresses.

2. This value is based on the component specification.

3. These bytes are programmed by code of Date Week & Date Year with BCD format.

4. These bytes are programmed by Samsung ¢s own Assembly Serial # system. All modules may have different unique serial #.

5. These bytes are Undefined and can be used for Samsung ¢s own purpose.

Rev. 0.0 May 2001


型号：	M464S3254CTS-L1H
厂家：	SAMSUNG
描述：	DDR DRAM Module, 32MX64, 6ns, CMOS, SODIMM-144 动态存储器双倍数据速率
文件：	总11页 (文件大小：181K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M464S3254CTS-L1H [SAMSUNG]

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