M464S6453EN0-C7A [SAMSUNG]
SDRAM Unbuffered SODIMM; 无缓冲SDRAM SODIMM
| 型号： | M464S6453EN0-C7A |
| 厂家： | 
SAMSUNG |
| 描述： | SDRAM Unbuffered SODIMM |
| 文件： | 总18页 (文件大小：270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
SDRAM Unbuffered SODIMM
144pin Unbuffered SODIMM based on 256Mb E-die
64-bit Non ECC
Revision 1.5
May 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
Revision History
Revision 1.1 (Sepember, 2003)
- Corrected typo.
Revision 1.2 (February, 2004)
- Corrected typo.
Revision 1.3 (March. 2004)
- Corrected package dimension.
Revision 1.4 (March. 2004)
- Modified DC Characteristics Notes.
Revision 1.5 (May. 2004)
- Added Note 5. sentense of tRDL parameter
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
144Pin Unbuffered SODIMM based on 256Mb E-die(x8, x16)
Ordering Information
Component
Package
Part Number
Density
Organization
Component Composition
Height
M464S1654ETS-C(L)7A
M464S3254ETS-C(L)7A
M464S6453EN0-C(L)7A
128MB
256MB
512MB
16M x 64
32M x 64
64M x 64
16Mx16(K4S561632E) * 4EA
16Mx16(K4S561632E) * 8EA
32Mx 8 (K4S560832E)*16EA
1,000mil
1,250mil
1,250mil
54-TSOP(II)
54-sTSOP(II)
Operating Frequencies
7A
@CL3
133MHz(7.5ns)
3 - 3 - 3
@CL2
Maximum Clock Frequency
CL-tRCD-tRP(clock)
100MHz(10ns)
2 - 2 - 2
Feature
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• Serial presence detect with EEPROM
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
PIN CONFIGURATIONS (Front side/back side)
Pin
Front
Pin
Back
Pin
Front
Pin
Back
Pin
Front
Pin
Back
1
3
5
7
9
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VDD
A0
2
4
6
8
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
VSS
DQM4
DQM5
VDD
A3
A4
51
53
55
57
59
DQ14
DQ15
VSS
NC
52
54
56
58
60
DQ46
DQ47
VSS
NC
95
97
99
DQ21
DQ22
DQ23
VDD
A6
A8
96
98
DQ53
DQ54
DQ55
VDD
A7
BA0
VSS
BA1
A11
VDD
DQM6
DQM7
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
NC
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Note :
Voltage Key
VSS
A9
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
**CLK0
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
**CKE0
VDD
CAS
**CKE1
A12
*A13
**CLK1
VSS
NC
NC
VDD
DQ48
DQ49
DQ50
DQ51
VSS
A10/AP
VDD
DQM2
DQM3
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
VDD
RAS
WE
**CS0
**CS1
DU
VSS
NC
NC
VDD
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
A1
A2
A5
VSS
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
DQ40
DQ41
DQ42
DQ43
VDD
DQ44
DQ45
SDA
VDD
SCL
VDD
DQ52
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Pin Description
Pin Name
A0 ~ A12
Function
Address input (Multiplexed)
Select bank
Pin Name
Function
WE
Write enable
DQM
BA0 ~ BA1
DQ0 ~ DQ63
CLK0 ~ CLK1
CKE0 ~ CKE1
CS0 ~ CS1
RAS
DQM0 ~ 7
VDD
Data input/output
Power supply (3.3V)
Ground
Clock input
VSS
Clock enable input
Chip select input
SDA
SCL
DU
Serial data I/O
Serial clock
Row address strobe
Column address strobe
Don′t use
CAS
NC
No connection
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
PIN CONFIGURATION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA12
A0 ~ A12
Address
Column address : (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
BA0 ~ BA1
RAS
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data input/output mask
DQ0 ~ 63
VDD/VSS
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power supply/ground
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
128MB, 16Mx64 Module (M464S1654ETS) (Populated as 1 bank of x16 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
CS0
DQM0
DQM4
LDQM CS
DQ0
DQ1
LDQM CS
DQ0
DQ1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ2
DQ2
U0
U2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
UDQM
DQM5
UDQM
DQ8
DQ9
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM2
DQM6
LDQM CS
LDQM CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
UDQM
U1
U3
DQM3
DQM7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ9
DQ8
DQ9
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
SDRAM U0 ~ U3
A0 ~ A12, BA0 & 1
Serial PD
SCL
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
SDRAM U0 ~ U3
RAS
CAS
WE
SDA
WP
SA0 SA1 SA2
47KΩ
CKE0
U0
U1
U2
10Ω
DQn
Every DQ pin of SDRAM
CLK0
VDD
U3
Three 0.1uF X7R 0603Capacitors
per each SDRAM
To all SDRAMs
10Ω
Vss
CLK1
10pF
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
256MB, 32Mx64 Module (M366S3254ETS) (Populated as 2 bank of x16 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
CS1
CS0
DQM0
DQM4
LDQM CS
LDQM CS
LDQM CS
LDQM CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ0
DQ1
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U0
U4
U2
U6
DQM1
UDQM
UDQM
DQM5
UDQM
UDQM
DQ8
DQ9
DQ8
DQ9
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM2
DQM6
LDQM CS
LDQM CS
LDQM CS
LDQM CS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ0
DQ1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
U5
U3
U7
DQM3
UDQM
UDQM
DQM7
UDQM
UDQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ8
DQ9
DQ8
DQ9
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ8
DQ9
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U3
SDRAM U4 ~ U7
A0 ~ A12, BA0 & 1
RAS
CAS
Serial PD
SCL
SDA
WP
SA0 SA1 SA2
47KΩ
WE
CKE0
CKE1
10Ω
DQn
Every DQ pin of SDRAM
U0/U4
U1/U5
U2/U6
U3/U7
VDD
CLK0/1
Three 0.1 uF X7R 0603 Capacitors
per each SDRAM
To all SDRAMs
Vss
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
512MB, 64Mx64 Module (M366S6453EN0) (Populated as 2 bank of x8 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
CS1
•
CS0
DQM0
•
•
•
DQM4
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ2
DQ2
DQ2
DQ2
U4
U12
U0
U8
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
•
DQM1
DQM5
•
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQ8
DQ9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ2
DQ2
DQ2
DQ2
U5
U13
U1
U9
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
•
•
DQM2
DQM6
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ2
DQ2
DQ2
DQ2
U6
U14
U2
U10
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
•
•
DQM3
DQM7
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQM CS
DQ0
DQ1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ2
DQ2
DQ2
DQ2
U7
U15
U3
U11
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
DQ3
DQ4
DQ5
DQ6
DQ7
Serial PD
WP
A0 ~ A12, BA0 & 1
SDRAM U0 ~ U15
SCL
SDA
SA0 SA1 SA2
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U15
SDRAM U0 ~ U7
RAS
CAS
WE
47KΩ
CKE0
CKE1
SDRAM U8 ~ U15
CLK0
10Ω
U0/U1/U4/U5
U8/U9/U12/U13
DQn
Every DQpin of SDRAM
•
VDD
Vss
•
•
•
Two 0.1uF Capacitors
per each SDRAM
U2/U3/U6/U7
To all SDRAMs
•
•
CLK1
U10/U11/U14/U15
•
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
Unit
V
-1.0 ~ 4.6
V
-55 ~ +150
1.0 * # of component
50
°C
W
Power dissipation
PD
Short circuit current
IOS
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input high voltage
Input low voltage
3.0
VDDQ+0.3
V
1
VIL
0
-
0.8
-
V
2
Output high voltage
Output low voltage
Input leakage current
VOH
VOL
ILI
V
IOH = -2mA
IOL = 2mA
3
-
0.4
10
V
-10
-
uA
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
M464S1654ETS
M464S3254ETS
M464S6453EN0
Parameter
Symbol
Unit
Min
Max
Min
Max
Min
Max
Input capacitance (A0 ~ A12, BA0 ~ BA1)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0 ~ CKE1)
Input capacitance (CLK0 ~ CLK1)
Input capacitance (CS0 ~ CS1)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
15
15
15
15
15
10
10
25
25
25
21
25
12
12
25
25
15
15
15
10
10
45
45
25
21
25
12
12
45
45
25
15
15
10
13
90
90
45
21
25
15
18
pF
pF
pF
pF
pF
pF
pF
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
DC CHARACTERISTICS
M464S1654ETS (16M x 64, 128MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
360
mA
mA
1
ICC2P
CKE ≤ VIL(max), tCC = 10ns
8
8
Precharge standby current
in power-down mode
ICC2PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2N
80
40
Precharge standby current
in non power-down mode
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC2NS
ICC3P
CKE ≤ VIL(max), tCC = 10ns
25
25
Active standby current in
power-down mode
ICC3PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3N
100
100
mA
mA
Active standby current in
non power-down mode
(One bank active)
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
tCCD = 2CLKs
ICC4
520
mA
1
2
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
720
12
6
mA
mA
mA
C
Self refresh current
CKE ≤ 0.2V
L
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
DC CHARACTERISTICS
M464S3254ETS (32M x 64, 256MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
460
mA
mA
1
ICC2P
CKE ≤ VIL(max), tCC = 10ns
16
16
Precharge standby current
in power-down mode
ICC2PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2N
160
80
Precharge standby current
in non power-down mode
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC2NS
ICC3P
CKE ≤ VIL(max), tCC = 10ns
50
50
Active standby current in
power-down mode
ICC3PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3N
200
200
mA
mA
Active standby current in
non power-down mode
(One bank active)
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
tCCD = 2CLKs
ICC4
620
mA
1
2
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
820
24
mA
mA
mA
C
Self refresh current
CKE ≤ 0.2V
L
12
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
DC CHARACTERISTICS
M464S6453EN0 (64M x 64, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
7A
Parameter
Symbol
Test Condition
Unit
Note
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
Operating current
(One bank active)
ICC1
840
mA
mA
1
ICC2P
CKE ≤ VIL(max), tCC = 10ns
32
32
Precharge standby current
in power-down mode
ICC2PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2N
320
160
Precharge standby current
in non power-down mode
mA
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC2NS
ICC3P
CKE ≤ VIL(max), tCC = 10ns
100
100
Active standby current in
power-down mode
ICC3PS
CKE & CLK ≤ VIL(max), tCC =∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3N
400
400
mA
mA
Active standby current in
non power-down mode
(One bank active)
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC =∞
Input signals are stable
ICC3NS
IO = 0 mA
Operating current
(Burst mode)
Page burst
4Banks activated
tCCD = 2CLKs
ICC4
1,000
mA
1
2
Refresh current
ICC5
ICC6
tRC ≥ tRC(min)
1,000
48
mA
mA
mA
C
Self refresh current
CKE ≤ 0.2V
L
48
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50Ω
50pF
50pF
870Ω
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
7A
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
15
ns
ns
1
1
1
1
20
Row precharge time
20
ns
tRAS(min)
tRAS(max)
tRC(min)
45
ns
Row active time
100
us
Row cycle time
65
ns
1
2,5
5
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tDAL(min)
tCDL(min)
tBDL(min)
tCCD(min)
2
CLK
-
2 CLK + tRP
1
1
1
2
1
CLK
CLK
CLK
2
2
Col. address to col. address delay
3
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
7A
Parameter
Symbol
Unit
ns
Note
1
Min
7.5
10
Max
CAS latency=3
CLK cycle
time
tCC
1000
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
5.4
6
CLK to valid
output delay
tSAC
ns
1,2
2
3
Output data
hold time
tOH
ns
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
2.5
2.5
1.5
0.8
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
5.4
6
CLK to output
in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
A0 ~ A9,
A11, A12
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
Mode register set
Register
Refresh
H
X
H
L
L
L
L
L
X
OP code
1,2
3
Auto refresh
H
L
L
L
L
H
X
X
X
X
Entry
Exit
3
Self
refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
L
Read &
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
4
4,5
4
Column
L
L
H
H
L
L
H
L
column address
address
H
L
Write &
Column
address
H
X
X
V
column address
H
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank selection
All banks
V
X
L
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
Notes :
1. OP Code : Operand code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
PACKAGE DIMENSIONS : 16Mx64 (M464S1654ETS)
Units : Inches (Millimeters)
2.66
(67.56)
2.50
(63.60)
2-R 0.078 Min
(2.00 Min)
0.16 ± 0.039
(4.00 ± 0.10)
1
59
61
143
0.91
(23.20)
1.29
(32.80)
0.13
(3.30)
2-φ 0.07
(1.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
Z
Y
0.15
(3.70)
2
60
62
144
0.150 Max
(3.80 Max)
0.024 ± 0.001
(0.600 ± 0.050)
0.16 ± 0.0039
(4.00 ± 0.10)
0.008 ±0.006
(0.200 ±0.150)
0.06 ± 0.0039
(1.50 ± 0.1)
0.03 TYP
(0.80 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ± 0.006(.15) unless otherwise specified
The used device is 16Mx16 SDRAM, TSOPII
SDRAM Part No. : K4S561632E
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
PACKAGE DIMENSIONS : 32Mx64 (M464S3254ETS)
Units : Inches (Millimeters)
2.66
(67.56)
2.50
(63.60)
2-R 0.078 Min
(2.00 Min)
0.16 ± 0.039
(4.00 ± 0.10)
1
59
61
143
0.91
(23.20)
1.29
(32.80)
0.13
(3.30)
2-φ 0.07
(1.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
Z
Y
0.15
(3.70)
2
60
62
144
0.150 Max
(3.80 Max)
0.024 ± 0.001
(0.600 ± 0.050)
0.16 ± 0.0039
(4.00 ± 0.10)
0.008 ±0.006
(0.200 ±0.150)
0.06 ± 0.0039
(1.50 ± 0.1)
0.03 TYP
(0.80 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 16Mx16 SDRAM, TSOPII
SDRAM Part No. : K4S561632E
Rev. 1.5 May 2004
128MB, 256MB, 512MB Unbuffered SODIMM
SDRAM
PACKAGE DIMENSIONS : 64Mx64 (M464S6453EN0)
Units : Inches (Millimeters)
2.66
(67.60)
2.50
(63.60)
2-R 0.078 Min
(2.00 Min)
0.16 ± 0.039
(4.00 ± 0.10)
1
59
61
143
0.91
(23.20)
1.29
(32.80)
0.13
(3.30)
2-φ 0.07
(1.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
Z
Y
0.15
(3.70)
2
60
62
144
0.150 Max
(3.80 Max)
0.024 ± 0.001
(0.600 ± 0.050)
0.16 ± 0.0039
(4.00 ± 0.10)
0.008 ±0.006
(0.200 ±0.150)
0.06 ± 0.0039
(1.50 ± 0.1)
0.03 TYP
(0.80 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Y
Detail Z
Tolerances : ±.006(.15) unless otherwise specified
The used device is 32Mx8 SDRAM, sTSOP
SDRAM Part No. : K4S560832E
Rev. 1.5 May 2004
相关型号：
M464S6453J60-C7A
Synchronous DRAM Module, 64MX8, 5.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, SODIMM-144
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M464S6453J60-L7A
Synchronous DRAM Module, 64MX8, 5.4ns, CMOS, HALOGEN FREE AND ROHS COMPLIANT, SODIMM-144
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