M466S0823CT3-L10 [SAMSUNG]
Synchronous DRAM Module, 8MX64, 7ns, CMOS, 1.050 INCH HEIGHT, SODIMM-144;
| 型号： | M466S0823CT3-L10 |
| 厂家： | 
SAMSUNG |
| 描述： | Synchronous DRAM Module, 8MX64, 7ns, CMOS, 1.050 INCH HEIGHT, SODIMM-144 时钟 动态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M466S0823CT3
PC66 SODIMM
M466S0823CT3 SDRAM SODIMM
8Mx64 SDRAM SODIMM based on 8Mx8, 4Banks, 4K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
FEATURE
The Samsung M466S0823CT3 is a 8M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M466S0823CT3 consists of eight CMOS 8M x 8 bit with 4banks
Synchronous DRAMs in TSOP-II 400mil package and a 2K
EEPROM in 8-pin TSSOP package on a 144-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM. The
M466S0823CT3 is a Small Outline Dual In-line Memory Module
and is intended for mounting into 144-pin edge connector sock-
ets.
• Performance range
Part No.
Max Freq. (Speed)
M466S0823CT3-L10
66MHz (@ CL=2 & CL=3)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ± 0.3V power supply
• MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB : Height (1,050mil), double sided component
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth,
high performance memory system applications.
PIN CONFIGURATIONS (Front side/back side)
PIN NAMES
Pin Name
A0 ~ A11
Function
Address input (Multiplexed)
Select bank
1
3
VSS
DQ0
DQ1
DQ2
2
4
6
8
VSS
51 DQ14 52 DQ46 95 DQ21 96 DQ53
BA0 ~ BA1
DQ0 ~ DQ63
DQ32 53 DQ15 54 DQ47 97 DQ22 98 DQ54
Data input/output
5
DQ33 55
DQ34 57
VSS
NC
NC
56
58
60
VSS
NC
NC
99 DQ23 100 DQ55
CLK0 ~ CLK1 Clock input
7
101
103
105
107
109
VDD
A6
102 VDD
104 A7
9
DQ3 10 DQ35 59
12
CKE0
CS0
RAS
CAS
WE
Clock enable input
11
VDD
VDD
A8
106 BA0
108 VSS
110 BA1
Chip select input
Row address strobe
Column address strobe
Write enable
13 DQ4 14 DQ36
15 DQ5 16 DQ37
VSS
A9
Voltage Key
17 DQ6 18 DQ38 61 CLK0 62 CKE0 111 A10/AP 112 A11
19 DQ7 20 DQ39 63 64 VDD 113 114 VDD
21 22 65 RAS 66 CAS 115 DQM2 116 DQM6
VDD
VDD
DQM0 ~ 7
VDD
DQM
VSS
VSS
Power supply (3.3V)
Ground
23 DQM0 24 DQM4 67
25 DQM1 26 DQM5 69
WE
68 *CKE1 117 DQM3 118 DQM7
70 *A12 119 120 VSS
CS0
VSS
VSS
27
29
31
33
35
VDD
A0
28
30
32
34
36
VDD
A3
71 *CS1 72 *A13 121 DQ24 122 DQ56
SDA
SCL
DU
Serial data I/O
Serial clock
73
75
77
79
DU
VSS
NC
74 CLK1 123 DQ25 124 DQ57
A1
A4
76
78
80
82
VSS 125 DQ26 126 DQ58
Don¢t use
A2
A5
NC
NC
127 DQ27 128 DQ59
129 130 VDD
NC
No connection
VSS
VSS
NC
VDD
37 DQ8 38 DQ40 81
VDD
VDD 131 DQ28 132 DQ60
*
These pins are not used in this module.
39 DQ9 40 DQ41 83 DQ16 84 DQ48 133 DQ29 134 DQ61
41 DQ10 42 DQ42 85 DQ17 86 DQ49 135 DQ30 136 DQ62
43 DQ11 44 DQ43 87 DQ18 88 DQ50 137 DQ31 138 DQ63
** These pins should be NC in the system
which does not support SPD.
45
47 DQ12 48 DQ44 91
49 DQ13 50 DQ45 93 DQ20 94 DQ52 143
VDD
46
VDD
89 DQ19 90 DQ51 139
92 VSS 141 **SDA 142 **SCL
VDD 144 VDD
VSS
140 VSS
VSS
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 Jun. 1999
M466S0823CT3
PC66 SODIMM
PIN CONFIGURATION DESCRIPTION
Pin
Name
System clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Chip select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
CKE
Clock enable
CKE should be enabled 1CLK+tSS prior to valid command.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
A0 ~ A11
BA0 ~ BA1
RAS
Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Bank select address
Row address strobe
Column address strobe
Write enable
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
CAS
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
WE
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQM0 ~ 7
Data input/output mask
DQ0 ~ 63
VDD/VSS
Data input/output
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Power supply/ground
Rev. 0.0 Jun. 1999
M466S0823CT3
PC66 SODIMM
FUNCTIONAL BLOCK DIAGRAM
CS0
DQM0
DQM4
DQ32
DQM CS
CS
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U0
U4
DQM1
DQM5
DQM CS
DQM CS
DQ8
DQ9
DQ0
DQ1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U1
U5
DQM2
DQM6
DQM
DQM
CS
CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U2
U6
DQM7
DQM3
DQM
DQM
CS
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U3
U7
Serial PD
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
SDRAM U0 ~ U7
A0 ~ An, BA0 & 1
SCL
SDA
A0 A1 A2
RAS
CAS
WE
10W
U0/U4
CKE0
U1/U5
U2/U6
CLK0/1
U3/U7
10W
VDD
Vss
Two 0.1uF Capacitors
per each SDRAM
To all SDRAMs
Rev. 0.0 Jun. 1999
M466S0823CT3
PC66 SODIMM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
8
Unit
V
V
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter
Supply voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
-
Typ
Max
Unit
V
Note
3.3
3.6
Input high voltage
3.0
VDDQ+0.3
V
1
Input low voltage
VIL
0
-
0.8
-
V
2
IOH = -2mA
IOL = 2mA
3
Output high voltage
VOH
VOL
IIL
V
Output low voltage
-
0.4
8
V
Input leakage current (Inputs)
Input leakage current (I/O pins)
-8
-
uA
uA
IIL
-1.5
-
1.5
3,4
Notes :
1. VIH (max) = 5.6V AC.The overshoot voltage duration is £ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V £ VOUT £ VDDQ.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A11, BA0 ~ BA1)
Input capacitance (RAS, CAS, WE)
Input capacitance (CKE0)
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
COUT
40
40
35
25
35
5
60
60
55
35
55
15
15
pF
pF
pF
pF
pF
pF
pF
Input capacitance (CLK0 ~ CLK1)
Input capacitance (CS0)
Input capacitance (DQM0 ~ DQM7)
Data input/output capacitance (DQ0 ~ DQ63)
5
Rev. 0.0 Jun. 1999
M466S0823CT3
PC66 SODIMM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Version
-10
CAS
Latency
Parameter
Symbol
Test Condition
Burst length = 1
tRC ³ tRC(min)
IOL = 0 mA
Unit
mA
Note
Operating current
(One bank active)
ICC1
520
1
ICC2P
CKE £ VIL(max), tCC = 15ns
CKE & CLK £ VIL(max), tCC =¥
8
8
Precharge standby current in
power-down mode
mA
ICC2PS
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC2N
96
48
Precharge standby current in
non power-down mode
mA
mA
CKE ³ VIH(min), CLK £ VIL(max), tCC =¥
Input signals are stable
ICC2NS
ICC3P
CKE £ VIL(max), tCC = 15ns
CKE & CLK £ VIL(max), tCC =¥
16
16
Active standby current in
power-down mode
ICC3PS
CKE ³ VIH(min), CS ³ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns
ICC3N
160
80
mA
mA
Active standby current in
non power-down mode
(One bank active)
CKE ³ VIH(min), CLK £ VIL(max), tCC =¥
Input signals are stable
ICC3NS
IOL = 0 mA
Page burst
2Banks activated
tCCD = 2CLKs
3
600
560
Operating current
(Burst mode)
ICC4
mA
1
2
2
Refresh current
ICC5
ICC6
tRC ³ tRC(min)
880
3.6
mA
mA
Self refresh current
CKE £ 0.2V
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
Rev. 0.0 Jun. 1999
M466S0823CT3
PC66 SODIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Value
2.4/0.4
1.4
Unit
V
Input timing measurement reference level
Input rise and fall time
V
tr/tf = 1/1
1.4
ns
V
Output timing measurement reference level
Output load condition
See Fig. 2
3.3V
Vtt = .4V
1200W
50W
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Output
Z0 = 50W
50pF
50pF
870W
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-10
20
24
24
50
100
80
12
1
Row active to row active delay
RAS to CAS delay
tRRD(min)
tRCD(min)
tRP(min)
ns
ns
1
1
1
1
Row precharge time
ns
tRAS(min)
tRAS(max)
tRC(min)
ns
Row active time
us
Row cycle time
ns
1
2
2
2
3
Last data in to row precharge
Last data in to new col. address delay
Last data in to burst stop
tRDL(min)
tCDL(min)
tBDL(min)
tCCD(min)
ns
CLK
CLK
CLK
1
Col. address to col. address delay
1
CAS latency=3
CAS latency=2
2
Number of valid output data
ea
4
1
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time,
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 0.0 Jun. 1999
M466S0823CT3
PC66 SODIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
REFER TO THE INDIVIDUAL COMPONENT, NOT THE WHOLE MODULE.
-10
Parameter
Symbol
Unit
ns
Note
1
Min
10
Max
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CAS latency=3
CAS latency=2
CLK cycle time
tCC
1000
13
7
7
CLK to valid output delay
Output data hold time
tSAC
ns
1,2
2
3
tOH
ns
3
CLK high pulse width
CLK low pulse width
Input setup time
tCH
tCL
3.5
3.5
2.5
1.5
1
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
Input hold time
tSH
tSLZ
CLK to output in Low-Z
CAS latency=3
CAS latency=2
7
7
CLK to output in Hi-Z
tSHZ
ns
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 0.0 Jun. 1999
M466S0823CT3
PC66 SODIMM
SIMPLIFIED TRUTH TABLE
A11,
A9 ~ A0
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM BA0,1
A10/AP
Note
Command
Register
Refresh
Mode register set
Auto refresh
H
X
H
L
L
L
L
L
X
OP code
1,2
3
H
L
L
L
L
H
X
X
X
X
Entry
3
Self
L
H
L
H
X
L
H
X
H
H
X
H
3
refresh
Exit
H
3
Bank active & row addr.
H
H
X
X
X
X
V
V
Row address
Column
address
(A0 ~ A8)
Read &
column address
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
L
H
L
4
4,5
4
L
L
H
H
L
L
H
L
Column
address
(A0 ~ A8)
Write &
column address
H
X
X
V
H
X
L
4,5
6
Burst stop
Precharge
H
H
X
X
L
L
H
L
H
H
L
L
X
X
Bank selection
All banks
V
X
X
H
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
H
L
X
Clock suspend or
active power down
X
X
Exit
L
H
L
X
H
L
X
X
Entry
H
Precharge power down mode
H
L
Exit
L
H
X
X
X
DQM
H
H
V
X
X
X
7
H
L
X
H
X
H
X
H
No operation command
(V=Valid, X=Don¢t care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.0 Jun. 1999
M466S0823CT3
PC66 SODIMM
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
2.66
(67.60)
2.50
(63.60)
2-R 0.078 Min
(2.00 Min)
0.16 ± 0.039
(4.00 ± 0.10)
1.29
(32.80)
0.13
(3.30)
0.91
(23.20)
2-f 0.07
(1.80)
0.18
(4.60)
0.083
(2.10)
0.10
(2.50)
Z
Y
0.15
(3.70)
0.150 Max
(3.81 Max)
0.024 ± 0.001
(0.600 ± 0.050)
0.16 ± 0.0039
(4.00 ± 0.10)
0.008 ±0.006
(0.200 ±0.150)
0.06 ± 0.0039
(1.50 ± 0.1)
0.03 TYP
(0.80 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.005(.13) unless otherwise specified
The used device is 8Mx8 SDRAM, TSOP
SDRAM Part No. : K4S640832C
Rev. 0.0 Jun. 1999
相关型号：
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