M470L0914ET0-LA2 [SAMSUNG]
DDR DRAM Module, 8MX64, 0.75ns, CMOS, SODIMM-200;
| 型号： | M470L0914ET0-LA2 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 8MX64, 0.75ns, CMOS, SODIMM-200 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总17页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
DDR SDRAM Unbuffered SODIMM
200pin Unbuffered SODIMM based on 128Mb E-die (x16)
with 64-bit Non ECC
Revision 1.4
March. 2004
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
Revision History
Revision 1.0 (December, 2002)
- First release
Revision 1.1 (Febrary, 2003)
- Add 64MB SODIMM M470L0914ET0
Revision 1.2 (March, 2003)
- Complete 128Mb x16 DC current spec.
Revision 1.3 (August, 2003)
- Corrected typo.
Revision 1.4 (March, 2004)
- Corrected package dimension.
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
184Pin Unbuffered DIMM based on 128Mb E-die (x16)
Ordering Information
Part Number
Density
64MB
Organization
8M x 64
Component Composition
Height
1,250mil
1,250mil
M470L0914ET0-C(L)B3/A2/B0
M470L1714ET0-C(L)B3/A2/B0
8Mx16 (K4H281638E) * 4EA
8Mx16 (K4H281638E) * 8EA
128MB
16M x 64
Operating Frequencies
B3(DDR333@CL=2.5)
133MHz
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Speed @CL2
Speed @CL2.5
CL-tRCD-tRP
133MHz
133MHz
2-3-3
100MHz
133MHz
2.5-3-3
166MHz
2.5-3-3
Feature
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil), single (64MB), double (128MB) sided
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
Pin Configurations (Front side/back side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
3
5
7
VREF
VSS
67
69
*71
*73
75
*77
*79
81
*83
85
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
/CK2
VDD
CKE1
DU
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
2
4
6
8
VREF
VSS
68
70
*72
*74
76
*78
*80
82
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
136
138
140
142
144
146
148
150
152
DQ38
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
/CK0
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
/CK1
CK1
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
*84
86 *DU/(RESET) 154
88
90
92
94
87
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
*89
*91
93
*95
97
VDD
VSS
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
96
98
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
99
*A12
A9
VSS
A7
A5
A3
100
102
104
106
108
110
112
114
116
118
120
*122
124
126
128
130
101
103
105
107
109
111
113
115
117
119
121
VSS
KEY
A4
A2
A0
KEY
41
43
45
47
49
51
53
55
57
59
61
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
42
44
46
48
50
52
54
56
58
60
62
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
A1
VDD
A10/AP
BA0
/WE
/CS0
VDD
BA1
/RAS
/CAS
/CS1
DU
VSS
DQ36
DQ37
123 *DU(A13) 191
125
127
129
VSS
DQ32
DQ33
193
195
197 VDDSPD
Note 1. * : These pins are not used in this module.
2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are reserved for x72 module, and are not used on x64 module.
Pin 95,122 are NC for 8Mx16 based module & used for 16Mx8 based module.
3. Pins 89, 91 are reserved for x72 modules.
Pin Description
Pin Name
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
Pin Name
Function
Data - in mask
Power supply (2.5V)
A0 ~ A11
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
CK0,CK0 ~ CK2, CK2
CKE0
DM0 ~ 7
VDD
VDDQ
VSS
Power Supply for DQS(2.5V)
Ground
Data Strobe input/output
Clock input
VREF
VDDSPD
SDA
Power supply for reference
Serial EEPROM Power
Serial data I/O
Clock enable input
Chip select input
CS0
RAS
Row address strobe
Column address strobe
Write enable
SCL
Serial clock
CAS
SA0 ~ 2
NC
Address in EEPROM
No connection
WE
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
6MB, 8M x 64 Non ECC Module (M470L0914ET0) (Populated as 1 bank of x8 DDR SDRAM Module)
Functional Block Diagram
CS0
DQS0
DM0
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
DQS4
DM4
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
CS
CS
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
D0
D2
DQS1
DM1
UDQS
UDM
I/0 8
DQS5
DM5
UDQS
UDM
I/0 8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
I/0 9
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
DQS2
DM2
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
DQS6
DM6
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
CS
CS
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
D1
D3
DQS3
DM3
UDQS
UDM
I/0 8
DQS7
UDQS
UDM
I/0 8
DM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
I/0 9
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
BA0 - BA1
BA0-BA1: DDR SDRAMs D0 - D3
A0-A11: DDR SDRAMs D0 - D3
D0/D1/Cap
A0 - A11
RAS
*Clock Net Wiring
RAS: SDRAMs D0 - D3
Cap/Cap/Cap
R=120Ω
± 5%
CAS
CAS: SDRAMs D0 - D3
CKE: SDRAMs D0 - D3
Clock Wiring
CK0/1/2
CK0./1/2
Card
CKE0
Clock
Input
SDRAMs
WE
WE: SDRAMs D0 - D3
CK0/CK0
CK1/CK1
CK2/CK2
2 SDRAMs
2 SDRAMs
NC
Edge
D1/D3/Cap
VDDSPD
SPD
Cap/Cap/Cap
VDD/VDDQ
D0 - D3
D0 - D3
Serial PD
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
SCL
WP
VREF
VSS
D0 - D3
D0 - D3
SDA
A0
A1
A2
VDDID
Strap: see Note 4
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
SA0 SA1 SA2
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
128MB, 16M x 64 Non ECC Module (M470L1714ET0) (Populated as 2 bank of x16 DDR SDRAM Module)
Functional Block Diagram
CS1
CS0
DQS0
DM0
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS4
DM4
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
CS
CS
CS
CS
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D4
D2
D6
DQS1
DM1
UDQS
UDM
I/0 8
UDQS
UDM
I/0 8
DQS5
DM5
UDQS
UDM
I/0 8
UDQS
UDM
I/0 8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/0 9
I/0 9
I/0 9
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
DQS2
DM2
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQS6
DM6
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
LDQS
LDM
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
CS
CS
CS
CS
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D1
D5
D3
D7
DQS3
DM3
UDQS
UDM
I/0 8
UDQS
UDM
I/0 8
DQS7
DM7
UDQS
UDM
I/0 8
UDQS
UDM
I/0 8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/0 9
I/0 9
I/0 9
I/0 9
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
I/0 10
I/0 11
I/0 12
I/0 13
I/0 14
I/0 15
D0/D2/Cap
BA0 - BA1
A0 - A11
RAS
BA0-BA1: DDR SDRAMs D0 - D7
A0-A11: DDR SDRAMs D0 - D7
RAS: SDRAMs D0 - D7
R=120Ω
± 5%
Clock Wiring
SDRAMs
D1/D3/Cap
D4/D6/Cap
Clock
CK0/1/2
CK0/1/2
Input
CAS
CAS: SDRAMs D0 - D7
CK0/CK0
CK1/CK1
CK2/CK2
4 SDRAMs
4 SDRAMs
NC
Card
Edge
CKE0
CKE1
CKE: SDRAMs D0 - D3
CKE: SDRAMs D4 - D7
*Clock Net Wiring
D5/D7/Cap
WE
WE: SDRAMs D0 - D7
VDDSPD
VDD/VDDQ
Notes:
SPD
Serial PD
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
D0 - D7
D0 - D7
SCL
WP
SDA
A0
A1
A2
VREF
VSS
D0 - D7
D0 - D7
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
SA0 SA1 SA2
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to VSS
VIN, VOUT
VDD, VDDQ
TSTG
-0.5 ~ 3.6
V
Voltage on VDD & VDDQ supply relative to VSS
Storage temperature
-1.0 ~ 3.6
-55 ~ +150
V
°C
W
Power dissipation
PD
1.5 * # of component
50
Short circuit current
IOS
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Symbol
Min
Max
2.7
Unit
Note
Supply voltage(for device with a nominal VDD of 2.5V)
VDD
2.3
I/O Supply voltage
VDDQ
VREF
VTT
2.3
2.7
V
V
I/O Reference voltage
I/O Termination voltage(system)
0.49*VDDQ
VREF-0.04
0.51*VDDQ
VREF+0.04
1
2
V
Input logic high voltage
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VI(Ratio)
II
VREF+0.15
-0.3
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.4
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
-0.3
V
0.36
0.71
-2
V
3
4
-
2
uA
uA
mA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V
IOH
-16.8
Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V
Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V
Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
IOL
IOH
IOL
16.8
-9
mA
mA
mA
9
Note :
1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.
Peak-to peak noise on VREF may not exceed +/-2% of the dc value.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the
maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the
maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
DDR SDRAM IDD spec table
M470L0914ET0 [ (8M x 16) * 4, 64MB Non ECC Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
620
740
12
540
660
12
540
660
12
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
260
220
220
480
1020
1000
840
12
240
200
200
420
920
860
780
12
240
200
200
420
920
860
780
12
IDD6
Normal
Low power
IDD7A
4
4
4
Optional
1580
1460
1460
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M470L1714ET0 [ (8M x 16) * 8, 128MB Non ECC Module ]
(VDD=2.7V, T = 10°C)
Symbol
IDD0
B3(DDR333@CL=2.5)
A2(DDR266@CL=2)
B0(DDR266@CL=2.5)
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
1100
1220
24
960
1080
24
960
1080
24
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
520
440
440
960
1500
1480
1320
24
480
400
400
840
1340
1280
1200
24
480
400
400
840
1340
1280
1200
24
IDD6
Normal
Low power
IDD7A
8
8
8
Optional
2060
1880
1880
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
AC Operating Conditions
Max
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
Unit
V
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VREF + 0.31
3
3
1
2
VREF - 0.31
VDDQ+0.6
V
0.7
V
Input Crossing Point Voltage, CK and CK inputs
0.5*VDDQ-0.2 0.5*VDDQ+0.2
V
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
M470L0914ET0
Min Max
41 45
M470L1714ETM
Unit
Parameter
Symbol
Min
49
34
34
34
10
10
10
Max
57
38
38
38
12
12
12
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS,WE )
Input capacitance(CKE0, CKE1)
CIN1
CIN2
CIN3
CIN4
CIN5
Cout1
Cout2
pF
pF
pF
pF
pF
pF
pF
34
34
24
6
38
38
28
7
Input capacitance(CS0, CS1)
Input capacitance( CLK0, CLK1,CLK2)
Input capacitance(DM0~DM7)
Data & DQS input/output capacitance(DQ0~DQ63)
Data input/output capacitance (CB0~CB7)
6
7
6
7
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
AC Timming Parameters & Specifications
B3
A2
B0
(DDR266@CL=2.5))
(DDR333@CL=2.5))
(DDR266@CL=2.0)
Parameter
Symbol
Unit
Note
Min
60
Max
Min
65
Max
Min
65
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
Refresh row cycle time
Row active time
72
75
75
42
70K
45
120K
45
120K
ns
RAS to CAS delay
18
20
20
ns
Row precharge time
18
20
20
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
12
15
15
ns
15
15
15
ns
Last data in to Read command
Col. address to Col. address delay
tWTR
tCCD
1
1
1
tCK
tCK
ns
1
1
1
CL=2.0
CL=2.5
7.5
6
12
7.5
7.5
0.45
0.45
-0.75
-0.75
-
12
12
10
12
12
Clock cycle time
tCK
12
7.5
0.45
0.45
-0.75
-0.75
-
ns
Clock high level width
tCH
tCL
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.55
0.55
+0.75
+0.75
0.5
0.55
0.55
+0.75
+0.75
0.5
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
tDQSCK
tAC
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
ns
12
3
0.9
0.4
0.75
0
0.9
0.4
0.75
0
1.1
0.9
0.4
0.75
0
1.1
tCK
tCK
tCK
ns
Read Postamble
0.6
0.6
0.6
CK to valid DQS-in
1.25
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.35
0.9
0.75
0.75
0.8
0.8
-0.7
-0.7
0.5
0.5
1.0
0.67
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
-0.75
-0.75
0.5
0.5
1.0
0.67
0.25
0.2
0.2
0.35
0.35
0.9
0.9
0.9
1.0
1.0
-0.75
-0.75
0.5
0.5
1.0
0.67
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
1.1
1.1
1.1
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
i,5.7~9
i,5.7~9
i, 6~9
i, 6~9
1
tIH
ns
tIS
ns
tIH
ns
tHZ
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
ns
tLZ
ns
1
tSL(I)
tSL(IO)
tSL(O)
tSLMR
V/ns
V/ns
V/ns
Output Slew Rate(x4,x8)
4.5
1.5
4.5
1.5
4.5
1.5
Output Slew Rate Matching Ratio(rise to fall)
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
B3
AA
A2
B0
(DDR333@CL=2.5)) (DDR266@CL=2.0) (DDR266@CL=2.0) (DDR266@CL=2.5))
Parameter
Symbol
Unit
Note
Min
12
Max
Min
15
Max
Min
15
Max
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tMRD
tDS
15
ns
ns
ns
0.45
0.5
0.5
0.5
j, k
j, k
tDH
0.45
0.5
0.5
0.5
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
tIPW
tDIPW
tPDEX
tXSNR
tXSRD
tREFI
2.2
1.75
6
2.2
1.75
7.5
2.2
1.75
7.5
2.2
1.75
7.5
ns
ns
8
8
ns
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
75
75
75
75
ns
200
200
200
200
tCK
us
15.6
-
15.6
-
15.6
-
15.6
-
4
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
ns
ns
11
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
-
10, 11
Data hold skew factor
tQHS
0.55
0.6
0.75
0.6
0.75
0.6
0.75
0.6
ns
11
2
DQS write postamble time
tWPST
0.4
18
0.4
20
0.4
20
0.4
20
tCK
Active to Read with Auto precharge
command
tRAP
Autoprecharge write recovery +
Precharge time
(tWR/tCK)
+
(tWR/tCK)
+
(tWR/tCK)
+
(tWR/tCK)
+
tDAL
tCK
13
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
(tRP/tCK)
System Characteristics for DDR SDRAM
The following specification parameters are required in systems using DDR333& DDR266 devices to ensure proper system
performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS
DDR333
DDR266
PARAMETER
SYMBOL
DCSLEW
MIN
TBD
MAX
TBD
MIN
TBD
MAX
TBD
Units
V/ns
Notes
a, m
DQ/DM/DQS input slew rate measured between
VIH(DC), VIL(DC) and VIL(DC), VIH(DC)
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tIS
0
tIH
0
Units
ps
Notes
i
i
i
0.4 V/ns
+50
+100
0
ps
0.3 V/ns
0
ps
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate
0.5 V/ns
tDS
0
tDH
0
Units
ps
Notes
k
k
k
0.4 V/ns
+75
+150
+75
+150
ps
0.3 V/ns
ps
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate
+/- 0.0 V/ns
tDS
0
tDH
0
Units
ps
Notes
j
j
j
+/- 0.25 V/ns
+/- 0.5 V/ns
+50
+100
+50
+100
ps
ps
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
1.0
1.0
4.5
4.5
a,c,d,f,g,h
b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Typical Range
(V/ns)
Minimum
(V/ns)
Maximum
(V/ns)
Slew Rate Characteristic
Notes
Pullup Slew Rate
Pulldown slew
1.2 ~ 2.5
1.2 ~ 2.5
0.7
0.7
5.0
5.0
a,c,d,f,g,h
b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS DDR333
DDR266
PARAMETER
Output Slew Rate Matching Ratio (Pullup to Pulldown)
MIN
TBD
MAX
TBD
MIN
TBD
MAX
TBD
Notes
e,m
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
Component Notes
1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a
specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
tem performance (bus turnaround) will degrade accordingly.
3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
5. For command/address input slew rate ≥ 1.0 V/ns
6. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
7. For CK & CK slew rate ≥ 1.0 V/ns
8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
device design or tester correlation.
9. Slew Rate is measured between VOH(ac) and VOL(ac).
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
11. tQH = tHP - tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
12. tDQSQ
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given
cycle.
13. tDAL = (tWR/tCK) + (tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
Test point
Output
50Ω
VSSQ
Figure 1 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 2.
VDDQ
50Ω
Output
Test point
Figure 2 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)
Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output
switching.
Example : For typical slew rate, DQ0 is switching
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
d. Evaluation conditions
Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process
Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process
Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and
voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns
as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or
VIH(DC) to VIL(DC), similarly for rising transitions.
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4.
Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the
slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.
The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotony.
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
Command Truth Table
A0 ~ A9
A11
COMMAND
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
V
V
Row Address
L
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
4
4
Column
Address
L
H
L
H
H
L
Column
Address
Write &
Column Address
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
Units : Inches (Millimeters)
Full R 2x
Physical Dimensions : 8M x64 (M470L0914ET0)
2.70
(67.60)
2.50
(63.60)
0.16 ± 0.039
(4.00 ± 0.10)
1
39 41
199
0.086
2.15
0.456
11.40
1.896
(47.40)
2-φ 0.07
(1.80)
0.17
(4.20)
0.096
(2.40)
0.07
(1.8)
Z
Y
0.098
2.45
2
40 42
200
0.150 Max
(3.80 Max)
0.018 ± 0.001
(0.45 ± 0.03)
0.16 ± 0.0039
(4.00 ± 0.10)
0.01
(0.25)
0.04 ± 0.0039
(1.00 ± 0.1)
0.024 TYP
(0.60 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 8Mx16 SDRAM, TSOPII
SDRAM Part No. : K4H281638E-T***
Rev. 1.4 March. 2004
64MB, 128MB Unbuffered SODIMM
DDR SDRAM
Units : Inches (Millimeters)
Full R 2x
Physical Dimensions : 16M x64 (M470L1714ET0)
2.70
(67.60)
2.50
(63.60)
0.16 ± 0.039
(4.00 ± 0.10)
1
39 41
199
0.086
2.15
0.456
11.40
1.896
(47.40)
2-φ 0.07
(1.80)
0.17
(4.20)
0.096
(2.40)
0.07
(1.8)
Z
Y
0.098
2.45
2
40 42
200
0.150 Max
(3.80 Max)
0.018 ± 0.001
(0.45 ± 0.03)
0.16 ± 0.0039
(4.00 ± 0.10)
0.01
(0.25)
0.04 ± 0.0039
(1.00 ± 0.1)
0.024 TYP
(0.60 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used devices are 8Mx16 DDR SDRAM, TSOPII.
DDR SDRAM Part No. : K4H281638E-T***
Rev. 1.4 March. 2004
相关型号：
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