M470L1713BT0-CA2 [SAMSUNG]
DDR DRAM Module, 16MX64, 0.75ns, CMOS, SODIMM-200;
| 型号： | M470L1713BT0-CA2 |
| 厂家： | 
SAMSUNG |
| 描述： | DDR DRAM Module, 16MX64, 0.75ns, CMOS, SODIMM-200 时钟 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总14页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
200pin DDR SDRAM SODIMM
M470L1713BT0
128MB DDR SDRAM MODULE
(16Mx64 based on 16Mx 8 DDR SDRAM)
200pin SODIMM
64bit Non-ECC/Parity
Revision 0.1
June. 2001
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
Revision History
Revision 0.0 (Apr. 2001)
1. First release.
Revision 0.1 (June. 2001)
1. Changed module current speificaton
2. Changed typo size on module PCB in package dimesions. (from 2.6mm to 3mm).
3. Changed AC parameter table.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
M470L1713BT0 200pin DDR SDRAM SODIMM
16Mx64 200pin DDR SDRAM SODIMM based on 16Mx8
FEATURE
GENERAL DESCRIPTION
• Performance range
The Samsung M470L1713BT0 is 16M bit x 64 Double Data
Rate SDRAM high density memory modules based on first gen
of 128Mb DDR SDRAM respectively.
Part No.
Max Freq.
Interface
M470L1713BT0-C(L)A2 133MHz(7.5ns@CL=2)
M470L1713BT0-C(L)B0 133MHz(7.5ns@CL=2.5)
SSTL_2
The Samsung M470L1713BT0 consists of eight CMOS 16M x
8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-
II(400mil) packages mounted on a 200pin glass-epoxy sub-
strate. Four 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each DDR SDRAM.
The M470L1713BT0 is Dual In-line Memory Modules and
intended for mounting into 200pin edge connector sockets.
Synchronous design allows precise cycle control with the use
of system clock. Data I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable
latencies and burst lengths allow the same device to be useful
for a variety of high bandwidth, high performance memory sys-
tem applications.
100MHz(10ns@CL=2)
M470L1713BT0-C(L)A0
• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe(DQS)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency 2, 2.5 (clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 15.6us refresh interval(4K/64ms refresh)
• Serial presence detect with EEPROM
• PCB:Height1250(mil),double sided component
PIN DESCRIPTION
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin
Front Pin
Front
Pin Back
Pin
Back
Pin
Back
Pin Name
A0 ~ A11
Function
Address input (Multiplexed)
Bank Select Address
Data input/output
1
3
5
7
9
VREF
VSS
DQ0
DQ1
VDD
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
DQ27 135
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
2
4
6
8
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
68
70
72
74
76
78
80
82
84
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
136 DQ38
138 VSS
140 DQ39
142 DQ44
144
146 DQ45
148
150
VDD
CB0
CB1
VSS
137
139
141
143
BA0 ~ BA1
DQ0 ~ DQ63
DQS0 ~ DQS7
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VDD
Data Strobe input/output
11 DQS0
DQS8 145
13
15
17
19
21
23
DQ2
VSS
DQ3
DQ8
VDD
DQ9
CB2
VDD
CB3
DU
VSS
CK2
/CK2
VDD
147
149
151
153
155
157
159
161
DM5
VSS
CK0~ CK2,
CK0~ CK2
Clock input
152 DQ46
86 DU/(RESET) 154 DQ47
88
90
92
94
CKE0
CS0
Clock enable input
Chip select input
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
/RAS
/CAS
/S1
156
158
160
162
164 DQ52
166 DQ53
168
170
172 DQ54
174 VSS
176 DQ55
178 DQ60
180
182 DQ61
184
186
188 DQ62
190 DQ63
VDD
/CK1
CK1
VSS
VDD
VSS
VSS
25 DQS1
27 VSS
29 DQ10
31 DQ11
RAS
Row address strobe
Column address strobe
Write enable
CKE1 163
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
96
98
CAS
97 DU(A13) 165
WE
33
35
37
39
VDD
CK0
/CK0
VSS
99
A12
A9
VSS
A7
A5
A3
167
169
171
173
175
177
179
181
100
102
104
106
108
VDD
DM6
101
103
105
107
DM0 ~ DM7
VDD
Data - in mask
Power supply (2.5V)
Power Supply for DQS(2.5V)
Ground
Key
Key
VDDQ
VSS
41 DQ16 109
43 DQ17 111
42
44
46
48
50
52
54
56
58
60
DQ20 110
DQ21 112
VDD
DM2
DQ22 118
VSS 120
DQ23 122
DQ28 124
A1
VDD
VDD
45
VDD
113
114
116
VREF
VDDSPD
Power supply for reference
47 DQS2 115 A10/AP 183
49 DQ18 117
51 VSS 119
53 DQ19 121
55 DQ24 123
DM7
VSS
BA0
/WE
/S0
DU
VSS
185
187
189
191
193
Serial EEPROM Power
Supply (2.3V to 3.6V)
DU
192
194
196
198
200
VDD
SA0
SA1
SA2
DU
SDA
Serial data I/O
57
VDD
125
VDD
DQ29 128
126
VSS
DQ36
DQ37
VDD
DM4
59 DQ25 127 DQ32 195
61 DQS3 129 DQ33 197 VDDSPD 62
SCL
Serial clock
DM3
VSS
DQ30 134
130
132
SA0 ~ 2
VDDID
NC
Address in EEPROM
VDD identification flag
No connection
63
VSS
131
VDD
199 VDDID
64
66
65 DQ26 133 DQS4
*
These pins are not used in this module.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
FUNCTIONAL BLOCK DIAGRAM
S0
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DM
DQS4
DM4
DQS
DM
S
S
DQ32
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
D4
DQS1
DM1
DQ8
DQS
DM
DQS5
DM5
DQ40
DQS
DM
S
S
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQ9
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D5
DQS2
DM2
DQS
DM
DQS6
DM6
DQ48
DQS
DM
S
S
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
Clock Wiring
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
Clock
Input
SDRAMs
D2
D6
CK0/CK0
CK1/CK1
CK2/CK2
4 SDRAMs
4 SDRAMs
NC
Serial PD
SCL
WP
SDA
DQS3
DM3
DQS
DM
DQS7
DM7
DQ56
DQS
DM
A0
A1
A2
S
S
SA0 SA1 SA2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
I/0 0
I/0 1
I/0 2
I/0 3
I/0 4
I/0 5
I/0 6
I/0 7
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
D7
Dram1
R=120W
± 5%
Dram2
Dram3
CK
CK
Card
Edge
*Clock Net Wiring
Dram4
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/CS relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
V
DDSPD
BA0 - BA1
A0 - A13
RAS
BA0-BA1: DDR SDRAMs D0 - D7
A0-A13: DDR SDRAMs D0 - D7
RAS: SDRAMs D0 - D7
SPD
V
/V
DD DDQ
D0 - D7
D0 - D7
4. VDDID strap connections
VREF
CAS
CAS: SDRAMs D0 - D7
D0 - D7
D0 - D7
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
STRAP IN (VSS): VDD ¹ VDDQ.
V
CKE0
WE
CKE: SDRAMs D0 - D7
SS
V
WE: SDRAMs D0 - D7
DDID
Strap: see Note 4
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Voltage on VDDQ supply relative to Vss
Storage temperature
Symbol
VIN, VOUT
VDD
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
8
Unit
V
V
V
VDDQ
TSTG
°C
W
Power dissipation
PD
Short circuit current
IOS
50
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70°C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V)
I/O Supply voltage
Symbol
VDD
Min
2.3
Max
2.7
Unit
Note
VDDQ
VREF
2.3
2.7
V
V
I/O Reference voltage
VDDQ/2-50mV VDDQ/2+50mV
1
2
4
4
I/O Termination voltage(system)
Input logic high voltage
V
VREF-0.04
VREF+0.04
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6
1.35
V
TT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
II
VREF+0.15
-0.3
-0.3
0.3
V
Input logic low voltage
V
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
Input crossing point voltage, CK and CK inputs
Input leakage current
V
V
3
5
1.15
-2
V
2
uA
uA
Output leakage current
IOZ
-5
5
Output High Current(Normal strengh driver)
IOH
IOL
IOH
-16.8
16.8
-9
mA
mA
mA
mA
;V
= V + 0.84V
OUT
TT
Output High Current(Normal strengh driver)
;V = V - 0.84V
OUT
TT
Output High Current(Half strengh driver)
;V = V + 0.45V
OUT
TT
Output High Current(Half strengh driver)
;V = V - 0.45V
IOL
9
OUT
TT
Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled
TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.
2.V is not applied directly to the device. V is a system supply for signal termination resistors, is expected to be set equal to
TT
TT
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
DDR SDRAM SPEC Items and Test Conditions
Recommended operating conditions Unless Otherwise Noted, TA=0 to 70°C)
Conditions
Symbol
IDD0
Typical
Worst
Operating current - One bank Active-Precharge;
-
-
tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
IDD1
-
-
-
-
Percharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD2P
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
IDD2F
IDD2Q
-
-
-
-
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
IDD3P
IDD3N
-
-
-
-
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once
per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst;
One bank active; address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =
133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A
IDD4R
IDD4W
-
-
-
-
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,
CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh
IDD5
-
-
-
-
-
-
Self refresh current; CKE =< 0.2V; External clock should be on;
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B
IDD6
Orerating current - Four bank operation ; Four bank interleaving with BL=4
IDD7A
-Refer to the following page for detailed test condition
Typical case: VDD = 2.5V, T = 25’C
Worst case : VDD = 2.7V, T = 10’C
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
DDR SDRAM module I spec table
DD
A2(DDR266@CL=2)
Symbol
B0(DDR266@CL=2.5)
A0(DDR200@CL=2)
Unit
Notes
typical
800
worst
880
1120
240
440
320
280
480
1600
1720
1720
16
typical
800
worst
880
1120
240
440
320
280
480
1600
1720
1720
16
typical
640
800
160
320
240
200
320
1120
1200
1200
16
worst
720
920
200
360
280
240
400
1320
1360
1360
16
IDD0
IDD1
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1000
200
1000
200
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
360
360
280
280
240
240
400
400
1360
1480
1480
16
1360
1480
1480
16
Normal
Low power
IDD7A
IDD6
8
8
8
8
8
8
Optional
2600
3000
2600
3000
2120
2480
* Module I
was calculated on the basis of component I
DD
and can be differently measured according to DQ loading cap.
DD
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
IDD7A : Operating current: Four bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
*100% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
AC Operating Conditions
Max
Parameter/Condition
Symbol
Min
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
VIH(AC) VREF + 0.31
VIL(AC)
V
V
V
V
3
3
1
2
VREF - 0.31
VDDQ+0.6
VID(AC) 0.7
Input Crossing Point Voltage, CK and CK inputs
VIX(AC) 0.5*VDDQ-0.2
0.5*VDDQ+0.2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of V is expected to equal 0.5*V of the transmitting device and must track variations in the DC level of the same.
IX
DDQ
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula-
tion. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
AC OPERATING TEST CONDITIONS (VDD=2.5V, VDDQ=2.5V, TA= 0 to 70°C)
Parameter
Value
Unit
Note
Input reference voltage for Clock
0.5 * VDDQ
V
Input signal maximum peak swing
Input Levels(VIH/VIL)
1.5
VREF+0.31/VREF-0.31
VREF
V
V
V
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
Vtt
See Load Circuit
Vtt=0.5*VDDQ
RT=50W
Output
Z0=50W
VREF
=0.5*VDDQ
CLOAD=30pF
Output Load Circuit (SSTL_2)
Input/Output CAPACITANCE (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance(A0 ~ A11, BA0 ~ BA1,RAS,CAS, WE )
CIN1
36
44
44
42
38
pF
pF
pF
pF
Input capacitance(CKE0)
Input capacitance( CS0 )
CIN2
CIN3
CIN4
36
34
34
Input capacitance( CLK0, CLK1)
Data & DQS input/output capacitance(DQ0~DQ63)
Input capacitance(DM0~DM8)
COUT
CIN5
8
8
9
9
pF
pF
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)
-TCA2(DDR266A) -TCB0(DDR266B) -TCA0 (DDR200)
Parameter
Symbol
Unit
Note
Min
65
Max
Min
65
Max
Min
70
80
48
20
20
15
2
Max
Row cycle time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
Refresh row cycle time
Row active time
75
75
45
120K
45
120K
120K
ns
RAS to CAS delay
20
20
ns
Row precharge time
20
20
ns
Row active to Row active delay
Write recovery time
tRRD
tWR
15
15
ns
2
2
tCK
tCK
tCK
ns
Last data in to Read command
Col. address to Col. address delay
tCDLR
tCCD
1
1
1
1
1
1
CL=2.0
CL=2.5
7.5
7.5
0.45
0.45
-0.75
-0.75
-
12
12
10
12
12
10
12
5
5
Clock cycle time
tCK
7.5
0.45
0.45
-0.75
-0.75
-
12
ns
Clock high level width
tCH
tCL
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.55
0.55
+0.75
+0.75
+0.5
1.1
0.45
0.45
-0.8
-0.8
-
0.55
0.55
+0.8
+0.8
+0.6
1.1
tCK
tCK
ns
Clock low level width
DQS-out access time from CK/CK
tDQSCK
tAC
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
ns
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tDSS
ns
5
2
0.9
0.4
0.75
0
0.9
0.4
0.75
0
0.9
0.4
0.75
0
tCK
tCK
tCK
ns
Read Postamble
0.6
0.6
0.6
CK to valid DQS-in
1.25
1.25
1.25
DQS-in setup time
DQS-in hold time
0.25
0.2
0.2
0.35
0.25
0.2
0.2
0.35
0.25
0.2
0.2
0.35
tCK
tCK
tCK
tCK
tCK
tCK
ns
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
tDSH
tDQSH
DQS-in low level width
tDQSL
tDSC
tIS
0.35
0.9
0.9
0.9
0.35
0.9
0.9
0.9
0.35
0.9
DQS-in cycle time
1.1
1.1
1.1
Address and Control Input setup time
Address and Control Input hold time
Data-out high impedence time from CK/CK
1.1
6
6
tIH
1.1
ns
tHZ
tACmin- tACmax tACmin tACmax tACmin tACmax
400ps - 400ps - 400ps - 400ps - 400ps - 400ps
ps
ps
Data-out low impedence time from CK/CK
tLZ
tACmin- tACmax tACmin tACmax tACmin tACmax
400ps
- 400ps - 400ps - 400ps - 400ps - 400ps
Input Slew Rate(for input only pins)
Input Slew Rate(for I/O pins)
Output Slew Rate(x4,x8)
tSL(I)
tSL(IO)
tSL(O)
0.5
0.5
0.5
1.0
0.7
0.5
0.5
1.0
0.7
V/ns
V/ns
V/ns
V/ns
6
7
0.5
1.0
4.5
5
4.5
5
4.5
5
10
10
Output Slew Rate(x16)
tSL
0.7
(O)
Output Slew Rate Matching Ratio(rise to fall)
t
0.67
1.5
0.67
1.5
0.67
1.5
SLMR
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
-TCA2(DDR266A)
-TCB0(DDR266B)
-TCA0 (DDR200)
Parameter
Symbol
Unit Note
Min
15
Max
Min
15
Max
Min
16
Max
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
tMRD
tDS
ns
0.5
0.5
1.75
10
0.5
0.5
1.75
10
0.6
0.6
2
ns
ns
7,8,9
7,8,9
tDH
DQ & DM input pulse width
tDIPW
tPDEX
tXSW
tXSA
ns
ns
Power down exit time
10
Exit self refresh to write command
Exit self refresh to bank active command
Exit self refresh to read command
95
116
80
ns
75
75
200
15.6
7.8
ns
4
tXSR
tREF
200
15.6
7.8
200
15.6
7.8
Cycle
us
64Mb, 128Mb
Refresh interval time
256Mb
1
1
us
tHPmin
-tQHS
tHPmin
-tQHS
tHPmin
-tQHS
Output DQS valid window
Clock half period
tQH
tHP
-
-
-
ns
ns
5
tCLmin
or tCHmin
tCLmin
or tCHmin
tCLmin
or tCHmin
-
-
-
Data hold skew factor
tQHS
0.75
0.75
0.8
ns
DQS write postamble time
tWPST
0.25
0.25
0.25
tCK
3
Note : 1. Maximum burst refresh of 8
2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from
High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress,
DQS could be High at this time, depending on tDQSS.
3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter,
but system performance (bus turnaround) will degrade accordingly.
4. A write command can be applied with tRCD satisfied after this command.
5. For registered DINNs, tCL and tCH are ³ 45% of the period including both the half period jitter (tJIT(HP)) of the PLL and the half
period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
6. Input Setup/Hold Slew Rate Derating
Input Setup/Hold Slew Rate
DtIS
(ps)
0
DtIH
(ps)
0
(V/ns)
0.5
0.4
+50
+100
+50
+100
0.3
This derating table is used to increase t /t in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate
IS IH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
7. I/O Setup/Hold Slew Rate Derating
I/O Setup/Hold Slew Rate
DtDS
(ps)
0
DtDH
(ps)
0
(V/ns)
0.5
0.4
+75
+150
+75
+150
0.3
This derating table is used to increase t /t in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate
DS DH
based on the lesser of AC-AC slew rate and DC-DC slew rate.
8. I/O Setup/Hold Plateau Derating
I/O Input Level
(mV)
DtDS
(ps)
DtDH
(ps)
± 280
+50
+50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of
up to 2ns.
9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating
Delta Rise/Fall Rate
DtDS
(ps)
0
DtDH
(ps)
0
(ns/V)
0
±0.25
±0.5
+50
+100
+50
+100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate
is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall
Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate.
10. This parameter is fir system simulation purpose. It is guranteed by design.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
Command Truth Table
COMMAND
(V=Valid, X=Don¢t Care, H=Logic High, L=Logic Low)
A11
A9 ~ A0
CKEn-1
CKEn
CS
RAS
CAS
WE
BA0,1
A10/AP
Note
Register
Register
Extended MRS
H
H
X
X
H
L
L
L
L
L
L
L
L
L
OP CODE
OP CODE
1, 2
1, 2
3
Mode Register Set
Auto Refresh
H
L
L
L
H
X
X
Entry
3
Refresh
Self
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
3
Exit
L
H
H
H
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Column
Address
(A0~A8)
Read &
Column Address
Auto Precharge Disable
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
L
H
L
4
4
L
H
L
H
Column
Address
(A0~A8)
Write &
Column Address
4
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
V
H
4, 6
7
Burst Stop
Precharge
X
Bank Selection
All Banks
V
X
L
X
H
5
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Entry
Exit
H
L
L
H
L
Active Power Down
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
H
H
X
DM
X
X
8
9
9
H
L
X
H
X
H
No operation (NOP) : Not defined
Note : 1. OP Code : Operand Code. A0 ~ A11 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)
2. EMRS/ MRS can be issued only at all banks precharge state.
A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.
6. During burst write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.1 June. 2001
200pin DDR SDRAM SODIMM
M470L1713BT0
PACKAGE DIMENSIONS
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
Full R 2x
0.16 ± 0.039
(4.00 ± 0.10)
1
39 41
199
0.086
2.15
0.456
11.40
1.896
(47.40)
2-f 0.07
(1.80)
0.17
(4.20)
0.096
(2.40)
0.07
(1.8)
Z
Y
0.098
2.45
2
40 42
200
0.150 Max
(3.80 Max)
0.018 ± 0.001
(0.45 ± 0.03)
0.16 ± 0.0039
(4.00 ± 0.10)
0.01
(0.25)
0.04 ± 0.0039
(1.00 ± 0.1)
0.024 TYP
(0.60 TYP)
0.04 ± 0.0039
(1.00 ± 0.10)
Detail Z
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
The used device is 16Mx8 SDRAM, TSOP
SDRAM Part No. : K4H280838B-TC/L
Rev. 0.1 June. 2001
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